- 15 Jan, 2020 40 commits
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Ben Skeggs authored
This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GP107/GP108 FWs have interface differences. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
It serves the exact same purpose. Signed-off-by: -
Ben Skeggs authored
This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: -
Ben Skeggs authored
This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: -
Ben Skeggs authored
ACR LS FW loading is moving out of SECBOOT and into their specific subdevs, and the available GM20B/GP10B FWs have interface differences. Signed-off-by: -
Ben Skeggs authored
This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: -
Ben Skeggs authored
This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
PMU, SEC2 and GR will be modified to register their falcons with ACR before the main commit switching everything over. Signed-off-by: -
Ben Skeggs authored
This will replace the current SECBOOT subdev for handling firmware on secure falcons. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Will be used in upcoming commits to allow subdevs to better customise themselves based on which (if any) firmware is available. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
These will be used in upcoming commits which will provide more customisation. Signed-off-by: -
Ben Skeggs authored
Shortcut to avoid each subdev having to do this itself. Signed-off-by: -
Ben Skeggs authored
We want to be able to register falcons with ACR during the constructor for the subdev it belongs to, however, we may not have access to the falcon's registers prior to DEVINIT. Delay touching registers until the first time the falcon is acquired. This may temporarily break secboot on non-production boards due to not being able to determine whether the falcon is in debug or production mode, the new ACR subdev will not have this issue, and it's not a use-case that's terribly important for bisectability. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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YueHaibing authored
drivers/gpu/drm/nouveau/nouveau_ttm.c: In function nouveau_vram_manager_new: drivers/gpu/drm/nouveau/nouveau_ttm.c:66:22: warning: variable mem set but not used [-Wunused-but-set-variable] drivers/gpu/drm/nouveau/nouveau_ttm.c: In function nouveau_gart_manager_new: drivers/gpu/drm/nouveau/nouveau_ttm.c:106:22: warning: variable mem set but not used [-Wunused-but-set-variable] They are not used any more, so remove it. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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YueHaibing authored
Like other cases, it should use rcu protected 'chan' rather than 'fence->channel' in nouveau_fence_wait_uevent_handler. Fixes: 0ec5f02f ("drm/nouveau: prevent stale fence->channel pointers, and protect with rcu") Signed-off-by:
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Ben Skeggs authored
Will be used as a basis for implementing changes needed for Turing. Signed-off-by: -
Ben Skeggs authored
Method init is typically ordered by class in the FW image as ThreeD, TwoD, Compute. Due to a bug in parsing the FW into our internal format, we've been accidentally sending Twod + Compute methods to the ThreeD class, as well as Compute methods to the TwoD class - oops. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Dan Carpenter authored
We accidentally set "psb" which is a no-op instead of "*psb" so it generates a static checker warning. We should probably set it before the first error return so that it's always initialized. Fixes: 923f1bd2 ("drm/nouveau/secboot/gm20b: add secure boot support") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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James Jones authored
Turing introduced a new simplified page kind scheme, reducing the number of possible page kinds from 256 to 16. It also is the first NVIDIA GPU in which the highest possible page kind value is not reserved as an "invalid" page kind. To address this, the invalid page kind is made an explicit property of the MMU HAL, and a new table of page kinds is added to the tu102 MMU HAL. One hardware change not addressed here is that 0x00 is technically no longer a supported page kind, and pitch surfaces are instead intended to share the block-linear generic page kind 0x06. However, because that will be a rather invasive change to nouveau and 0x00 still works fine in practice on Turing hardware, addressing this new behavior is deferred. Signed-off-by:
James Jones <jajones@nvidia.com> Signed-off-by:
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James Jones authored
The pointer used to walk the table of move ops and pick the right one for the current GPU was declared static, meaning its state was carried over between invocations of the function, and also made the function non-rentrant and thread-unsafe. Since the table is ordered such that newer GPU methods are listed first, the result of this was that initializing newer GPUs after older GPUs would result in no suitable ttm move acceleration operations being found, and ttm would fall back to CPU blits on the older GPUs. This change declares the walking pointer separately from the table and makes it non-static to fix the logic. Signed-off-by:
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Wambui Karuga authored
Replace the use of 0 in the pointer assignment with NULL to address the following sparse warning: drivers/gpu/drm/nouveau/nouveau_hwmon.c:744:29: warning: Using plain integer as NULL pointer Signed-off-by:
Wambui Karuga <wambui.karugax@gmail.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Wambui Karuga authored
The local variable `pclks` is defined and set but not used and can therefore be removed. Issue found by coccinelle. Signed-off-by:
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Wambui Karuga authored
Explicitly declare constants as unsigned long long to address the following sparse warnings: warning: constant is so big it is long v2: convert to unsigned long long for compatibility with 32-bit architectures. Signed-off-by:
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YueHaibing authored
match_string() returns the array index of a matching string. Use it instead of the open-coded implementation. Signed-off-by:
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Thierry Reding authored
gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine class because on gp10b the PASCAL_DMA_COPY_B class is not supported. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Thierry Reding authored
There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by:
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Thierry Reding authored
The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by:
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Thierry Reding authored
If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by:
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