- 06 Feb, 2024 40 commits
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Manivannan Sadhasivam authored
QMP PHY used in SM8150 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 3834a2e9 ("arm64: dts: qcom: sm8150: Add ufs nodes") Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-11-58a49d2f4605@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Manivannan Sadhasivam authored
QMP PHY used in SM6350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 5a814af5 ("arm64: dts: qcom: sm6350: Add UFS nodes") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM6125 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: f8399e8a ("arm64: dts: qcom: sm6125: Add UFS nodes") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM6115 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 97e563bf ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SDM845 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: cc16687f ("arm64: dts: qcom: sdm845: add UFS controller") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in MSM8998 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: cd3dbe2a ("arm64: dts: qcom: msm8998: Add UFS nodes") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in MSM8996 requires 2 clocks: * ref - 19.2MHz reference clock from RPM * qref - QREF clock from GCC Fixes: 27520210 ("arm64: dts: qcom: msm8996: Use generic QMP driver for UFS") Reviewed-by:
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Christian Marangi authored
Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead of using the default value of 390KHz from MDIO default divider. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
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Dmitry Baryshkov authored
If cluster domain idle state is enabled on the RB1, the board becomes significantly less responsive. Under certain circumstances (if some of the devices are disabled in kernel config) the board can even lock up. It seems this is caused by the MPM not updating wakeup timer during CPU idle (in the same way the RPMh updates it when cluster idle state is entered). Disable cluster domain idle for the RB1 board until MPM driver is fixed to cooperate with the CPU idle states. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240130-rb1-suspend-cluster-v2-1-5bc1109b0869@linaro.orgSigned-off-by:
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Vladimir Lypak authored
Add the GPU node for the Adreno 506 found on this family of SoCs. The clock speeds are a bit different per SoC variant, SDM450 maxes out at 600MHz while MSM8953 (= SDM625) goes up to 650MHz and SDM632 goes up to 725MHz. To achieve this, create a new sdm450.dtsi to hold the 600MHz OPP and use the new dtsi for sdm450-motorola-ali. Signed-off-by:
Vladimir Lypak <vladimir.lypak@gmail.com> Co-developed-by:
Luca Weiss <luca@z3ntu.xyz> Signed-off-by:
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Vladimir Lypak authored
Add the IOMMU used for the GPU on MSM8953. Signed-off-by:
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Vladimir Lypak authored
With this reset we can avoid situations like IRQ storms from DSI host before it even started probing (because boot-loader left DSI IRQs on). Signed-off-by:
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Bjorn Andersson authored
Merge MSM8953 GCC DeviceTree binding update from topic branch, to get access to newly introduced MDSS reset constants.
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Vladimir Lypak authored
Add new defines for some more BCRs found on MSM8953. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Neil Armstrong authored
Add the sound card of SM8650-MTP board with the routing for Speakers. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-audio-dt-v1-2-c24d23ae5763@linaro.orgSigned-off-by:
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Neil Armstrong authored
Add the remaining Audio nodes on the SM8650-QRD board including: - Qualcomm Aqstic WCD9395 audio codec on the RX & TX Soundwire interfaces - WSA8845 Left & Right Speakers - Link the WCD9395 Codec node to the WCD9395 USB SubSystem node to handle the USB-C Audio Accessory Mode events & lane swapping - Sound card with routing for Speakers and Microphones Signed-off-by:
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Ling Xu authored
Add dma-coherent property to fastRPC context bank nodes to pass dma sequence test in fastrpc sanity test, ensure that data integrity is maintained during DMA operations. Signed-off-by:
Ling Xu <quic_lxu5@quicinc.com> Link: https://lore.kernel.org/r/20240125102413.3016-3-quic_lxu5@quicinc.comSigned-off-by:
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Ling Xu authored
Add dma-coherent property to fastRPC context bank nodes to pass dma sequence test in fastrpc sanity test, ensure that data integrity is maintained during DMA operations. Signed-off-by:
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Fenglin Wu authored
Add PM8010 regulator device nodes for sm8650-qrd board. Signed-off-by:
Fenglin Wu <quic_fenglinw@quicinc.com> Reviewed-by:
David Collins <quic_collinsd@quicinc.com> Link: https://lore.kernel.org/r/20240125-sm8650_pm8010_support-v3-2-2f291242a7c4@quicinc.comSigned-off-by:
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Fenglin Wu authored
Add PM8010 regulator device nodes for sm8650-mtp board. Signed-off-by:
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Mantas Pucka authored
Add thermal zones to make use of thermal sensors data. For CPU zone, add cooling device that uses CPU frequency scaling. Signed-off-by:
Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.comSigned-off-by:
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Mantas Pucka authored
IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add node for it. Signed-off-by:
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Krzysztof Kozlowski authored
Add proper audio routes for onboard analogue microphones AMIC[1345] - MIC biases and route from TX macro codec to WCD9385 audio codec. This should bring AMIC1, AMIC2 (headphones), AMIC3, AMIC4 and AMIC5 onboard microphones to work, although was not tested on the hardware. Signed-off-by:
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Krzysztof Kozlowski authored
Add proper audio routes for onboard analogue microphones AMIC[1345] - MIC biases and route from TX macro codec to WCD9385 audio codec. This finally brings AMIC1, AMIC3, AMIC4 and AMIC5 onboard microphones to work. AMIC2 (headphones) should be fine well, however it didn't work during tests, probably because of incomplete USB switch. Signed-off-by:
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Krzysztof Kozlowski authored
WCD9385 audio codec TX port mapping was copied form HDK8450, but in fact it is offset by one. Correct it to fix recording via analogue microphones. The change is based on QRD8550 and should be correct here as well, but was not tested on MTP8550. Cc: stable@vger.kernel.org Fixes: a541667c ("arm64: dts: qcom: sm8550-mtp: add WCD9385 audio-codec") Signed-off-by:
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Krzysztof Kozlowski authored
WCD9385 audio codec TX port mapping was copied form HDK8450, but in fact it is offset by one. Correct it to fix recording via analogue microphones. Cc: stable@vger.kernel.org Fixes: 83fae950 ("arm64: dts: qcom: sm8550-qrd: add WCD9385 audio-codec") Signed-off-by:
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Luca Weiss authored
Add the definitions for the various thermal zones found on the SM6350 SoC. Hooking up GPU and CPU cooling can limit the clock speeds there to reduce the temperature again to good levels. Most thermal zones only have one critical temperature configured at 125°C which can be mostly considered a placeholder until those zones can be hooked up to cooling. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240124-sm6350-tsens-v1-1-d37ec82140af@fairphone.comSigned-off-by:
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Dmitry Baryshkov authored
The USB3 PHY on the SM6115 platform doesn't have built-in PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately via the register in the TCSR space. Declare corresponding register. Fixes: 9dd5f6db ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node") Signed-off-by:
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Dmitry Baryshkov authored
The USB3 PHY on the QCM2290 platform doesn't have built-in PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately via the register in the TCSR space. Declare corresponding register. Fixes: 0c55f622 ("arm64: dts: qcom: qcm2290: Add USB3 PHY") Signed-off-by:
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Dmitry Baryshkov authored
The USB3 PHY on the MSM8998 platform doesn't have built-in PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately via the register in the TCSR space. Declare corresponding register. Fixes: 026dad8f ("arm64: dts: qcom: msm8998: Add USB-related nodes") Cc: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-4-a950c223f10f@linaro.orgSigned-off-by:
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Maulik Shah authored
QCM6490 uses Trustzone as firmware whereas SC7280 uses arm trusted firmware. The PSCI suspend param and the number of domain-idle-states supported is different in Trustzone for cluster sleep. Move the arm trusted firmware supported domain-idle-states in chrome specific sc7280-chrome-common.dtsi and add the Trustzone supported sleep states as default domain-idle-states in sc7280.dtsi Signed-off-by:
Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20240109-qcm6490_cluster_sleep-v2-1-8f94f1ad188d@quicinc.comSigned-off-by:
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Marijn Suijten authored
The board-specific (electrical) configuration was removed from PM660L in 90ba636e ("arm64: dts: qcom: pm660l: Remove board-specific WLED configuration") as it is platform-dependent. We reintroduce it here in the Nile board configuration (with a slightly lower current limit, as per downstream DT sources) and enable it for use in the dsi0 node. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20240204-sdm630-nile-wled-v1-1-9f5c4f8147f2@somainline.orgSigned-off-by:
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Dmitry Baryshkov authored
The idea impressed in the commit b32e592d ("devicetree: bindings: Document qcom board compatible format") never got actually adopted. As can be seen from the existing board DT files, no device actually used the PMIC / foundry / version parts of the compatible string. Drop this compatibility string description to avoid possible confusion and keep just the generic terms and the SoC list. Fixes: b32e592d ("devicetree: bindings: Document qcom board compatible format") Signed-off-by:
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Neil Armstrong authored
The qlink_logging memory region is also used by the modem firmware, add it to the reserved memories and add it to the MPSS memory regions. Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Link: https://lore.kernel.org/r/20240123-topic-sm8650-upstream-remoteproc-v7-4-61283f50162f@linaro.orgSigned-off-by:
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Vignesh Viswanathan authored
Add Inline Crypto Engine reg and clocks in MMC node and enable CQE support as Inline Crypto Engine requires CQE to be enabled. Signed-off-by:
Vignesh Viswanathan <quic_viswanat@quicinc.com> Link: https://lore.kernel.org/r/20231215095339.3055554-1-quic_viswanat@quicinc.comSigned-off-by:
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Krzysztof Kozlowski authored
Add nodes for four WSA8845 speakers. Unlike previous boards like SM8550-QRD, this board has four speakers spread over two Soundwire buses instead of two speakers on one bus. Each pair of speakers shares the reset GPIO thus pinctrl property is only in one of them. Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX and TX. Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add nodes for LPASS Soundwire v2.0.0 controllers. Difference against SM8550: 1. Update port configs to match reference implementation, 2. LPASS TLMM GPIO14 is not used as WCD_SR_TX_DATA2 pin but as GPIO (camera). Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8650. The nodes are exactly the same as on SM8550 and SM8650. Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node as part of audio subsystem in Qualcomm X1E80100 SoC. Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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