- 23 Jun, 2023 26 commits
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Dmytro Laktyushkin authored
Correct setting is div by 2 for odm. Seamless odm transitions are enabled with enable_dp_dig_pixel_rate_div_policy debug flag. Fixes: a2c7356f ("drm/amd/display: fix pixel rate update sequence") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Fangzhi Zuo authored
When using debugfs to change MST link settings, we need to wait until the next stream update to apply the preferred link setting. So, trigger a hotplug event right after the preferred link setting is applied. Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Acked-by:
Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by:
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Leo Chen authored
[Why & How] Having seamless boot on while forcing debug option ODM combine 2 to 1 will cause some corruptions because of some missing programmings. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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Austin Zheng authored
Why: Limiting clocks to DC mode max results in some display modes to no longer be supported How: Disable the path that limits the clock values Fixes: 3b718dca ("drm/amd/display: Filter out AC mode frequencies on DC mode systems") Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Austin Zheng <austin.zheng@amd.com> Signed-off-by:
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Alvin Lee authored
The new fast update sequence is now supported on some ASICs. So, enable it by default for all applicable ASICs. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Alvin Lee authored
Clear update flags so the next flip does not have any redundant programming (if a subsequent flip does not have a stream or plane update, the update flags are not cleared). Fixes: 0baae624 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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Alvin Lee authored
Condition for programming manually trigger used the wrong pipe (always used top pipe instead of the one we are iterating through). Fixes: 0baae624 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Reviewed-by:
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Sridevi Arvindekar authored
[Why] We are currently missing some ABM registers. [How] Add the missing registers to dce_abm.h. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by:
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Austin Zheng authored
Why: Certain display configs resulted in underflow How: Add an entry containing all max DC clock timings Reviewed-by:
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Sung-huai Wang authored
[Why & How] We have to check if stream is properly initialized before calling find_matching_pll(), otherwise we might end up trying to deferecence a NULL pointer. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Sung-huai Wang <danny.wang@amd.com> Signed-off-by:
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Daniel Miess authored
This partially reverts commit de231189 ("drm/amd/display: Fix possible underflow for displays with large vblank"). [Why] The increased value of VBlankNomDefaultUS causes underflow at the desktop of an IP KVM setup [How] Change the value from 800 back to 668 Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Signed-off-by:
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Daniel Miess authored
This reverts commit e383b127. Controling hubp power gating using the DMCUB isn't stable so we are reverting this change to move control back into the driver. Cc: stable@vger.kernel.org # 6.3+ Reviewed-by:
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Daniel Miess authored
[Why] RCO is causing error messages on some DCN314 systems [How] Force disable RCO for DCN314 Fixes: 17fbdbda ("drm/amd/display: Enable dcn314 DPP RCO") Reviewed-by:
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Daniel Miess authored
[Why] Power gating is causing error messages on some DCN314 systems [How] Force disable power gating for DCN314 Fixes: 4cc1cebe ("drm/amd/display: Re-enable DPP/HUBP Power Gating") Reviewed-by:
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Zhigang Luo authored
For SRIOV VF, no TMR needed. Reviewed-by:
Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by:
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Nathan Chancellor authored
After commit 8020f0f9 ("drm/amd/amdgpu: enable W=1 for amdgpu"), there is an instance of -Wunused-const-variable when CONFIG_DEBUG_FS is disabled: drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.c:38:34: error: unused variable 'clocks' [-Werror,-Wunused-const-variable] 38 | static const struct cg_flag_name clocks[] = { | ^ 1 error generated. clocks is only used when CONFIG_DEBUG_FS is set, so move the definition into the CONFIG_DEBUG_FS block right above its only usage to clear up the warning. Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Evan Quan authored
Also, correct the comment for NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT as 0x0000000E stands for 400ms instead of 4ms. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Samuel Pitoiset authored
Per VM BOs must be marked as moved or otherwise their ranges are not updated on use which might be necessary when the replace operation splits mappings. This fixes random GPU hangs when replacing sparse mappings from the userspace, while OP_MAP/OP_UNMAP works fine because always valid BOs are correctly handled there. Cc: stable@vger.kernel.org Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Sierra authored
This flag determines whether the host possesses coherent access to the memory of the device. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Lijo Lazar authored
Not all devices carry VBIOS version information. Add the device attribute only if supported. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Alex Deucher authored
LPDDR5 channels are 32 bit rather than 64, report the width properly in the log. v2: Only LPDDR5 are 32 bits per channel. DDR5 is 64 bits per channel Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Nathan Chancellor authored
After commit 8020f0f9 ("drm/amd/amdgpu: enable W=1 for amdgpu"), there is an instance of -Wunused-const-variable when CONFIG_DEBUG_FS is disabled: drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c:110:37: error: unused variable 'amdgpu_rap_debugfs_ops' [-Werror,-Wunused-const-variable] 110 | static const struct file_operations amdgpu_rap_debugfs_ops = { | ^ 1 error generated. There is no reason for the body of this function to be guarded when CONFIG_DEBUG_FS is disabled, as debugfs_create_file() is a stub that just returns an error pointer in that situation. Remove the preprocessor guards so that the variable never appears unused, while not changing anything at run time. Signed-off-by:
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Mingtong Bao authored
fix the following coccicheck warning: drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c:1657:14-18: Unneeded variable: "size". Signed-off-by:
Mingtong Bao <baomingtong001@208suo.com> Signed-off-by:
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Lijo Lazar authored
Its value is required for finding the memory id of xcp. Fixes: d26ea1b3 ("drm/amdgpu: Add xcp manager num_xcp_per_mem_partition") Signed-off-by:
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Jiadong Zhu authored
Only low priority rings are using chunks to save the offset. Bypass the mark offset callings from high priority rings. Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Acked-by:
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Wang Ming authored
Identify issues that arise by using the tests/doubletest.cocci semantic patch. Need to remove duplicate expression in if statement. Signed-off-by:
Wang Ming <machel@vivo.com> Reviewed-by:
Ammar Faizi <ammarfaizi2@gnuweeb.org> Signed-off-by:
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- 19 Jun, 2023 4 commits
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
Updates for v6.5.. this includes a backmerg of drm-next tree to be able to use new DRM DSC helpers. Core: + Add Marijn Suijten as drm/msm reviewer + Adreno A660 bindings + SM8350 MDSS bindings fix + Fix adreno_is_a690() warnings + More generic (DRM) and MSM-specific DSC helpers DP: + Removed obsolete USB-PD remains + Documented DP compatible string for sm8550 platform DPU: + Enable missing features (DSPP, DSC, split display) on sc8180x, sc8280xp, sm8450 + Enabled writeback on sc7280 + Implemented tearcheck support to support vsync on SM150 and newer platforms + Native HDMI output support + Dropped unused features: regdma, GC, IGC + Fixed the DSC flush operations + Simplified QoS handling, removing obsolete and unused features and merging SSPP and WB code paths + Reworked dpu_encoder initialisation path + Enabled DSPP support on sdm845 + Disabled color-management if DSPP blocks are not available + Added support for DSC 1.2 blocks found on sm8350 and later + Added .fb_dirty to fix CMD panels DSI: + Drop powerup quirks in favour of using pre_enable_prev_first for downstream bridges + Fixed 14nm DSI PHY programming + Added support for DSI and 28nm DSI PHY on MSM8226 platform + Make use of DRM and MSM DSC helpers MDP5: + Added support for display controller on MSM8226 platform GPU: + A690 support + Don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA on devices with coherent SMMU (like A690) + Move cmdstream dumping out of fence signaling path + Cleanups + Support for a6xx devices without GMU (aka "GMU wrapper" + a610 support + a619_holi support (a619 variant without GMU) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsUB=tRB4nR6ZCJMuLhro5zN3BQWUSywVYbaipqqDZ_cQ@mail.gmail.com
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Dave Airlie authored
Backmerge tag 'v6.4-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next Linux 6.4-rc7 Need this to pull in the msm work. Signed-off-by:
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.5-2023-06-16: amdgpu: - Misc display fixes - W=1 fixes - Improve scheduler naming - DCN 3.1.4 fixes - kdoc fixes - Enable W=1 - VCN 4.0 fix - xgmi fixes - TOPDOWN fix for large BAR systems - eDP fix - PSR fixes - SubVP fixes - Freesync fix - DPIA fix - SMU 13.0.5 fixes - vblflash fix - RAS fixes - SDMA 4 fix - BO locking fix - BO backing store fix - NBIO 7.9 fixes - GC 9.4.3 fixes - GPU reset recovery fixes - HMM fix amdkfd: - Fix NULL check - Trap fixes - Queue count fix - Add event age tracking radeon: - fbdev client fix scheduler: - Avoid an infinite loop UAPI: - Add KFD event age tracking: Proposed ROCT-Thunk-Interface: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/efdbf6cfbc026bd68ac3c35d00dacf84370eb81e https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/1820ae0a2db85b6f584611dc0cde1a00e7c22915 Proposed ROCR-Runtime: https://github.com/RadeonOpenCompute/ROCR-Runtime/compare/master...zhums:ROCR-Runtime:new_event_wait_review https://github.com/RadeonOpenCompute/ROCR-Runtime/commit/e1f5bdb88eb882ac798aeca2c00ea3fbb2dba459 https://github.com/RadeonOpenCompute/ROCR-Runtime/commit/7d26afd14107b5c2a754c1a3f415d89f3aabb503 drm: - DP MST fix Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2023-06-15' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * Fix fbdev initializer macros Signed-off-by:
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- 18 Jun, 2023 10 commits
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Linus Torvalds authored
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Konrad Dybcio authored
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542780/Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by:
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Konrad Dybcio authored
Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by:
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Konrad Dybcio authored
The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by:
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Konrad Dybcio authored
Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c ("drm/msm/adreno: Add A619 support") Reviewed-by:
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Konrad Dybcio authored
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by:
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Konrad Dybcio authored
A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by:
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Konrad Dybcio authored
A610 and A619_holi don't support the feature. Disable it to make the GPU stop crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature it. Reviewed-by:
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Konrad Dybcio authored
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by:
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