- 11 Oct, 2022 13 commits
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Alex Deucher authored
It's MIT. Fixes: b73353f7 ("drm/amd/display: Use the same cursor info across features") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's not used outside of virtual_link_hwss.c. Fixes a -Wmissing-prototypes warning. Reviewed-by:
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Alex Deucher authored
Fixes a warning in dc.c. Reviewed-by:
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Alex Deucher authored
It's not used outside of dcn32_fpu.c. Fixes: 20dad381 ("drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resources") Reviewed-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Yang Yingliang authored
dcn20_build_mapped_resource() and dcn20_acquire_dsc() is not defined, if CONFIG_DRM_AMD_DC_DCN is disabled. Fix the following build error on arm64: ERROR: modpost: "dcn20_build_mapped_resource" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "dcn20_acquire_dsc" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Fixes: 20dad381 ("drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resources") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Signed-off-by:
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Aric Cyr authored
DC version 3.2.207 brings along the following: - PMFW z-state interface update - Cursor update refactor - Fixes to DSC validation, DCFCLK during Freesync, etc. - Code cleanup Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Some unused macros might mislead developers during the debug, which can be removed without any issue. This commit drops some unused references to SE_COMMON_MASK_SH_LIST_DCN32. Tested-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Candice Li authored
Add poison mode query support on umc v8_10_0. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Candice Li authored
Add GeccCtrl offset and mask to umc v8_10_0 headers. Signed-off-by:
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Tao Zhou authored
Fix some issues found by checkpatch script. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
So the code can be simplified. Signed-off-by:
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Tao Zhou authored
Make the code reusable and remove redundant code. Signed-off-by:
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Tao Zhou authored
Only RAS UE error address is queried currently, no need to check CE status. Signed-off-by:
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- 10 Oct, 2022 26 commits
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Guenter Roeck authored
Commit 5d8c3e83 ("drm/amd/display: fix array-bounds error in dc_stream_remove_writeback()") tried to fix an array bounds error seen with gcc 12.0. Unfortunately, that results in another array bounds error, seen with older versions of gcc. Building csky:allmodconfig ... failed -------------- Error log: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function 'dc_stream_remove_writeback': drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:83: error: array subscript 1 is above array bounds of 'struct dc_writeback_info[1]' [-Werror=array-bounds] 527 | stream->writeback_info[j] = stream->writeback_info[i]; | ~~~~~~~~~~~~~~~~~~~~~~^~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc.h:1269, from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:29, from drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.h:29, from drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:27: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_stream.h:241:34: note: while referencing 'writeback_info' 241 | struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; We could check both i and j for overflow to fix the problem. That would, however, be not make much sense since it is known and provable that j <= i. Also, the check introduced with commit 5d8c3e83 does not really add value since it checks if j < MAX_DWB_PIPES. Since it is known that j <= i, it would make more sense to check if i < MAX_DWB_PIPES. Unfortunately, that does not help to solve the problem observed here: gcc still complains. To solve the problem, replace the subsequent check for 'i != j' with 'j < i'. This is identical to the original check since we know that j <= i, and it makes all versions of gcc happy. Drop the check introduced with commit 5d8c3e83 since it is not really useful and does not solve the problem. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Fixes: 5d8c3e83 ("drm/amd/display: fix array-bounds error in dc_stream_remove_writeback()") Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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Alexey Kodanev authored
Since 'hardwareActivityPerformanceLevels' is set to the size of the 'performance_levels' array in smu7_hwmgr_backend_init(), using the '<=' assertion to check for the next index value is incorrect. Replace it with '<'. Detected using the static analysis tool - Svace. Fixes: 599a7e9f ("drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7.") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alexey Kodanev <aleksei.kodanev@bell-sw.com> Signed-off-by:
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Alexey Kodanev authored
Since 'hardwareActivityPerformanceLevels' is set to the size of the 'performance_levels' array in vega10_hwmgr_backend_init(), using the '<=' assertion to check for the next index value is incorrect. Replace it with '<'. Detected using the static analysis tool - Svace. Fixes: f83a9991 ("drm/amd/powerplay: add Vega10 powerplay support (v5)") Reviewed-by:
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Alex Deucher authored
Update all SDMA versions that support SR-IOV to properly tear down the ttm buffer functions on suspend. Tested-by:
Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Switch all of the SDMA implementations to use the helper to tear down the ttm buffer manager. Tested-by:
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Bokun Zhang authored
- Under SRIOV, SDMA engine is shared between VFs. Therefore, we will not stop SDMA during hw_fini. This is not an issue with normal dirver loading and unloading. - However, when we put the SDMA engine to suspend state and resume it, the issue starts to show up. Something could attempt to use that SDMA engine to clear or move memory before the engine is initialized since the DRM entity is still there. - Therefore, we will call sdma_v5_2_enable(false) during hw_fini, and if we are under SRIOV, we will call sdma_v5_2_enable(true) afterwards to allow other VFs to use SDMA. This way, the DRM entity of SDMA engine is emptied and it will follow the flow of resume code path. Tested-by:
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Alvin Lee authored
Watermark calculation was incorrect due to missing brackets. Fixes: 85f4bc0c ("drm/amd/display: Add SubVP required code") Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The OTG_MASTER_UPDATE_LOCK_SEL is used for GSL and OTGs in the same group for selecting the OTG_MASTER_UPDATE_LOCK from the same OTG. At some point, it a check was added to see if OTG is running or not, which is not necessary, and for this reason, this commit dropped that check. Tested-by:
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Rodrigo Siqueira authored
In multiple parts of the DCN code, we write directly to the OTG_V_TOTAL_* registers in some OPTC functions. Let's avoid it by using the set_vtotal_min_max. Tested-by:
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Rodrigo Siqueira authored
The struct timing_generator_funcs provides a hook for setting up the maximum possible vertical dimension of display for OTG, as the panel supports. DCN10 has a standard function named optc1_set_vtotal_min_max which all ASICs can use to set the aforementioned hook. Since we did not set it for DCN20, this commit initializes the set_vtotal_min_max with the DCN10 function. Tested-by:
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Dmytro Laktyushkin authored
Prevents certain configs blocking s0i3 when streams aren't completely removed Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] Dpia hpd interrupt processing is disabled when entering S4/S0i3 and would be reenabled after detection completes during resuming. Because, keeping hpd interrupts enabled during detection leads to multiple detections for the same hpd transition. There is a S4 case where dpia hpd interrupt is missed when driver is in transitioning from hpd interrupt processing disable to enable and the display does not light up. [How] - Added dmub inbox command DMUB_CMD__DPIA_HPD_INT_ENABLE to explicitly control dmub to issue dpia hpd interrupt or not. If dpia hpd interrupt is disabled, dmub will keep the hpd pending and post it once driver reenables dpia hpd interrupt or when querying with DMUB_CMD__QUERY_HPD_STATE. - Added dmub boot option dpia_hpd_int_enable_supported to notify dmub about whether DMUB_CMD__DPIA_HPD_INT_ENABLE command would be used. Tested-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Max Tseng authored
Since different features would need to update cursor registers, However, they would use different approaches. To unify varied methods, this refactor is implemented the same update cursor info method for current varied features. Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Max Tseng <Max.Tseng@amd.com> Signed-off-by:
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Dillon Varone authored
[Why & How] FCLK pstate allow message should not be dependent on local "update_fclk". Tested-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
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Dillon Varone authored
[Why & How] Acquire FCLK DPM levels to properly construct DML clock limits. Further add new logic to keep number of indices for each clock in clk_mgr. Tested-by:
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Fangzhi Zuo authored
Before enabling new crtc, stream_count in dc_state does not sync with that in drm_atomic_state. Validating dsc in such case would leave newly added stream not jointly participating in dsc optimization with existing streams, but simply using default initialized vcpi all the time which gives wrong dsc determination decision. Consider the scenaio where one 4k60 connected to the dock under dp-alt mode. Since dp-alt mode is 2-lane setup, stream 1 consumes 63 slots with dsc needed. Then hook up a second 4k60 to the dock. stream 2 connected with 65 slot initialized by default without dsc. dsc pre validate will not jointly optimize stream 2 with stream 1 before crtc 2 added into the dc_state. That leads to stream 2 not getting dsc optimization, and trigger atomic_check failure all the time, as 65 > 63 limit. After getting all new crtcs added into the state, stream_count in dc_state correctly reflect that in drm_atomic_state which comes up with correct dsc decision. Fixes: 71be4b16 ("drm/amd/display: dsc validate fail not pass to atomic check") Tested-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by:
Mark Broadworth <mark.broadworth@amd.com> Signed-off-by:
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Jun Lei authored
[Why & How] Add a helper to map ODM/MPC/Multi-Plane resources from DC Tested-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
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Vladimir Stempen authored
[Why] Diagnostics reports exceptions generated when timeout waiting for DISPCLK frequency divider change expires when testing ODM4to1. Diagnostics reports exceptions generated when timeout waiting for OTG busy status expires when disabling OTG during ODM4to1 test. [How] Increase HW status waiting time for DISPCLK frequency divider change and OTG busy status when disable OTG. Tested-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Vladimir Stempen <vladimir.stempen@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Doing timing sync seqence for phantom pipes will not go through since they are not fully programmed like normal pipes. Skip the sequence on such pipes Tested-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Dillon Varone authored
[Why?] Currently phy_pix_clk is used to program DTO's which is incorrect. [How?] Use the timing pixel clock to program DTO's correctly. Reviewed-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
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Martin Leung authored
[Why & How] bug was caused when moving variable from stack to heap because it was reusable and garbage was left over, so we need to zero mem Fixes: 7acc487a ("drm/amd/display: reduce stack size in dcn32 dml (v2)") Tested-by:
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Vladimir Stempen authored
[Why] Bandwidth validation is using Freesync parameters from previous Freesync state. Bandwidth validation ignores DCFCLK calculated after Freesync parameters are configured [How] Set Freesync bandwidth parameters to its default state before running bandwidth validation. Take DCFCLK calculated after Freesync bandwidth parameters are assigned and bandwidth is recalculated. Tested-by:
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Dillon Varone authored
This reverts commit e4e481e4. [Why & How] The reverted commit creates memory leak and causes issue upon driver install. Tested-by:
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Nicholas Kazlauskas authored
[Why] Request from PMFW to change the messaging format to specify whether we support z-state via individual bits. [How] Update the args we pass in the support message. Fixes: d5c6909e ("drm/amd/display: Add DCN314 clock manager") Tested-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Shirish S authored
[Why] If psr_feature_enable is set to true by default, it continues to be enabled for non capable links. [How] explicitly disable the feature on links that are not capable of the same. Fixes: 8c322309 ("drm/amd/display: Enable PSR") Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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- 06 Oct, 2022 1 commit
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Hamza Mahfooz authored
This reverts commit 66f99628. Unfortunately, that commit causes performance regressions on non-PSR setups. So, just revert it until FB_DAMAGE_CLIPS support can be added. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2189 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216554 Fixes: 66f99628 ("drm/amdgpu: use dirty framebuffer helper") Fixes: abbc7a3d ("drm/amdgpu: don't register a dirty callback for non-atomic") Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
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