Merge tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

Pull "arm64: tegra: Device tree changes for v4.10-rc1" from Thierry Reding:

This adds initial support for Tegra186, the P3310 processor module as
well as the P2771 development board. Not much is functional, but there
is enough to boot to an initial ramdisk with debug serial output.

* tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add NVIDIA P2771 board support
  arm64: tegra: Enable PSCI on P3310
  arm64: tegra: Add NVIDIA P3310 processor module support
  arm64: tegra: Add GPIO controllers on Tegra186
  arm64: tegra: Add SDHCI controllers on Tegra186
  arm64: tegra: Add I2C controllers on Tegra186
  arm64: tegra: Add serial ports on Tegra186
  arm64: tegra: Add CPU nodes for Tegra186
  arm64: tegra: Add Tegra186 support

Merge tag 'renesas-arm64-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Pull "Second Round of Renesas ARM64 Based SoC DT Updates for v4.10" from Simon Horman:

Enhancements:
* Add device nodes for PRR
* Add m3ulcb board
* Enable I2C on r8a7796/salvator-x board
* Enable SDHI0 on h3ulcb board

* tag 'renesas-arm64-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7796: Add device node for PRR
  arm64: dts: r8a7795: Add device node for PRR
  arm64: dts: h3ulcb: rename SDHI0 pins
  arm64: dts: h3ulcb: enable SDHI2
  arm64: dts: m3ulcb: enable SDHI2
  arm64: dts: m3ulcb: enable SDHI0
  arm64: dts: m3ulcb: enable WDT
  arm64: dts: m3ulcb: enable EXTALR clk
  arm64: dts: m3ulcb: enable GPIO keys
  arm64: dts: m3ulcb: enable GPIO leds
  arm64: dts: m3ulcb: enable SCIF clk and pins
  arm64: dts: m3ulcb: initial device tree
  arm64: dts: m3ulcb: add M3ULCB board DT bindings
  arm64: dts: h3ulcb: update header
  arm64: dts: h3ulcb: update documentation with official board name
  arm64: dts: r8a7796: salvator-x: enable I2C
  arm64: dts: r8a7796: Enable I2C DMA
  arm64: dts: r8a7796: add I2C support

Two branches were incorrectly sent without having the necessary
header file changes. Rather than back those out now, I'm replacing
the symbolic names for the clks and resets with the numeric
values to get 'make allmodconfig dtbs' back to work.

After the header file changes are merged, we can revert this
patch.

Fixes: 6bc37fac ("arm64: dts: add Allwinner A64 SoC .dtsi")
Fixes: 50784e61 ("dts: arm64: db820c: add pmic pins specific dts file")
Acked-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Pull "mvebu dt64 for 4.10 (part 2)" from Gregory CLEMENT:

Fix DTC warning on Armada 37xx and 7K/8K

* tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu:
  ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx
  arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K
  arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx

Add PCIe support to the ARTPEC-6 SoC. This uses the existing
pcie-artpec6 driver.
So, all that is needed is device tree entries in the DTS.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Jesper Nilsson <jespern@axis.com>

The NVIDIA P2771 is composed of a P3310 processor module that connects
to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is
connected via the P2597's display connector and has several connectors
such as HDMI, USB 3.0, PCIe and ethernet.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The P3310 processor module comes ships with a firmware that implements
PSCI 1.0. Enable and use it to bring up all CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The NVIDIA P3310 is a processor module used in several reference designs
that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other
essentials such as ethernet, WiFi and a PMIC. It is typically connected
to an I/O board (such as the P2597) that provides the connecters needed
to hook it up to the outside world.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).
Signed-off-by: Thierry Reding <treding@nvidia.com>

The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>

This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[treding@nvidia.com: remove leading 0 from unit-addresses]
[treding@nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This changes SDHI0 pin names for H3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This supports SDHI2 for H3ULCB onboard eMMC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This supports SDHI2 for M3ULCB onboard eMMC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This supports SDHI0 on M3ULCB board SD card slot
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This supports watchdog timer for M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This enables EXTALR clock that can be used for the watchdog.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This supports GPIO keys on M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This supports GPIO leds on M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add the initial device tree for the R8A7796 SoC based M3ULCB low cost
board (R-Car Starter Kit Pro)

This commit supports the following peripherals:
- SCIF (console)
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add M3ULCB Device tree bindings Documentation, listing it as a supported
board.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This updates H3ULCB device tree header with official board name
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This updates H3ULCB Device tree bindings Documentation with
official board name
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

memory has a reg property so the unit name should contain an address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

config-space has a ranges property so the unit name should contain an
address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

internal-regs has a ranges property so the unit name should contain an
address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Merge tag 'samsung-dt64-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Topic branch with DT arm64 changes for v4.10.

Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC
interrupts.  Although this was working but with error messages like:
        genirq: Setting trigger mode 0 for irq 16 failed

Use level high interrupt instead of type none.  The choice of level high was
rather an arbitrary decision hoping it will work on each platform.  Tests shown
no issues so far.

* tag 'samsung-dt64-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Use human-friendly symbols for interrupt properties in exynos7
  arm64: dts: exynos: Fix invalid GIC interrupt flags in exynos7
Signed-off-by: Olof Johansson <olof@lixom.net>

mvebu dt64 for 4.10 (part 1)

Adding the new "community" board for Armada 3700

* tag 'mvebu-dt64-4.10-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Amlogic DT changes for 64-bit platforms for v4.10

Support for new drivers:
- USB
- i2c
- SPI
- mailbox/MHU
- PWM
- ethernet MAC, PHY
- secure monitor
- IR
- watchdog

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (27 commits)
  ARM64: dts: meson-gxbb-vega-s95: Add SD/SDIO/MMC and PWM nodes
  ARM64: dts: meson-gxl-s905x: Enable internal ethernet PHY
  ARM64: dts: meson-gxl-p23x: Enable ethernet
  ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY
  ARM64: dts: amlogic: Reorder copyrights for meson-gx
  ARM64: dts: meson-gxl-p23x: Enable IR receiver
  ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes
  ARM64: dts: meson-gxl-p23x: Add uart pinctrl
  ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes
  ARM64: dts: meson-gxl: Add i2c nodes
  ARM64: dts: meson-gxl: Add clock nodes
  ARM64: dts: meson-gxl: Add pinctrl nodes
  ARM64: dts: meson-gxbb: Move common nodes to meson-gx
  ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes
  ARM64: dts: meson-gxbb: Add SRAM node
  ARM64: dts: meson-gxbb: Add MMC nodes to Nexbox A95x
  ARM64: dts: meson-gxbb: Add P20x Wifi SDIO support
  ARM64: dts: meson-gxbb: Add Wifi 32K clock for p20x boards
  ARM64: dts: meson-gxbb: add MMC support
  ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'sunxi-dt64-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt64

Allwinner arm64 DT changes for 4.10

Support for the Allwinner A64, their first armv8 SoC.

* tag 'sunxi-dt64-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  arm64: dts: add Pine64 support
  Documentation: devicetree: add vendor prefix for Pine64
  arm64: dts: add Allwinner A64 SoC .dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>

ARM64: DT: Hisilicon SoC DT updates for 4.10

- Correct the hardware pin number of the usb node on the Hip06
- Add the Hisilicon Hip07 D05 board dts binding
- Add the initial dts for the Hip07 D05 board
- Fix the warning for the node without reg propery on the Hip06
- Fix the sas am max transmissions quirk property on the Hip06
- Disable the sas0 and sas2 on D03 board
- Add refclk node for SAS on the Hip06

* tag 'hisi-arm64-dt-4.10' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisi: add refclk node to hip06 dts files for SAS
  arm64: dts: hisi: disable sas0 and sas2 for d03
  arm64: dts: hisi: fix hip06 sas am-max-trans quirk
  arm64: dts: hip06: Fix no reg property warning
  arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
  Documentation: arm64: Add Hisilicon Hip07 D05 dts binding
  arm64: dts: hip06: Correct hardware pin number of usb node
Signed-off-by: Olof Johansson <olof@lixom.net>