1. 01 Sep, 2022 2 commits
    • Like Xu's avatar
      perf/x86/core: Completely disable guest PEBS via guest's global_ctrl · f2aeea57
      Like Xu authored
      When a guest PEBS counter is cross-mapped by a host counter, software
      will remove the corresponding bit in the arr[global_ctrl].guest and
      expect hardware to perform a change of state "from enable to disable"
      via the msr_slot[] switch during the vmx transaction.
      
      The real world is that if user adjust the counter overflow value small
      enough, it still opens a tiny race window for the previously PEBS-enabled
      counter to write cross-mapped PEBS records into the guest's PEBS buffer,
      when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff)
      to switch into the enabled state, while the arr[pebs_enable].guest has not.
      
      Close this window by clearing invalid bits in the arr[global_ctrl].guest.
      
      Fixes: 85425032 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations")
      Signed-off-by: default avatarLike Xu <likexu@tencent.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Link: https://lkml.kernel.org/r/20220831033524.58561-1-likexu@tencent.com
      f2aeea57
    • Kan Liang's avatar
      perf/x86/intel: Fix unchecked MSR access error for Alder Lake N · 24919fde
      Kan Liang authored
      For some Alder Lake N machine, the below unchecked MSR access error may be
      triggered.
      
      [ 0.088017] rcu: Hierarchical SRCU implementation.
      [ 0.088017] unchecked MSR access error: WRMSR to 0x38f (tried to write
      0x0001000f0000003f) at rIP: 0xffffffffb5684de8 (native_write_msr+0x8/0x30)
      [ 0.088017] Call Trace:
      [ 0.088017] <TASK>
      [ 0.088017] __intel_pmu_enable_all.constprop.46+0x4a/0xa0
      
      The Alder Lake N only has e-cores. The X86_FEATURE_HYBRID_CPU flag is
      not set. The perf cannot retrieve the correct CPU type via
      get_this_hybrid_cpu_type(). The model specific get_hybrid_cpu_type() is
      hardcode to p-core. The wrong CPU type is given to the PMU of the
      Alder Lake N.
      
      Since Alder Lake N isn't in fact a hybrid CPU, remove ALDERLAKE_N from
      the rest of {ALDER,RAPTOP}LAKE and create a non-hybrid PMU setup.
      
      The differences between Gracemont and the previous Tremont are,
      - Number of GP counters
      - Load and store latency Events
      - PEBS event_constraints
      - Instruction Latency support
      - Data source encoding
      - Memory access latency encoding
      
      Fixes: c2a960f7 ("perf/x86: Add new Alder Lake and Raptor Lake support")
      Reported-by: default avatarJianfeng Gao <jianfeng.gao@intel.com>
      Suggested-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Link: https://lkml.kernel.org/r/20220831142702.153110-1-kan.liang@linux.intel.com
      24919fde
  2. 28 Aug, 2022 25 commits
  3. 27 Aug, 2022 13 commits