- 05 Jun, 2011 1 commit
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Alex Deucher authored
The PHY was not initialized correctly after ac89af1e since the function bailed early as an encoder was not assigned. The encoder isn't necessary for PHY init so just assign to 0 for init so that the table is executed. Reported-by:
Ari Savolainen <ari.m.savolainen@gmail.com> Tested-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 02 Jun, 2011 8 commits
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Marek Olšák authored
BC6 and BC7 are described in ARB_texture_compression_bptc. No idea what FMT_32_AS_32_32_32_32 is good for. Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
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Alex Deucher authored
Otherwise, no vblank interrupts. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37522Signed-off-by:
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Alex Deucher authored
It got added twice by accident. Signed-off-by:
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Alex Deucher authored
- add gpu init support - add blit support - add ucode loader Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Dave Airlie authored
We need to take a reference to this object, pinning doesn't take a reference so if userspace deletes the object it can disappear even if pinned. v2: fix error paths to unreference properly also. should fix: https://bugzilla.kernel.org/show_bug.cgi?id=32402 and https://bugzilla.redhat.com/show_bug.cgi?id=680651Acked-By:
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- 25 May, 2011 5 commits
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Alex Deucher authored
- no longer in staging - all radeons supported Signed-off-by:
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Alex Deucher authored
Uses a different method than other evergreen asics. Signed-off-by:
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Alex Deucher authored
The rest of the code is already in place. Signed-off-by:
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Alex Deucher authored
Allows us to use the 3D engine for memory management and allows us to use vram beyond the BAR aperture. v2: fix copy paste typo Reported-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
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Alex Deucher authored
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- 23 May, 2011 6 commits
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Andrew Morton authored
udelay() doesn't like 8-bit arguments: drivers/gpu/drm/radeon/atom.c: In function 'atom_op_delay': drivers/gpu/drm/radeon/atom.c:653: warning: comparison is always false due to limited range of data type while we're there, use msleep() rather than open-coding it. Cc: David Airlie <airlied@linux.ie> Reviewed-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Alex Deucher authored
- proper bank size for fusion for 2D tiling. Signed-off-by:
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Alex Deucher authored
Needed by userspace for 2D tiled buffer alignment Signed-off-by:
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Alex Deucher authored
It only needs to be called once at startup, not for every modeset. Signed-off-by:
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Alex Deucher authored
Noticed by Droste on IRC. Signed-off-by:
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Alex Deucher authored
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- 22 May, 2011 8 commits
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Dave Airlie authored
cayman is reporting the wrong tile config value to userspace, this causes piglit mipmap generation tests to fail. Reviewed-by:
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Dave Airlie authored
This was leading to a bogus value being programmed to the backend routing register. Reviewed-by:
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Dave Airlie authored
None of the latest GPUs had this hooked up, this is necessary for correct operation in a lot of cases, however we should test this on a few GPUs in these families as we've had problems in this area before. Reviewed-by:
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Dave Airlie authored
On cayman we need to set the bit to cause HDP flushes to invalidate the HDP cache also. Reviewed-by:
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Alex Deucher authored
This needs to be explicitly set on btc. It's set by default on evergreen/fusion, so it fine to just unconditionally enable it for all chips. Signed-off-by:
Dave Airlie <airlied@gmail.com>
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Michel Dänzer authored
This was based on a description by Ben Herrenschmidt: > I've removed that SBA reset from the normal TLB invalidation path and > left it only once after turning AGP on. About six months ago, he said: > I did it a bit differently, but yeah, you get the idea. I'm doing a > patch series so don't bother pushing things too hard yet. But I haven't seen anything from him about this since then, and people are regularly hitting these lockups, so here we are... Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Alex Deucher authored
For DP/eDP, always use the standard DP SS indices. Signed-off-by:
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Alex Deucher authored
If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by:
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- 20 May, 2011 12 commits
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Alex Deucher authored
It's more like LVDS then DP in some ways. Signed-off-by:
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Alex Deucher authored
Don't try and en/disable the port as it may be a hpd event from powering up/down the panel during a modeset or dpms. Signed-off-by:
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Alex Deucher authored
In the hotplug handler, just use the drm dpms functions. If the monitor is plugged in, turn it on, if it's not, turn it off. This also reduces power usage by turning off the encoder and crtc when the monitor is unplugged. Signed-off-by:
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Alex Deucher authored
- reorganize the functions based on use - clean up function naming - rework link training to better match what we use internally - add initial support for DP 1.2 (no MST yet) Signed-off-by:
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Alex Deucher authored
Required for proper operation with DP bridges. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Fusion hardware often has DP to VGA/LVDS/TMDS bridges to handle non-DP encoders. Internally we treat them mostly like DP. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Used for dp1.2 support and for dp bridges. Signed-off-by:
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Alex Deucher authored
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