- 01 Apr, 2015 40 commits
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Andrew Bresticker authored
If a machine-specific hook is not implemented for restart, poweroff, or halt, fall back to halting secondary CPUs, disabling interrupts, and spinning. In the case of restart, attempt to restart the system via do_kernel_restart() (which will call any registered restart handlers) before halting. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9600/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Andrew Bresticker authored
Since cpu_wait() enables interrupts upon return, CPUs which have entered stop_this_cpu() may still end up handling interrupts. This can lead to the softlockup detector firing on a panic or restart/poweroff/halt. Just disable interrupts and spin to ensure nothing else runs on the CPU once it has entered stop_this_cpu(). Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9601/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Helmut Schaa authored
At least QCA955x can handle up to 256MBytes. Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Cc: linux-mips@linux-mips.org Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Helmut Schaa <helmut.schaa@googlemail.com> Patchwork: https://patchwork.linux-mips.org/patch/8738/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Delay slot emulation in the FPU emulator is the only kernel user of an executable stack, it is also very slow. Add a counter so we can see how many of these emulations are done. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8634/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Joshua Kinard authored
Update arch/mips/include/asm/sgi/sgi.h with some updated information on SGI systems. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8666/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Wolfram Sang authored
This platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: linux-kernel@vger.kernel.org Cc: Wolfram Sang <wsa@the-dreams.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8824/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Wolfram Sang authored
This platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8823/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ganesan Ramalingam authored
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8896/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Subhendu Sekhar Behera authored
The new I2C block in XLP9XX has 4 interrupts, add the mapping for these in nlm_hal.c Signed-off-by: Subhendu Sekhar Behera <sbehera@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8897/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ganesan Ramalingam authored
Add support for third XHCI port in XLPII processors. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8895/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
Enabling the SUE bit for core can can result in rare cache errors which are difficult to track down, so do not enable it. This can cause a minor performance loss in some tests. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8894/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
Core configuration register IFU_BRUB_RESERVE has to be setup to handle a silicon errata which can result in a CPU hang. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8902/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
Change name of xlp_get_dram_map to nlm_get_dram_map to be consistent with the rest of the functions in the file. Pass the the size of the array 'dram_map' to the function, and ensure that it does not write past the end of the array. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8892/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Prem Mallappa authored
Enable CPU_SUPPORTS_HUGEPAGES for XLP processors. Signed-off-by: Prem Mallappa <pmallapp@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8891/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
XLP9XX has 5 bits that specify the core in the EBASE register. XLP5XX case added as well for completeness. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8890/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
Use the current_cpu_data package field to get the node of the current CPU. This allows us to remove xlp_cores_per_node and move nlm_threads_per_node() and nlm_cores_per_node() to netlogic/common.h, which simplifies code. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8889/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
commit bda4584c ("MIPS: Support CPU topology files in sysfs") added topology related macros for all MIPS platforms and commit bbbf6d87 ("MIPS: NL: Fix nlm_xlp_defconfig build error") removed most of the contents from mach-netlogic/topology.h. The netlogic specific topology is not needed anymore, we just need to setup the package field in current_cpu_data. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8888/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
The per-cpu interrupt ACK using EIRR has to be done just once after all the bits in the status register are processed. PIC ack has to be done once in case of MSI, and for every interrupt in case of MSI-X Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8887/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ganesan Ramalingam authored
Change the PIC frequency calculation to use the register that has the current configuration. The existing code used the register that is written to change frequency, which can have an invalid value if the firmware did not set it up correctly. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8885/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C authored
If the device header of a block is not present, return invalid IRT value so that we do not program an incorrect offset. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8882/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ganesan Ramalingam authored
PRID register should be masked with IMP_MASK to get processor ID. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8883/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Qingmin Liu authored
The variable ref_div is initialized to the correct divisor but not used in the frequency calculation. This caused incorrect frequency to be reported when the clock divisor is not 3. Signed-off-by: Qingmin Liu <qingmin@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8884/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Shanghui Liu authored
For core 0, the condition of "cpu == bootcpu" is always true, so it does not wait for other three threads to become ready. Fix this by using correct check. Signed-off-by: Shanghui Liu <shliu@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8881/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Toma Tabacu authored
Remove variable self-assignments. This silences a bunch of -Wself-assign warnings reported by clang. The changed code can be compiled without warnings by both gcc and clang. Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9314/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Daniel Sanders authored
Replace incorrect matching constraint that caused the error with an alternative that still has the required constraints on the inline assembly. This is the error message reported by clang: arch/mips/include/asm/checksum.h:285:27: error: unsupported inline asm: input with type '__be32' (aka 'unsigned int') matching output with type 'unsigned short' "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); ^~~~~~~~~~~~ The changed code can be compiled successfully by both gcc and clang. Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Suggested-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9313/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Toma Tabacu authored
Remove a cast to the 'mips16e_instruction' union inside an if condition and instead do an assignment to a local 'union mips16e_instruction' variable's 'full' member before the if statement and use this variable in the if condition. This is the error message reported by clang: arch/mips/kernel/branch.c:38:8: error: cast to union type from type 'unsigned short' not present in union if (((union mips16e_instruction)inst).ri.opcode ^ ~~~~ The changed code can be compiled successfully by both gcc and clang. Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: David Daney <david.daney@cavium.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9312/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Daniel Sanders authored
Without this, a 'break' instruction is executed very early in the boot and the boot hangs. The problem is that clang doesn't honour named registers on local variables and silently treats them as normal uninitialized variables. However, it does honour them on global variables. Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: David Daney <ddaney.cavm@gmail.com> Acked-by: Behan Webster <behanw@converseincode.com> Patchwork: https://patchwork.linux-mips.org/patch/9311/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Steven J. Hill authored
Add in new config files for enabling a XPA platform. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9354/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Chandrakala Chavva authored
This fixes reboot for Octeon III boards [ralf@linux-mips.org: Dropped segment for function cvmx_reset_octeon() which was removed by the preceeding commit.] Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9464/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
As suggested by David Daney. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Don't assume they are there, the device tree will tell us. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9461/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Without this, we get bus errors. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9460/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Some hardware blocks attached to the OCTEON bootbus run asynchronously to accesses from the CPUs. These include MMC/SD host, CF(when using DMA), and NAND controller. A bus error, or corrupt data may occur if a CPU is trying to access a bootbus connected device at the same time the bus is running asynchronous operations. To work around these problems we add this semaphore that must be acquired before initiating bootbus activity. Subsequent patches will add users for this. Signed-off-by: David Daney <david.daney@cavium.com> [aleksey.makarov@auriga.com: combine the patches] Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9459/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
Most of the supported chips use legacy (non-DT) bootloaders, so they will need to select an appropriate builtin DTB at compile time until the bootloader is updated. Provide suitable DTS files, and a means to compile one of them into the kernel image. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8858/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
Add an entry for each supported Broadcom SoC. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8857/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
The DT bindings for this platform have changed as the bootloader and product requirements evolved. In particular, there are both Linux-on-Zephyr and Linux-on-Viper configurations. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8856/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
Also, add an LE defconfig for set-top box (BCM7xxx). This will allow the BMIPS kernel to run on several non-BCM3384 platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8855/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
This will be required to support BMIPS3300 platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8854/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no longer need this code under arch/mips. [ralf@linux-mips.org: Fix conflicts.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8853/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
A couple of chips require special handling in order to make SMP secondary boot and/or exception vectors work correctly. Take care of these in setup.c. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8852/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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