1. 19 Sep, 2019 3 commits
    • Stephen Boyd's avatar
      Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-meson' into clk-next · f5c7305d
      Stephen Boyd authored
       - Support qcom SM8150 RPMh clks
       - Set floor ops for qcom sd clks
       - Support qcom QCS404 WCSS clks
       - Support for Mediatek MT6779 SoCs
       - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
      
      * clk-qcom:
        clk: qcom: rcg: Return failure for RCG update
        clk: qcom: fix QCS404 TuringCC regmap
        clk: qcom: clk-rpmh: Add support for SM8150
        dt-bindings: clock: Document SM8150 rpmh-clock compatible
        clk: qcom: clk-rpmh: Convert to parent data scheme
        dt-bindings: clock: Document the parent clocks
        clk: qcom: gcc: Use floor ops for SDCC clocks
        clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
        clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
        clk: qcom: define probe by index API as common API
        clk: qcom: Add WCSS gcc clock control for QCS404
        clk: qcom: msm8916: Don't build by default
        clk: qcom: gcc: Add global clock controller driver for SM8150
        dt-bindings: clock: Document gcc bindings for SM8150
        clk: qcom: clk-alpha-pll: Add support for Trion PLLs
        clk: qcom: clk-alpha-pll: Remove post_div_table checks
        clk: qcom: clk-alpha-pll: Remove unnecessary cast
      
      * clk-mtk:
        clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
        clk: mediatek: Register clock gate with device
        clk: mediatek: add pericfg clocks for MT8183
        dt-bindings: clock: mediatek: add pericfg for MT8183
        clk: mediatek: Add MT6779 clock support
        clk: mediatek: Add dt-bindings for MT6779 clocks
        dt-bindings: mediatek: bindings for MT6779 clk
        clk: reset: Modify reset-controller driver
      
      * clk-armada:
        clk: mvebu: ap80x: add AP807 clock support
        clk: mvebu: ap806: Prepare the introduction of AP807 clock support
        clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
        clk: mvebu: ap806: be more explicit on what SaR is
        clk: mvebu: ap80x-cpu: add AP807 CPU clock support
        clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
        dt-bindings: ap806: Document AP807 clock compatible
        dt-bindings: ap80x: Document AP807 CPU clock compatible
        clk: mvebu: ap806: Fix clock name for the cluster
        clk: mvebu: add CPU clock driver for Armada 7K/8K
        clk: mvebu: add helper file for Armada AP and CP clocks
        dt-bindings: ap806: add the cluster clock node in the syscon file
      
      * clk-ingenic:
        clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
        clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
      
      * clk-meson: (23 commits)
        clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
        clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
        clk: meson: g12a: add support for SM1 GP1 PLL
        dt-bindings: clk: meson: add sm1 periph clock controller bindings
        clk: meson: axg-audio: add g12a reset support
        dt-bindings: clock: meson: add resets to the audio clock controller
        clk: meson: g12a: expose CPUB clock ID for G12B
        clk: meson: g12a: add notifiers to handle cpu clock change
        clk: meson: add g12a cpu dynamic divider driver
        clk: core: introduce clk_hw_set_parent()
        clk: meson: remove clk input helper
        clk: meson: remove ee input bypass clocks
        clk: meson: clk-regmap: migrate to new parent description method
        clk: meson: meson8b: migrate to the new parent description method
        clk: meson: axg: migrate to the new parent description method
        clk: meson: gxbb: migrate to the new parent description method
        clk: meson: g12a: migrate to the new parent description method
        clk: meson: remove ao input bypass clocks
        clk: meson: axg-aoclk: migrate to the new parent description method
        clk: meson: gxbb-aoclk: migrate to the new parent description method
        ...
      f5c7305d
    • Stephen Boyd's avatar
      Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put',... · cee99529
      Stephen Boyd authored
      Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk-data' and 'clk-debugfs' into clk-next
      
       - Add SDIO gate to aspeed driver
       - Support aspeed AST2600 SoC
       - Add missing of_node_put() calls in various clk drivers
       - Drop NULL checks in clk debugfs
       - Add min/max rates to clk debugfs
      
      * clk-aspeed:
        clk: Add support for AST2600 SoC
        clk: aspeed: Move structures to header
        clk: aspeed: Add SDIO gate
      
      * clk-unused:
        clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
        clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
        clk: composite: Drop unused clk.h include
        clk: Si5341/Si5340: remove redundant assignment to n_den
        clk: qoriq: Fix -Wunused-const-variable
      
      * clk-of-node-put:
        clk: ti: dm814x: Add of_node_put() to prevent memory leak
        clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()
        clk: davinci: pll: Add of_node_put() in of_davinci_pll_init()
        clk: versatile: Add of_node_put() in cm_osc_setup()
      
      * clk-const-bulk-data:
        clk: Constify struct clk_bulk_data * where possible
      
      * clk-debugfs:
        clk: Drop !clk checks in debugfs dumping
        clk: Use seq_puts() in possible_parent_show()
        clk: Assert prepare_lock in clk_core_get_boundaries
        clk: Add clk_min/max_rate entries in debugfs
      cee99529
    • Stephen Boyd's avatar
      clk: Drop !clk checks in debugfs dumping · 7f480466
      Stephen Boyd authored
      These recursive functions have checks for !clk being passed in, but the
      callers are always looping through lists and therefore the pointers
      can't be NULL. Drop the checks to simplify the code.
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      Link: https://lkml.kernel.org/r/20190826234729.145593-1-sboyd@kernel.org
      7f480466
  2. 18 Sep, 2019 8 commits
  3. 17 Sep, 2019 5 commits
  4. 09 Sep, 2019 11 commits
  5. 06 Sep, 2019 4 commits
  6. 04 Sep, 2019 1 commit
    • Stephen Boyd's avatar
      Merge tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson into clk-meson · 5a85a642
      Stephen Boyd authored
      Pull second set of Amlogic clk driver updates from Jerome Brunet:
      
       - Add g12a reset support to the axg audio clock controller
       - Add sm1 support to the g12a clock controller
      
      * tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson:
        clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
        clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
        clk: meson: g12a: add support for SM1 GP1 PLL
        dt-bindings: clk: meson: add sm1 periph clock controller bindings
        clk: meson: axg-audio: add g12a reset support
        dt-bindings: clock: meson: add resets to the audio clock controller
      5a85a642
  7. 26 Aug, 2019 5 commits
  8. 20 Aug, 2019 3 commits