- 06 Apr, 2022 1 commit
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Xiaoke Wang authored
kzalloc() is a memory allocation function which can return NULL when some internal memory errors happen. So it is better to check it to prevent potential wrong memory access. Signed-off-by:
Xiaoke Wang <xkernel.wang@foxmail.com> Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/tencent_B3E19486FF39415098B572B7397C2936C309@qq.comSigned-off-by:
Rob Clark <robdclark@chromium.org>
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- 24 Mar, 2022 5 commits
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Dmitry Baryshkov authored
Make dpu-qcm2290 example really follow the defined schema: - Drop qcom,mdss compatible. It's only used for MDP5 devices. - Change display controller name to display-controller as specified in the yaml Reported-by:
Rob Herring <robh@kernel.org> Cc: Loic Poulain <loic.poulain@linaro.org> Fixes: 164f69d9 ("dt-bindings: msm: disp: add yaml schemas for QCM2290 DPU bindings") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220324115536.2090818-1-dmitry.baryshkov@linaro.orgSigned-off-by:
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Rob Clark authored
Fixes: 25faf2f2 ("drm/msm: Show process names in gem_describe") Signed-off-by:
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Rob Clark authored
The mutex wasn't really protecting anything before. Before the previous patch we could still be racing with the scheduler's kthread, as that is not necessarily frozen yet. Now that we've parked the sched threads, the only race is with jobs retiring, and that is harmless, ie. Signed-off-by:
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Rob Clark authored
In the system suspend path, we don't want to be racing with the scheduler kthreads pushing additional queued up jobs to the hw queue (ringbuffer). So park them first. While we are at it, move the wait for active jobs to complete into the new system- suspend path. Signed-off-by:
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Rob Clark authored
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- 08 Mar, 2022 2 commits
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Rob Clark authored
Avoid going down devfreq paths on devices where devfreq is not initialized. v2: Change has_devfreq() logic [Dmitry] Reported-by:
Linux Kernel Functional Testing <lkft@linaro.org> Reported-by:
Anders Roxell <anders.roxell@linaro.org> Signed-off-by:
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Dan Carpenter authored
These casts need to happen before the shift. The only time it would matter would be if "rev.core" is >= 128. In that case the sign bit would be extended and we do not want that. Fixes: afab9d91 ("drm/msm/adreno: Expose speedbin to userspace") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Link: https://lore.kernel.org/r/20220307133105.GA17534@kiliSigned-off-by:
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- 07 Mar, 2022 1 commit
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Rob Clark authored
refcount_t complains about 0->1 transitions, which isn't *quite* what we wanted. So use dirtyfb==1 to mean that the fb is not connected to any output that requires dirtyfb flushing, so that we can keep the underflow and overflow checking. Fixes: 9e4dde28 ("drm/msm: Avoid dirtyfb stalls on video mode displays (v2)") Signed-off-by:
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- 05 Mar, 2022 2 commits
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Rob Clark authored
Fixes: f6d62d09 ("drm/msm/a6xx: add support for Adreno 660 GPU") Signed-off-by:
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Rob Clark authored
Add a way for userspace to specify the sequence number fence used to track completion of the submit. As the seqno fence is simply an incrementing counter which is local to the submitqueue, it is easy for userspace to know the next value. This is useful for native userspace drivers in a vm guest, as the guest to host roundtrip can have high latency. Assigning the fence seqno in the guest userspace allows the guest to continue without waiting for response from the host. Signed-off-by:
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- 04 Mar, 2022 4 commits
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Rob Clark authored
Any app controlled perfcntr collection (GL_AMD_performance_monitor, etc) does not require counters to maintain state across context switches. So clear them if systemwide profiling is not active. Signed-off-by:
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Rob Clark authored
Add a SYSPROF param for system profiling tools like Mesa's pps-producer (perfetto) to control behavior related to system-wide performance counter collection. In particular, for profiling, one wants to ensure that GPU context switches do not effect perfcounter state, and might want to suppress suspend (which would cause counters to lose state). v2: Swap the order in msm_file_private_set_sysprof() [sboyd] and initialize the sysprof_active refcount to one (because the under/ overflow checking in refcount_t doesn't expect a 0->1 transition) meaning that values greater than 1 means sysprof is active. Signed-off-by: -
Rob Clark authored
It was always expected to have a use for this some day, so we left a placeholder. Now we do. (And I expect another use in the not too distant future when we start allowing userspace to allocate GPU iova.) Signed-off-by:
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Rob Clark authored
Update headers from mesa commit: commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef Author: Rob Clark <robclark@freedesktop.org> AuthorDate: Wed Mar 2 17:11:10 2022 -0800 freedreno/registers: Add a couple regs we need for kernel Signed-off-by:
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- 03 Mar, 2022 1 commit
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Dmitry Baryshkov authored
Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix indentation for another brace, so it matches the corresponding line. Reported-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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- 02 Mar, 2022 1 commit
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Rob Herring authored
The MDSS interrupt provider is a single cell, so specifying interrupt flags on the consumers is incorrect. Signed-off-by:
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- 25 Feb, 2022 5 commits
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Akhil P Oommen authored
Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace identify the sku. Signed-off-by:
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Akhil P Oommen authored
Add support for 7c3 SKU detection using speedbin fuse. Signed-off-by:
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Akhil P Oommen authored
Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of hardcoding one. This helps to avoid code churn in case of a gpu rename. Signed-off-by:
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Akhil P Oommen authored
Use generic name for resources like irq and kthread instead of hardware specific name to make it easier to grep. Signed-off-by:
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Rob Clark authored
Someone on IRC once asked an innocent enough sounding question: Why with xf86-video-modesetting is es2gears limited at 120fps. So I broke out the perfetto tracing mesa MR and took a look. It turns out the problem was drm_atomic_helper_dirtyfb(), which would end up waiting for vblank.. es2gears would rapidly push two frames to Xorg, which would blit them to screen and in idle hook (I assume) call the DIRTYFB ioctl. Which in turn would do an atomic update to flush the dirty rects, which would stall until the next vblank. And then the whole process would repeat. But this is a bit silly, we only need dirtyfb for command mode DSI panels. So track in plane state whether dirtyfb is required, and track in the fb how many attached planes require dirtyfb so that we can skip it when not required. (Note, mdp4 does not actually have cmd mode support.) Signed-off-by:
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- 23 Feb, 2022 7 commits
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Dmitry Baryshkov authored
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Dmitry Baryshkov authored
The commit adding msm8998 support didn't added msm8998's DSPP blocks configuration, but did not use them in msm8998_cfg_init(). Wire them up to be used for display post processing. Reported-by:
kernel test robot <lkp@intel.com> Fixes: 94391a14 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: Jami Kettunen <jami.kettunen@somainline.org> Signed-off-by:
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Loic Poulain authored
QCM2290 MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Reviewed-by:
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Loic Poulain authored
Add compatibility for QCM2290 display subsystem, including required entries in DPU hw catalog. Signed-off-by:
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Loic Poulain authored
Add DSI block specific qcm2290 compatible string as valid Qualcomm DSI controller. Signed-off-by:
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Loic Poulain authored
QCM2290 MDSS includes a Qualcomm DSI controller v2.4.1. Since this controller version is not SoC specific, and already assigned to sc7180 for auto configuration, we rely on DSI block specific compatible string "qcom,dsi-ctrl-6g-qcm2290", and use the device's data to point to the right dsi config handler. Signed-off-by:
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Loic Poulain authored
Config autodetect based on DSI controller version is quite limited since several qcom SoCs can integrate a DSI controller with the same version, but with different config (io_offset, supplies, etc). This change allows to specify dsi config via device data pointer. config autodetect is still used in case data pointer is NULL. Signed-off-by:
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- 20 Feb, 2022 2 commits
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Rob Clark authored
Other processes don't need to know about faults that they are isolated from by virtue of address space isolation. They are only interested in whether some of their state might have been corrupted. But to be safe, also track unattributed faults. This case should really never happen unless there is a kernel bug (and that would never happen, right?) v2: Instead of adding a new param, just change the behavior of the existing param to match what userspace actually wants [anholt] Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5934Signed-off-by:Emma Anholt <emma@anholt.net> Signed-off-by:
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Rob Clark authored
Prep work for next patch. Signed-off-by:
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- 19 Feb, 2022 4 commits
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Dmitry Baryshkov authored
Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi' and 'msm-next-lumag-mdp5' into msm-next-lumag
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Dmitry Baryshkov authored
It is possible to supply display-connector (bridge) to the DP interface, add support for parsing it too. Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
Currently DP driver will allocate panel bridge for eDP panels. This supports only the following topology: - eDP encoder ⇒ eDP panel (wrapped using panel-bridge) Simplify this code to just check if there is any next bridge in the chain (be it a panel bridge or regular bridge). Rename panel_bridge field to next_bridge accordingly. This allows one to use e.g. one of the following display topologies: - eDP encoder ⇒ ptn3460 ⇒ fixed LVDS panel - eDP encoder ⇒ ptn3460 ⇒ LVDS connector with EDID lines for panel autodetect - eDP encoder ⇒ ptn3460 ⇒ THC63LVD1024 ⇒ DPI panel. - eDP encoder ⇒ LT8912 ⇒ DSI panel Signed-off-by:
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Dmitry Baryshkov authored
In commit 8a3b4c17 ("drm/msm/dp: employ bridge mechanism for display enable and disable") the DP driver received a drm_bridge instance, which is always attached to the encoder as a root bridge. However it conflicts with the panel_bridge support for eDP panels. The panel bridge attaches to the encoder before the "dp" bridge (DP driver's drm_bridge instance created in msm_dp_bridge_init()) has a chance to do so. Change panel bridge attachment to come after the "dp" bridge attachment (and to use it as a previous bridge). Fixes: 8a3b4c17 ("drm/msm/dp: employ bridge mechanism for display enable and disable") Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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- 18 Feb, 2022 5 commits
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AngeloGioacchino Del Regno authored
In function dpu_encoder_phys_cmd_wait_for_commit_done we are always checking if the relative CTL is started by waiting for an interrupt to fire: it is fine to do that, but then sometimes we call this function while the CTL is up and has never been put down, but that interrupt gets raised only when the CTL gets a state change from 0 to 1 (disabled to enabled), so we're going to wait for something that will never happen on its own. Solving this while avoiding to restart the CTL is actually possible and can be done by just checking if it is already up and running when the wait_for_commit_done function is called: in this case, so, if the CTL was already running, we can say that the commit is done if the command transmission is complete (in other terms, if the interface has been flushed). Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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AngeloGioacchino Del Regno authored
Add a function that returns whether the requested CTL is active or not: this will be used in a later commit to fix command mode panel issues. Signed-off-by:
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Dmitry Baryshkov authored
DPU driver contains code to parse clock items from device tree into special data struct and then enable/disable/set rate for the clocks using that data struct. However the DPU driver itself uses only parsing and enabling/disabling part (the rate setting is used by DP driver). Move this implementation to the DP driver (which actually uses rate setting) and replace hand-coded enable/disable/get loops in the DPU with the respective clk_bulk operations. Put operation is removed completely because, it is handled using devres instead. DP implementation is unchanged for now. Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # RB3 (sdm845) and RB5 (qrb5165) Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by:
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Dmitry Baryshkov authored
All physical encoders used by virtual encoder share the same connector, so pull the connector field from dpu_encoder_phys into dpu_encoder_virt structure. Otherwise code suggests that different phys_encs can have different connectors. Reviewed-by:
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Dmitry Baryshkov authored
Make dpu_encoder use atomic_mode_set to receive connector and CRTC states as arguments rather than finding connector and CRTC by manually looping through the respective lists. Reviewed-by:
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