- 11 Aug, 2023 12 commits
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Sricharan Ramabadhran authored
Document the new ipq5018 SOC/board device tree bindings. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-4-git-send-email-quic_srichara@quicinc.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Bjorn Andersson authored
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
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Sricharan Ramabadhran authored
This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
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Bartosz Golaszewski authored
Enable the second MAC on sa8775p-ride. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.plSigned-off-by:
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Bartosz Golaszewski authored
Once we add a second ethernet node, the MDIO bus names will conflict unless we provide aliases. Add one for the existing ethernet node. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by:
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Bartosz Golaszewski authored
For improved readability order the aliases alphabetically for sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index the first one for better readability. Signed-off-by:
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Bartosz Golaszewski authored
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a global reset-gpios property at the MDIO node level which controls all devices on the bus. The latter is most likely a workaround for the chicken-and-egg problem where we cannot read the ID of the PHY before bringing it out of reset but we cannot bring it out of reset until we've read its ID. I have proposed a comprehensive solution for this problem in 2020 but it never got upstream. We do however have workaround in place which allows us to hard-code the PHY id in the compatible property, thus skipping the ID scanning. Let's make the device-tree for sa8775p-ride slightly more correct by moving the reset-gpios property to the PHY node with its ID put into the PHY node's compatible. Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/Signed-off-by:
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Bartosz Golaszewski authored
Enable the second SerDes PHY on sa8775p-ride development board. Signed-off-by:
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Bartosz Golaszewski authored
Add a node for the second MAC on sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add a node for the SerDes PHY used by EMAC1 on sa8775p-ride. Signed-off-by:
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- 10 Aug, 2023 2 commits
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Bryan O'Donoghue authored
Enable CAMSS on the standard RB3 as it is possible to run the test pattern generator (TPG) without any populated ports/endpoints. media-ctl --reset yavta --no-query -w '0x009f0903 9' /dev/v4l-subdev4 yavta --list /dev/v4l-subdev4 media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:SGRBG10_1X10/3280x2464]' media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:SGRBG10_1X10/3280x2464]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' media-ctl -d /dev/media0 -p yavta -B capture-mplane --capture=5 -n 5 -I -f SGRBG10P -s 3280x2464 --file=TPG-SGRBG10-3280x2464-000-#.bin /dev/video2 Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230809203534.1100030-2-bryan.odonoghue@linaro.orgSigned-off-by:
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Eric Chanudet authored
SA8540P-ride is one of the Qualcomm platforms that does not have access to UEFI runtime services and on which the RTC registers are read-only, as described in: https://lore.kernel.org/all/20230202155448.6715-1-johan+linaro@kernel.org/ Reserve four bytes in one of the PMIC registers to hold the RTC offset the same way as it was done for sc8280xp-crd which has similar limitations: commit e67b4558 ("arm64: dts: qcom: sc8280xp-crd: enable rtc") On SA8540P-ride, the register bank SDAM6 of the first PMIC is not writable. Following recommendations provided during the review, use SDAM2 from the second PMIC at offset 0xa0 instead. Reviewed-by:
Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by:
Eric Chanudet <echanude@redhat.com> Link: https://lore.kernel.org/r/20230809203506.1833205-1-echanude@redhat.comSigned-off-by:
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- 04 Aug, 2023 3 commits
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Richard Acayan authored
Add the coefficients for the CPU frequencies to aid in frequency scaling. Profiling setup: - freqbench (https://github.com/kdrag0n/freqbench) - LineageOS kernel, android_kernel_google_msm-4.9 - recommended configuration options by freqbench - disabled options that require clang or 32-bit compilers - mmc governor switched from simple_ondemand to powersave Frequency domains: cpu1 cpu6 Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 Sampling power every 1000 ms Baseline power usage: 445 mW ===== CPU 1 ===== Frequencies: 300 576 748 998 1209 1324 1516 1612 1708 300: 1114 3.7 C/MHz 43 mW 11.6 J 25.8 I/mJ 269.4 s 576: 2138 3.7 C/MHz 51 mW 7.1 J 42.2 I/mJ 140.3 s 748: 2780 3.7 C/MHz 67 mW 7.3 J 41.3 I/mJ 107.9 s 998: 3706 3.7 C/MHz 73 mW 5.9 J 51.1 I/mJ 80.9 s 1209: 4490 3.7 C/MHz 86 mW 5.7 J 52.2 I/mJ 66.8 s 1324: 4918 3.7 C/MHz 90 mW 5.5 J 54.6 I/mJ 61.0 s 1516: 5631 3.7 C/MHz 103 mW 5.5 J 54.9 I/mJ 53.3 s 1612: 5987 3.7 C/MHz 109 mW 5.5 J 55.0 I/mJ 50.1 s 1708: 6344 3.7 C/MHz 126 mW 5.9 J 50.5 I/mJ 47.3 s ===== CPU 6 ===== Frequencies: 300 652 825 979 1132 1363 1536 1747 1843 1996 300: 1868 6.2 C/MHz 53 mW 8.5 J 35.2 I/mJ 160.6 s 652: 4073 6.2 C/MHz 96 mW 7.1 J 42.4 I/mJ 73.7 s 825: 5132 6.2 C/MHz 117 mW 6.9 J 43.7 I/mJ 58.5 s 979: 6099 6.2 C/MHz 151 mW 7.4 J 40.4 I/mJ 49.2 s 1132: 7071 6.2 C/MHz 207 mW 8.8 J 34.1 I/mJ 42.4 s 1363: 8482 6.2 C/MHz 235 mW 8.3 J 36.1 I/mJ 35.4 s 1536: 9578 6.2 C/MHz 287 mW 9.0 J 33.3 I/mJ 31.3 s 1747: 10892 6.2 C/MHz 340 mW 9.4 J 32.0 I/mJ 27.6 s 1843: 11471 6.2 C/MHz 368 mW 9.6 J 31.1 I/mJ 26.2 s 1996: 12425 6.2 C/MHz 438 mW 10.6 J 28.3 I/mJ 24.2 s Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20230802011548.387519-10-mailingradian@gmail.comSigned-off-by:
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Richard Acayan authored
Add CPU frequency scaling, and also add the corresponding memory and cache bandwidths for each frequency. Signed-off-by:
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Richard Acayan authored
Add the interconnect node for L3 cache on SDM670. Signed-off-by:
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- 03 Aug, 2023 6 commits
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Marijn Suijten authored
As discussed in [1] it is more convenient to use a generic `channel` node name for ADC channels while storing a friendly - board-specific instead of PMIC-specific - name in the label, if/when desired to overwrite the channel description already contained (but previously unused) in the driver [2]. Follow up on the dt-bindings' `channel` node name requirement, and instead provide this (sometimes per-board) channel description through a label property. Also remove all the unused label references (not to be confused with label properties) from pm660, pmp8074 and pms405. [1]: https://lore.kernel.org/linux-arm-msm/20221106193018.270106-1-marijn.suijten@somainline.org/T/#u [2]: https://lore.kernel.org/linux-arm-msm/20230116220909.196926-4-marijn.suijten@somainline.org/Acked-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230730-generic-adc-channels-v5-2-e6c69bda8034@somainline.orgSigned-off-by:
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Krzysztof Kozlowski authored
MAX98927 speaker amplifier "interleave_mode" property was never documented. Corrected bindings expect "maxim,interleave-mode" instead, which is already supported by Linux driver. Change is not compatible with older Linux kernels. Signed-off-by:
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Krzysztof Kozlowski authored
MAX98927 speaker amplifier has only one DAI, so DAI cells can be just 0 (as expected by bindings). Signed-off-by:
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Krzysztof Kozlowski authored
MAX98927 speaker amplifier has only one DAI, so DAI cells can be just 0 (as expected by bindings). Signed-off-by:
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Krzysztof Kozlowski authored
Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. Signed-off-by:
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Abel Vesa authored
Even though currently there is no consumer for L1B, add the supply for it anyway. Fixes: 71342fb9 ("arm64: dts: qcom: Add base SM8550 MTP dts") Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230801095246.2884770-1-abel.vesa@linaro.orgSigned-off-by:
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- 31 Jul, 2023 6 commits
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Tengfei Fan authored
Add DTS for Qualcomm QRD platform which uses SM4450 SoC. Reviewed-by:
Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20230731080043.38552-5-quic_tengfan@quicinc.comSigned-off-by:
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Tengfei Fan authored
Add based DTSI for SM4450 SoC and includes base description of CPUs and interrupt-controller which helps to boot to shell with dcc console on boards with this SoC. Reviewed-by:
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Tengfei Fan authored
Document the SM4450 SoC binding and also the boards using it. Reviewed-by:
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Neil Armstrong authored
Add nodes to support Type-C USB/DP functionality. On this platform, a Type-C redriver is added to the SuperSpeed graph. Signed-off-by:
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Neil Armstrong authored
Add nodes to support Type-C USB/DP functionality. Signed-off-by:
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Neil Armstrong authored
Add the USB3+DP Combo QMP PHY port subnodes in the SM8550 SoC DTSI to avoid duplication in the devices DTs. Reviewed-by:
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- 28 Jul, 2023 3 commits
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Zeyan Li authored
I2C6 and I2C7 use the same interrupts, which is incorrect. In the downstream kernel, I2C7 has interrupts of 608 instead of 607. Fixes: 81bee695 ("arm64: dts: qcom: sm8150: add i2c nodes") Signed-off-by:
Zeyan Li <qaz6750@outlook.com> Reviewed-by:
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Stephan Gerhold authored
A7 seems to have external pull-up for the SD card chip detect (like most MSM8916/MSM8939 devices) so drop the internal pull-up. It's not necessary. Tested-by:
"Lin, Meng-Bo" <linmengbo0689@protonmail.com> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20230723-a7sdc2cdnopull-v1-1-699fd730afcb@gerhold.netSigned-off-by:
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Alexander Stein authored
Use id-gpios and vbus-gpios instead. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Acked-by:
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- 22 Jul, 2023 8 commits
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Krzysztof Kozlowski authored
Bindings expect the LPG node name to be "pwm": sc8180x-lenovo-flex-5g.dtb: pmic@5: 'lpg' does not match any of the regexes: Fixes: d3302290 ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
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Krzysztof Kozlowski authored
Bindings expect the Power-on node name to be "pon": sc8180x-lenovo-flex-5g.dtb: pmic@0: 'power-on@800' does not match any of the regexes: Fixes: d3302290 ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by:
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Krzysztof Kozlowski authored
The GPIO children of PMICs should use gpio-ranges: sc8180x-primus.dtb: pmic@0: gpio@c000: 'gpio-ranges' is a required property Fixes: d3302290 ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by:
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Krzysztof Kozlowski authored
The GPIO children of PMICs should use qcom,spmi-gpio fallback: sc8180x-primus.dtb: pmic@0: gpio@c000:compatible: ['qcom,pmc8180-gpio'] is too short Fixes: d3302290 ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by:
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Krzysztof Kozlowski authored
Synaptics RMI4 Touchscreen bindings never defined syna,codes property for function 1a. No usage in Linux drivers. Signed-off-by:
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Krzysztof Kozlowski authored
According to bindings and Linux driver, there is no VDDA but VIO supply. Fixes: 4ac46b36 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5") Signed-off-by:
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Krzysztof Kozlowski authored
Interrupts extended already define a parent interrupt controller: msm8953-xiaomi-vince.dtb: touchscreen@20: Unevaluated properties are not allowed ('interrupts-parent' was unexpected) Fixes: aa17e707 ("arm64: dts: qcom: msm8953: Add device tree for Xiaomi Redmi 5 Plus") Cc: <stable@vger.kernel.org> Signed-off-by: -
Mrinmay Sarkar authored
Enable pcie0, pcie1 nodes and their respective phy's. Signed-off-by:
Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689960276-29266-5-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
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