- 26 Sep, 2022 11 commits
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Dmitry Baryshkov authored
Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-7-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by:
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Dmitry Baryshkov authored
Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by:
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Dmitry Baryshkov authored
To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by:
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Yassine Oudjana authored
Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> [DB: switch to parent_hws for pmux clocks] Signed-off-by:
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Yassine Oudjana authored
The clocks currently listed in clocks and clock-names are the ones supplied by this clock controller, not the ones it consumes. Replace them with the only clock it consumes - the on-board oscillator (XO), and make the properties required. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Yassine Oudjana authored
There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by:
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Yassine Oudjana authored
The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by:
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Yassine Oudjana authored
This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by:
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Yassine Oudjana authored
The parent at this index is the secondary mux, which can connect not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX to better reflect the parent. Signed-off-by:
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- 14 Sep, 2022 19 commits
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Stephan Gerhold authored
MSM8909 has mostly the same as clocks in RPM as MSM8916, but additionally the QPIC clock for the NAND flash controller. Signed-off-by:
Stephan Gerhold <stephan.gerhold@kernkonzept.com> Signed-off-by:
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Stephan Gerhold authored
Document the "qcom,rpmcc-msm8909" compatible for the clocks available via the RPM on the MSM8909 SoC. Signed-off-by:
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Stephan Gerhold authored
The USB PHY on MSM8909 works with the driver used on MSM8916 (phy-qcom-usb-hs.c). When turning the PHY on/off it is first reset using the standard reset controller API. On MSM8916 the reset is provided by the USB driver (ci_hdrc_msm_por_reset() in ci_hdrc_msm.c). While this seems to work on MSM8909 as well, the Qualcomm Linux sources suggest that the PHY should be reset using the GCC_USB2_HS_PHY_ONLY_BCR register instead. In general this is easy to set up in the device tree, thanks to the standard reset controller API. However, to conform to the specifications of the PHY the reset signal should be asserted for at least 10 us. This is handled correctly on MSM8916 in ci_hdrc_msm_por_reset(), but not within the GCC driver. Fix this by making use of the new "udelay" field of qcom_reset_map and set a delay of ~15 us between the assertion/deassertion of the USB PHY reset signal. Signed-off-by:
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Stephan Gerhold authored
The amount of time required between asserting and deasserting the reset signal can vary depending on the involved hardware component. Sometimes 1 us might not be enough and a larger delay is necessary to conform to the specifications. Usually this is worked around in the consuming drivers, by replacing reset_control_reset() with a sequence of reset_control_assert(), waiting for a custom delay, followed by reset_control_deassert(). However, in some cases the driver making use of the reset is generic and can be used with different reset controllers. In this case the reset time requirement is better handled directly by the reset controller driver. Make this possible by adding an "udelay" field to the qcom_reset_map that allows setting a different reset delay (in microseconds). Signed-off-by:
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Stephan Gerhold authored
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a driver for it to make it possible to enable additional functionality for the SoC. Work on this driver was originally started independently by Dominik, I picked it up and added missing clocks/resets, as well as various cleanup to bring it into shape for mainline. Co-developed-by:
Dominik Kobinski <dominikkobinski314@gmail.com> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Stephan Gerhold authored
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a DT schema to describe it, similar to other Qualcomm SoCs. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s clocks. This simplifies the driver and removes extra code duplication. The clock mi2s_div_clk used .enable_reg/.enable_bit, however these fields are not used with by the clk_regmap_div_ops, thus they are silently dropped. Clock enablement is handled in the mi2s_bit_div_clk clock. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Define clock/clock-names properties of the MMCC device node to be used on MSM8960/APQ8064 platform. Signed-off-by:
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Dmitry Baryshkov authored
Define clock/clock-names properties of the GCC device node to be used on MSM8960/APQ8064 platforms. Signed-off-by:
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Li Zhengyu authored
By the clk framework already reference counts prepare/unprepare, this if statement should be never true. Signed-off-by:
Li Zhengyu <lizhengyu3@huawei.com> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220613063327.89320-1-lizhengyu3@huawei.comSigned-off-by:
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Richard Acayan authored
The Snapdragon 670 adds and removes some clocks, adds new frequencies, and adds a new GPLL (Global Phase-Locked Loop) in reference to SDM845, while also removing some GDSCs. Despite these differences, there are many similarities with SDM670. Add data for SDM670 in the driver for SDM845 to reuse the most of the clock data. Advantages and disadvantages of this approach: + maintenance applies to both sdm670 and sdm845 by default + less duplicate code (clocks) means smaller distro/pre-built kernels with all drivers enabled - clocks for both SoC's must be compiled if the user wants clocks for one specific SoC (both or none) - additional testing needed for sdm845 devices Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F10Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
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Richard Acayan authored
This driver will support more than one SoC's set of clocks, and set of GDSCs. This behavior would be unclean with hard-coded static variables. Support it by grabbing clocks, GDSCs, and BCRs in the match data. Signed-off-by:
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Richard Acayan authored
The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most of the new clocks, GDSCs, and resets already have reserved IDs but there are some resources that don't. Add the new clock from Snapdragon 670 and document the differences between the SoC parent clocks. Signed-off-by:
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- 13 Sep, 2022 10 commits
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Dmitry Baryshkov authored
Change a53-pll driver to use clk_parent_data rather than always looking up the xo clock in the system clock list. Note, this change also switches the a53-pll from the global `xo' clock to the `xo_board', the clock that is specified as the `xo' clock in the DT file. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Create a separate DT bindings for Global Clock Controller on MSM8660 platform. Reviewed-by:
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Dang Huynh authored
While working on the Fxtec Pro1X device, this error shows up with my own minimal configuration: gcc-sm6115: probe of 1400000.clock-controller failed with error -38 The clock driver depends on CONFIG_QCOM_GDSC and after enabling that, the driver probes successfully. Signed-off-by:
Dang Huynh <danct12@riseup.net> Fixes: cbe63bfd ("clk: qcom: Add Global Clock controller (GCC) Reviewed-by:
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Taniya Das authored
The clock gating control for TX/RX/WSA core bus clocks would be required to be reset(moved from hardware control) from audio core driver. Thus add the support for the reset clocks. Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after disable as this clock signal is used by hardware to turn ON memories in LPASS. Also add the external mclk to interface external MI2S. Fixes: a9dd2663 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Taniya Das authored
Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode" is enabled in the lpass_aon DT node. Signed-off-by:
Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by:
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Bjorn Andersson authored
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Taniya Das authored
Support external mclk to interface external MI2S clocks for SC7280. Fixes: 4185b27b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280") Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Taniya Das authored
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for SC7280. Update reg property min/max items in YAML schema. Fixes: 4185b27b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280") Acked-by:
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