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- 06 Dec, 2017 1 commit
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Mikita Lipski authored
This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underflow and other potential corruptions. Multi display synchronization is using the same functions as timing_sync in order to minimize redunduncy and decision to disable synchronization is based on trigger parametre set in DM Feature is developed for DCN1 and DCE11 Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 04 Dec, 2017 6 commits
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Tony Cheng authored
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Tony Cheng <tony.cheng@amd.com> Reviewed-by:
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Anthony Koo authored
Need to move HDR Metadata from Surface to Stream since there is only one infoframe possible per stream. Also cleaning up some duplicate definitions. Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
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SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Tony Cheng authored
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Tony Cheng authored
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Anthony Koo authored
Some features should only be enabled on APUs or should not be enabled on APUs. Signed-off-by:
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- 21 Oct, 2017 29 commits
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Tony Cheng authored
- regression fixes in dal 3.1.06 - more linux upstream backport Signed-off-by:
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Tony Cheng authored
Raven bug fixes - RS3 MPO stability improvement - SLS fixes - AM4 fixes DAL 3.1 - merge in upstream patches from DRM maintainer Dave Arilie - hubp, dpp HW objects Signed-off-by:
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Yongqiang Sun authored
Three monitor connected and playing a video will occupy all 4 pipes, if hot plug forth display, commit streams will be failed due to no free pipe can be found. Work around: When forth monitor connected, mark video plane as a fake plane, remove it in dc, keep it in dm and report address to OS, until OS turn off MPO. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
When scaling is enabled, our preference is to scale up to the prefered (native) mode. This means that hardware timings will be the same across a modeset. Therefore, also report mode as changed if source or destination rectangle is different. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
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Tony Cheng authored
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Tony Cheng authored
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Yongqiang Sun authored
Half screen gamma setting and cursor are incorrect when switching mode through win+p due to wrong programming gamma sequence (In case of bottom pipe, gamma and cursor are programmed before front end programmed, pipe is power gated). change: 1. Cache curor attributes to stream 2. Move set gamma and cursor inside front end programming. Signed-off-by:
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Hersen Wu authored
- avoid eDP screen flash 4 times when resume from s3 - improve s3 and boot time Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Charlene Liu authored
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Yongqiang Sun authored
1. Fixed acquire free split pipe bug. 2. Change return value for dc_add_stream_to_ctx from bool to enum. 4. Remove redundant apply_ctx_for_surface calling 5. Unlock pipe after back end programming. Signed-off-by:
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Charlene Liu authored
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Charlene Liu authored
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Shirish S authored
Currently FBC is guarded with ENABLE_FBC macro, which needs to be manually enabled in Makefile. This patch moves it to Kconfig so that there wont be any need to additional patch to be carried for enabling or disabling on every SoC. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Eric Yang authored
For verification of watermark select with SMU team, proper implementation will follow Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Tony Cheng authored
in past program SMU will use all voltage headroom. RV does not if DAL need higher voltage for DCFCLK or DISPCLK, also increase FCLK to improve stutter as voltage is already Signed-off-by:
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Tony Cheng authored
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Tony Cheng authored
experimental change for testing if max line buffer result in better stutter efficiency for 1080p, LB can hold up to 9 line at 10bpcc, potentially add 10 line time of latency hiding. Signed-off-by:
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Tony Cheng authored
1. reverts commit e67f51012740 ("dc: temp disable DCC on high res.") - default still DCC enabled 2. add debug options to decide how DCC is disabled - disable DCC - disable DCC if DCC requires 128b (aka. half) request -- observed compressed data corruption result in screen corruption in full (256b) request while half (128b) would cause DCN to hang, result in DF hang Signed-off-by: -
Tony Cheng authored
also refactor debug option. now pipe_split_policy are dynamic = no hack around dcn_calcs. will split based on HW recommendation avoid = avoid split if we can support the config with higher voltage avoid_multi_display = allow split with single display output. force_single_disp_pipe_split force single display to pipe split to improve stutter efficiency by using DET buffers using 2 HUBP. Signed-off-by:
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Hersen Wu authored
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Tony Cheng authored
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Yongqiang Sun authored
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Charlene Liu authored
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Bhawanpreet Lakha authored
Split update_planes_and_stream_state (split Software and Hardware programming) as the state is already build, so we only need to program the hardware Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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- 06 Oct, 2017 4 commits
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Dave Airlie authored
Refcounts use krefs. Signed-off-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
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Dave Airlie authored
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Dave Airlie authored
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Dave Airlie authored
Rolling your own atomic ref counts is frowned upon. Signed-off-by:
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