1. 09 May, 2014 11 commits
    • Steve Capper's avatar
      arm64: mm: Optimise tlb flush logic where we have >4K granule · fa48e6f7
      Steve Capper authored
      The tlb maintainence functions: __cpu_flush_user_tlb_range and
      __cpu_flush_kern_tlb_range do not take into consideration the page
      granule when looping through the address range, and repeatedly flush
      tlb entries for the same page when operating with 64K pages.
      
      This patch re-works the logic s.t. we instead advance the loop by
       1 << (PAGE_SHIFT - 12), so avoid repeating ourselves.
      
      Also the routines have been converted from assembler to static inline
      functions to aid with legibility and potential compiler optimisations.
      
      The isb() has been removed from flush_tlb_kernel_range(.) as it is
      only needed when changing the execute permission of a mapping. If one
      needs to set an area of the kernel as execute/non-execute an isb()
      must be inserted after the call to flush_tlb_kernel_range.
      
      Cc: Laura Abbott <lauraa@codeaurora.org>
      Signed-off-by: default avatarSteve Capper <steve.capper@linaro.org>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      fa48e6f7
    • Will Deacon's avatar
      arm64: xchg: prevent warning if return value is unused · e1dfda9c
      Will Deacon authored
      Some users of xchg() don't bother using the return value, which results
      in a compiler warning like the following (from kgdb):
      
      In file included from linux/arch/arm64/include/asm/atomic.h:27:0,
                       from include/linux/atomic.h:4,
                       from include/linux/spinlock.h:402,
                       from include/linux/seqlock.h:35,
                       from include/linux/time.h:5,
                       from include/uapi/linux/timex.h:56,
                       from include/linux/timex.h:56,
                       from include/linux/sched.h:19,
                       from include/linux/pid_namespace.h:4,
                       from kernel/debug/debug_core.c:30:
      kernel/debug/debug_core.c: In function ‘kgdb_cpu_enter’:
      linux/arch/arm64/include/asm/cmpxchg.h:75:3: warning: value computed is not used [-Wunused-value]
        ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
         ^
      linux/arch/arm64/include/asm/atomic.h:132:30: note: in expansion of macro ‘xchg’
       #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
      
      kernel/debug/debug_core.c:504:4: note: in expansion of macro ‘atomic_xchg’
          atomic_xchg(&kgdb_active, cpu);
          ^
      
      This patch makes use of the same trick as we do for cmpxchg, by assigning
      the return value to a dummy variable in the xchg() macro itself.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      e1dfda9c
    • Steve Capper's avatar
      arm64: mm: Create gigabyte kernel logical mappings where possible · 206a2a73
      Steve Capper authored
      We have the capability to map 1GB level 1 blocks when using a 4K
      granule.
      
      This patch adjusts the create_mapping logic s.t. when mapping physical
      memory on boot, we attempt to use a 1GB block if both the VA and PA
      start and end are 1GB aligned. This both reduces the levels of lookup
      required to resolve a kernel logical address, as well as reduces TLB
      pressure on cores that support 1GB TLB entries.
      Signed-off-by: default avatarSteve Capper <steve.capper@linaro.org>
      Tested-by: default avatarJungseok Lee <jays.lee@samsung.com>
      [catalin.marinas@arm.com: s/prot_sect_kernel/PROT_SECT_NORMAL_EXEC/]
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      206a2a73
    • Bjorn Helgaas's avatar
      arm64: Make atomic64_t() return "long", not "long long" · ba6bf8c8
      Bjorn Helgaas authored
      arm64 sets CONFIG_64BIT=y and hence uses the "long counter" atomic64_t
      definition from include/linux/types.h.  Make atomic64_read() return "long",
      not "long long".
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      ba6bf8c8
    • Catalin Marinas's avatar
      arm64: Clean up the default pgprot setting · a501e324
      Catalin Marinas authored
      The primary aim of this patchset is to remove the pgprot_default and
      prot_sect_default global variables and rely strictly on predefined
      values. The original goal was to be able to run SMP kernels on UP
      hardware by not setting the Shareability bit. However, it is unlikely to
      see UP ARMv8 hardware and even if we do, the Shareability bit is no
      longer assumed to disable cacheable accesses.
      
      A side effect is that the device mappings now have the Shareability
      attribute set. The hardware, however, should ignore it since Device
      accesses are always Outer Shareable.
      
      Following the removal of the two global variables, there is some PROT_*
      macro reshuffling and cleanup, including the __PAGE_* macros (replaced
      by PAGE_*).
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      a501e324
    • Catalin Marinas's avatar
      arm64: Introduce execute-only page access permissions · bc07c2c6
      Catalin Marinas authored
      The ARMv8 architecture allows execute-only user permissions by clearing
      the PTE_UXN and PTE_USER bits. The kernel, however, can still access
      such page, so execute-only page permission does not protect against
      read(2)/write(2) etc. accesses. Systems requiring such protection must
      implement/enable features like SECCOMP.
      
      This patch changes the arm64 __P100 and __S100 protection_map[] macros
      to the new __PAGE_EXECONLY attributes. A side effect is that
      pte_valid_user() no longer triggers for __PAGE_EXECONLY since PTE_USER
      isn't set. To work around this, the check is done on the PTE_NG bit via
      the pte_valid_ng() macro. VM_READ is also checked now for page faults.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      bc07c2c6
    • Catalin Marinas's avatar
      arm64: Expose ESR_EL1 information to user when SIGSEGV/SIGBUS · 15af1942
      Catalin Marinas authored
      This information is useful for instruction emulators to detect
      read/write and access size without having to decode the faulting
      instruction. The current patch exports it via sigcontext (struct
      esr_context) and is only valid for SIGSEGV and SIGBUS.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      15af1942
    • Catalin Marinas's avatar
      arm64: Remove the aux_context structure · 0e0276d1
      Catalin Marinas authored
      This patch removes the aux_context structure (and the containing file)
      to allow the placement of the _aarch64_ctx end magic based on the
      context stored on the signal stack.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      0e0276d1
    • Catalin Marinas's avatar
      arm64: Provide read/write fault information in compat signal handlers · 9141300a
      Catalin Marinas authored
      For AArch32, bit 11 (WnR) of the FSR/ESR register is set when the fault
      was caused by a write access and applications like Qemu rely on such
      information being provided in sigcontext. This patch introduces the
      ESR_EL1 tracking for the arm64 kernel faults and sets bit 11 accordingly
      in compat sigcontext.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      9141300a
    • Catalin Marinas's avatar
      arm64: Remove boot thread synchronisation for spin-table release method · 64001113
      Catalin Marinas authored
      The synchronisation with the boot thread already happens in __cpu_up()
      via wait_for_completion_timeout(). In addition, __cpu_up() calls are
      protected by the cpu_add_remove_lock mutex and already serialised.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      64001113
    • Catalin Marinas's avatar
      arm64: Implement cache_line_size() based on CTR_EL0.CWG · a41dc0e8
      Catalin Marinas authored
      The hardware provides the maximum cache line size in the system via the
      CTR_EL0.CWG bits. This patch implements the cache_line_size() function
      to read such information, together with a sanity check if the statically
      defined L1_CACHE_BYTES is smaller than the hardware value.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      a41dc0e8
  2. 05 May, 2014 1 commit
  3. 04 May, 2014 4 commits
  4. 03 May, 2014 11 commits
    • Catalin Marinas's avatar
      arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent · 7a8d1ec1
      Catalin Marinas authored
      Since the default DMA ops for arm64 are non-coherent, mark the X-Gene
      controller explicitly as dma-coherent to avoid additional cache
      maintenance.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Cc: Loc Ho <lho@apm.com>
      7a8d1ec1
    • Catalin Marinas's avatar
      arm64: Use bus notifiers to set per-device coherent DMA ops · 6ecba8eb
      Catalin Marinas authored
      Recently, the default DMA ops have been changed to non-coherent for
      alignment with 32-bit ARM platforms (and DT files). This patch adds bus
      notifiers to be able to set the coherent DMA ops (with no cache
      maintenance) for devices explicitly marked as coherent via the
      "dma-coherent" DT property.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      6ecba8eb
    • Ritesh Harjani's avatar
      arm64: Make default dma_ops to be noncoherent · c7a4a765
      Ritesh Harjani authored
      Currently arm64 dma_ops is by default made coherent which makes it
      opposite in default policy from arm.
      
      Make default dma_ops to be noncoherent (same as arm), as currently there
      aren't any dma-capable drivers which assumes coherent ops
      Signed-off-by: default avatarRitesh Harjani <ritesh.harjani@gmail.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      c7a4a765
    • Marc Zyngier's avatar
      arm64: fixmap: fix missing sub-page offset for earlyprintk · f774b7d1
      Marc Zyngier authored
      Commit d57c33c5 (add generic fixmap.h) added (among other
      similar things) set_fixmap_io to deal with early ioremap of devices.
      
      More recently, commit bf4b558e (arm64: add early_ioremap support)
      converted the arm64 earlyprintk to use set_fixmap_io. A side effect of
      this conversion is that my virtual machines have stopped booting when
      I pass "earlyprintk=uart8250-8bit,0x3f8" to the guest kernel.
      
      Turns out that the new earlyprintk code doesn't care at all about
      sub-page offsets, and just assumes that the earlyprintk device will
      be page-aligned. Obviously, that doesn't play well with the above example.
      
      Further investigation shows that set_fixmap_io uses __set_fixmap instead
      of __set_fixmap_offset. A fix is to introduce a set_fixmap_offset_io that
      uses the latter, and to remove the superflous call to fix_to_virt
      (which only returns the value that set_fixmap_io has already given us).
      
      With this applied, my VMs are back in business. Tested on a Cortex-A57
      platform with kvmtool as platform emulation.
      
      Cc: Will Deacon <will.deacon@arm.com>
      Acked-by: default avatarMark Salter <msalter@redhat.com>
      Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      f774b7d1
    • Dave Anderson's avatar
      arm64: Fix for the arm64 kern_addr_valid() function · da6e4cb6
      Dave Anderson authored
      Fix for the arm64 kern_addr_valid() function to recognize
      virtual addresses in the kernel logical memory map.  The
      function fails as written because it does not check whether
      the addresses in that region are mapped at the pmd level to
      2MB or 512MB pages, continues the page table walk to the
      pte level, and issues a garbage value to pfn_valid().
      
      Tested on 4K-page and 64K-page kernels.
      Signed-off-by: default avatarDave Anderson <anderson@redhat.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      da6e4cb6
    • Linus Torvalds's avatar
      Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 0384dcae
      Linus Torvalds authored
      Pull irq fixes from Thomas Gleixner:
       "This udpate delivers:
      
         - A fix for dynamic interrupt allocation on x86 which is required to
           exclude the GSI interrupts from the dynamic allocatable range.
      
           This was detected with the newfangled tablet SoCs which have GPIOs
           and therefor allocate a range of interrupts.  The MSI allocations
           already excluded the GSI range, so we never noticed before.
      
         - The last missing set_irq_affinity() repair, which was delayed due
           to testing issues
      
         - A few bug fixes for the armada SoC interrupt controller
      
         - A memory allocation fix for the TI crossbar interrupt controller
      
         - A trivial kernel-doc warning fix"
      
      * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        irqchip: irq-crossbar: Not allocating enough memory
        irqchip: armanda: Sanitize set_irq_affinity()
        genirq: x86: Ensure that dynamic irq allocation does not conflict
        linux/interrupt.h: fix new kernel-doc warnings
        irqchip: armada-370-xp: Fix releasing of MSIs
        irqchip: armada-370-xp: implement the ->check_device() msi_chip operation
        irqchip: armada-370-xp: fix invalid cast of signed value into unsigned variable
      0384dcae
    • Linus Torvalds's avatar
      Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 98facf0e
      Linus Torvalds authored
      Pull timer fixes from Thomas Gleixner:
       "This update brings along:
      
         - Two fixes for long standing bugs in the hrtimer code, one which
           prevents remote enqueuing and the other preventing arbitrary delays
           after a interrupt hang was detected
      
         - A fix in the timer wheel which prevents math overflow
      
         - A fix for a long standing issue with the architected ARM timer
           related to the C3STOP mechanism.
      
         - A trivial compile fix for nspire SoC clocksource"
      
      * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        timer: Prevent overflow in apply_slack
        hrtimer: Prevent remote enqueue of leftmost timers
        hrtimer: Prevent all reprogramming if hang detected
        clocksource: nspire: Fix compiler warning
        clocksource: arch_arm_timer: Fix age-old arch timer C3STOP detection issue
      98facf0e
    • Linus Torvalds's avatar
      Merge tag 'trace-fixes-v3.15-rc3' of... · 00622e61
      Linus Torvalds authored
      Merge tag 'trace-fixes-v3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace
      
      Pull tracing fix from Steven Rostedt:
       "This is a small fix where the trigger code used the wrong
        rcu_dereference().  It required rcu_dereference_sched() instead of the
        normal rcu_dereference().  It produces a nasty RCU lockdep splat due
        to the incorrect rcu notation"
      Acked-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
      
      * tag 'trace-fixes-v3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
        tracing: Use rcu_dereference_sched() for trace event triggers
      00622e61
    • Steven Rostedt (Red Hat)'s avatar
      tracing: Use rcu_dereference_sched() for trace event triggers · 561a4fe8
      Steven Rostedt (Red Hat) authored
      As trace event triggers are now part of the mainline kernel, I added
      my trace event trigger tests to my test suite I run on all my kernels.
      Now these tests get run under different config options, and one of
      those options is CONFIG_PROVE_RCU, which checks under lockdep that
      the rcu locking primitives are being used correctly. This triggered
      the following splat:
      
      ===============================
      [ INFO: suspicious RCU usage. ]
      3.15.0-rc2-test+ #11 Not tainted
      -------------------------------
      kernel/trace/trace_events_trigger.c:80 suspicious rcu_dereference_check() usage!
      
      other info that might help us debug this:
      
      rcu_scheduler_active = 1, debug_locks = 0
      4 locks held by swapper/1/0:
       #0:  ((&(&j_cdbs->work)->timer)){..-...}, at: [<ffffffff8104d2cc>] call_timer_fn+0x5/0x1be
       #1:  (&(&pool->lock)->rlock){-.-...}, at: [<ffffffff81059856>] __queue_work+0x140/0x283
       #2:  (&p->pi_lock){-.-.-.}, at: [<ffffffff8106e961>] try_to_wake_up+0x2e/0x1e8
       #3:  (&rq->lock){-.-.-.}, at: [<ffffffff8106ead3>] try_to_wake_up+0x1a0/0x1e8
      
      stack backtrace:
      CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.15.0-rc2-test+ #11
      Hardware name:                  /DG965MQ, BIOS MQ96510J.86A.0372.2006.0605.1717 06/05/2006
       0000000000000001 ffff88007e083b98 ffffffff819f53a5 0000000000000006
       ffff88007b0942c0 ffff88007e083bc8 ffffffff81081307 ffff88007ad96d20
       0000000000000000 ffff88007af2d840 ffff88007b2e701c ffff88007e083c18
      Call Trace:
       <IRQ>  [<ffffffff819f53a5>] dump_stack+0x4f/0x7c
       [<ffffffff81081307>] lockdep_rcu_suspicious+0x107/0x110
       [<ffffffff810ee51c>] event_triggers_call+0x99/0x108
       [<ffffffff810e8174>] ftrace_event_buffer_commit+0x42/0xa4
       [<ffffffff8106aadc>] ftrace_raw_event_sched_wakeup_template+0x71/0x7c
       [<ffffffff8106bcbf>] ttwu_do_wakeup+0x7f/0xff
       [<ffffffff8106bd9b>] ttwu_do_activate.constprop.126+0x5c/0x61
       [<ffffffff8106eadf>] try_to_wake_up+0x1ac/0x1e8
       [<ffffffff8106eb77>] wake_up_process+0x36/0x3b
       [<ffffffff810575cc>] wake_up_worker+0x24/0x26
       [<ffffffff810578bc>] insert_work+0x5c/0x65
       [<ffffffff81059982>] __queue_work+0x26c/0x283
       [<ffffffff81059999>] ? __queue_work+0x283/0x283
       [<ffffffff810599b7>] delayed_work_timer_fn+0x1e/0x20
       [<ffffffff8104d3a6>] call_timer_fn+0xdf/0x1be^M
       [<ffffffff8104d2cc>] ? call_timer_fn+0x5/0x1be
       [<ffffffff81059999>] ? __queue_work+0x283/0x283
       [<ffffffff8104d823>] run_timer_softirq+0x1a4/0x22f^M
       [<ffffffff8104696d>] __do_softirq+0x17b/0x31b^M
       [<ffffffff81046d03>] irq_exit+0x42/0x97
       [<ffffffff81a08db6>] smp_apic_timer_interrupt+0x37/0x44
       [<ffffffff81a07a2f>] apic_timer_interrupt+0x6f/0x80
       <EOI>  [<ffffffff8100a5d8>] ? default_idle+0x21/0x32
       [<ffffffff8100a5d6>] ? default_idle+0x1f/0x32
       [<ffffffff8100ac10>] arch_cpu_idle+0xf/0x11
       [<ffffffff8107b3a4>] cpu_startup_entry+0x1a3/0x213
       [<ffffffff8102a23c>] start_secondary+0x212/0x219
      
      The cause is that the triggers are protected by rcu_read_lock_sched() but
      the data is dereferenced with rcu_dereference() which expects it to
      be protected with rcu_read_lock(). The proper reference should be
      rcu_dereference_sched().
      
      Cc: Tom Zanussi <tom.zanussi@linux.intel.com>
      Cc: stable@vger.kernel.org # 3.14+
      Signed-off-by: default avatarSteven Rostedt <rostedt@goodmis.org>
      561a4fe8
    • Linus Torvalds's avatar
      Merge tag 'pm+acpi-3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm · 6c6ca9c2
      Linus Torvalds authored
      Pull ACPI and power management fixes from Rafael Wysocki:
       "A bunch of regression fixes this time.  They fix two regressions in
        the PNP subsystem, one in the ACPI processor driver and one in the
        ACPI EC driver, four cpufreq driver regressions and an unrelated bug
        in one of the drivers.  The regressions are recent or introduced in
        3.14.
      
        Specifics:
      
         - There are two bugs in the ACPI PNP core that cause errors to be
           returned if optional ACPI methods are not present.  After an ACPI
           core change made in 3.14 one of those errors leads to serial port
           suspend failures on some systems.  Fix from Rafael J Wysocki.
      
         - A recently added PNP quirk related to Intel chipsets intorduced a
           build error in unusual configurations (PNP without PCI).  Fix from
           Bjorn Helgaas.
      
         - An ACPI EC workaround related to system suspend on Samsung machines
           added in 3.14 introduced a race causing some valid EC events to be
           discarded.  Fix from Kieran Clancy.
      
         - The acpi-cpufreq driver fails to load on some systems after a 3.14
           commit related to APIC ID parsing that overlooked one corner case.
           Fix from Lan Tianyu.
      
         - Fix for a recently introduced build problem in the ppc-corenet
           cpufreq driver from Tim Gardner.
      
         - A recent cpufreq core change to ensure serialization of frequency
           transitions for drivers with a ->target_index() callback overlooked
           the fact that some of those drivers had been doing operations
           introduced by it into the core already by themselves.  That
           resulted in a mess in which the core and the drivers try to do the
           same thing and block each other which leads to deadlocks.  Fixes
           for the powernow-k7, powernow-k6, and longhaul cpufreq drivers from
           Srivatsa S Bhat.
      
         - Fix for a computational error in the powernow-k6 cpufreq driver
           from Srivatsa S Bhat"
      
      * tag 'pm+acpi-3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
        ACPI / processor: Fix failure of loading acpi-cpufreq driver
        PNP / ACPI: Do not return errors if _DIS or _SRS are not present
        PNP: Fix compile error in quirks.c
        ACPI / EC: Process rather than discard events in acpi_ec_clear
        cpufreq: ppc-corenet-cpufreq: Fix __udivdi3 modpost error
        cpufreq: powernow-k7: Fix double invocation of cpufreq_freq_transition_begin/end
        cpufreq: powernow-k6: Fix double invocation of cpufreq_freq_transition_begin/end
        cpufreq: powernow-k6: Fix incorrect comparison with max_multipler
        cpufreq: longhaul: Fix double invocation of cpufreq_freq_transition_begin/end
      6c6ca9c2
    • Linus Torvalds's avatar
      Merge tag 'dt-for-linus' of git://git.secretlab.ca/git/linux · e981e795
      Linus Torvalds authored
      Pull driver core deferred probe fix from Grant Likely:
       "Drivercore race condition fix (exposed by devicetree)
      
        This branch fixes a bug where a device can get stuck in the deferred
        list even though all its dependencies are met.  The bug has existed
        for a long time, but new platform conversions to device tree have
        exposed it.  This patch is needed to get those platforms working.
      
        This was the pending bug fix I mentioned in my previous pull request.
        Normally this would go through Greg's tree seeing that it is a
        drivercore change, but devicetree exposes the problem.  I've discussed
        with Greg and he okayed me asking you to pull directly"
      
      * tag 'dt-for-linus' of git://git.secretlab.ca/git/linux:
        drivercore: deferral race condition fix
      e981e795
  5. 02 May, 2014 8 commits
  6. 01 May, 2014 5 commits