- 24 Jun, 2024 5 commits
-
-
Bjorn Andersson authored
Merge the in-kernel protection-domain mapper implementation through a feature branch, to allow sharing with the remoteproc tree.
-
Dmitry Baryshkov authored
Existing userspace protection domain mapper implementation has several issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't reread JSON files if firmware location is changed (or if firmware was not available at the time pd-mapper was started but the corresponding directory is mounted later), etc. Provide in-kernel service implementing protection domain mapping required to work with several services, which are provided by the DSP firmware. This module is loaded automatically by the remoteproc drivers when necessary via the symbol dependency. It uses a root node to match a protection domains map for a particular board. It is not possible to implement it as a 'driver' as there is no corresponding device. Tested-by:
Steev Klimaszewski <steev@kali.org> Tested-by:
Alexey Minnekhanov <alexeymin@postmarketos.org> Reviewed-by:
Chris Lew <quic_clew@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240622-qcom-pd-mapper-v9-4-a84ee3591c8e@linaro.org [bjorn: include linux/slab.h] Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
-
Dmitry Baryshkov authored
The in-kernel PD mapper is going to use same message structures as the QCOM_PDR_HELPERS module. Extract message marshalling data to separate module that can be used by both PDR helpers and by PD mapper. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by:
-
Dmitry Baryshkov authored
While parsing the domains list, start offsets from 0 rather than from domains_read. The domains_read is equal to the total count of the domains we have seen, while the domains list in the message starts from offset 0. Fixes: fbe639b4 ("soc: qcom: Introduce Protection Domain Restart helpers") Tested-by:
-
Dmitry Baryshkov authored
If the service locator server is restarted fast enough, the PDR can rewrite locator_addr fields concurrently. Protect them by placing modification of those fields under the main pdr->lock. Fixes: fbe639b4 ("soc: qcom: Introduce Protection Domain Restart helpers") Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by:
-
- 23 Jun, 2024 13 commits
-
-
Bartosz Golaszewski authored
The "memory protection" mechanism mentioned in the comment is the SHM Bridge. This is also the reason why we do not convert this call to using the TZ memory allocator. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Tested-by: Deepti Jaggi <quic_djaggi@quicinc.com> #sa8775p-ride Reviewed-by:
Elliot Berman <quic_eberman@quicinc.com> Link: https://lore.kernel.org/r/20240527-shm-bridge-v10-13-ce7afaa58d3a@linaro.orgSigned-off-by:
-
Bartosz Golaszewski authored
Parse the "memory-region" property and - if present - use it to assign the dedicated reserved memory to the underlying DMA callbacks which will then allocate memory for the SCM calls from it. Signed-off-by:
-
Bartosz Golaszewski authored
SHM Bridge is a safety mechanism allowing to limit the amount of memory shared between the kernel and the TrustZone to regions explicitly marked as such. Add a variant of the tzmem allocator that configures the memory pools as SHM bridges. It also enables the SHM bridge globally so non-SHM bridge memory will no longer work with SCM calls. If enabled at build-time, it will still be checked for availability at run-time. If the architecture doesn't support SHM Bridge, the allocator will fall back to the generic mode. Signed-off-by:
-
Bartosz Golaszewski authored
SHM Bridge is a safety mechanism allowing to limit the amount of memory shared between the kernel and the TrustZone to regions explicitly marked as such. Add low-level primitives for enabling SHM bridge support as well as creating and destroying SHM bridges to qcom-scm. Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Tested-by: Deepti Jaggi <quic_djaggi@quicinc.com> #sa8775p-ride Reviewed-by:
-
Bartosz Golaszewski authored
Drop the DMA mapping operations from qcom_scm_qseecom_app_send() and convert all users of it in the qseecom module to using the TZ allocator for creating SCM call buffers. As this is largely a module separate from the SCM driver, let's use a separate memory pool. Set the initial size to 4K and - if we run out - add twice the current amount to the pool. Signed-off-by:
Amirreza Zarrabi <quic_azarrabi@quicinc.com> Link: https://lore.kernel.org/r/20240527-shm-bridge-v10-9-ce7afaa58d3a@linaro.orgSigned-off-by:
-
Bartosz Golaszewski authored
Let's use the new TZ memory allocator to obtain a buffer for this call instead of manually kmalloc()ing it and then mapping to physical space. Signed-off-by:
Maximilian Luz <luzmaximilian@gmail.com> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Tested-by: Deepti Jaggi <quic_djaggi@quicinc.com> #sa8775p-ride Reviewed-by:
-
Bartosz Golaszewski authored
Let's use the new TZ memory allocator to obtain a buffer for this call instead of using dma_alloc_coherent(). Signed-off-by:
-
Bartosz Golaszewski authored
Let's use the new TZ memory allocator to obtain a buffer for this call instead of using dma_alloc_coherent(). Signed-off-by:
-
Bartosz Golaszewski authored
Let's use the new TZ memory allocator to obtain a buffer for this call instead of using dma_alloc_coherent(). Signed-off-by:
-
Bartosz Golaszewski authored
We need to allocate, map and pass a buffer to the trustzone if we have more than 4 arguments for a given SCM call. Let's use the new TrustZone allocator for that memory and shrink the code in process. As this code lives in a different compilation unit than the rest of the SCM code, we need to provide a helper in the form of qcom_scm_get_tzmem_pool() that allows the SMC low-level routines to access the SCM memory pool. Signed-off-by:
-
Bartosz Golaszewski authored
Select the TrustZone memory allocator in Kconfig and create a pool of memory shareable with the TrustZone when probing the SCM driver. This will allow a gradual conversion of all relevant SCM calls to using the dedicated allocator. The policy used for the pool is "on-demand" and the initial size is 0 as - depending on the config - it's possible that no SCM calls needing to allocate memory will be called. The sizes of possible allocations also vary substiantially further warranting the "on-demand" approach. Signed-off-by:
-
Bartosz Golaszewski authored
We have several SCM calls that require passing buffers to the TrustZone on top of the SMC core which allocates memory for calls that require more than 4 arguments. Currently every user does their own thing which leads to code duplication. Many users call dma_alloc_coherent() for every call which is terribly unperformant (speed- and size-wise). Provide a set of library functions for creating and managing pools of memory which is suitable for sharing with the TrustZone, that is: page-aligned, contiguous and non-cachable as well as provides a way of mapping of kernel virtual addresses to physical space. Make the allocator ready for extending with additional modes of operation which will allow us to support the SHM bridge safety mechanism once all users convert. Signed-off-by:
-
Bartosz Golaszewski authored
Document a new property (currently only for sa8775p) that describes the memory region reserved for communicating with the TrustZone. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240527-shm-bridge-v10-1-ce7afaa58d3a@linaro.orgSigned-off-by:
-
- 21 Jun, 2024 5 commits
-
-
Sibi Sankar authored
The following warning is seen during bwmon_remove due to refcount imbalance, fix this by releasing the OPPs after use. Logs: WARNING: at drivers/opp/core.c:1640 _opp_table_kref_release+0x150/0x158 Hardware name: Qualcomm Technologies, Inc. X1E80100 CRD (DT) ... Call trace: _opp_table_kref_release+0x150/0x158 dev_pm_opp_remove_table+0x100/0x1b4 devm_pm_opp_of_table_release+0x10/0x1c devm_action_release+0x14/0x20 devres_release_all+0xa4/0x104 device_unbind_cleanup+0x18/0x60 device_release_driver_internal+0x1ec/0x228 driver_detach+0x50/0x98 bus_remove_driver+0x6c/0xbc driver_unregister+0x30/0x60 platform_driver_unregister+0x14/0x20 bwmon_driver_exit+0x18/0x524 [icc_bwmon] __arm64_sys_delete_module+0x184/0x264 invoke_syscall+0x48/0x118 el0_svc_common.constprop.0+0xc8/0xe8 do_el0_svc+0x20/0x2c el0_svc+0x34/0xdc el0t_64_sync_handler+0x13c/0x158 el0t_64_sync+0x190/0x194 --[ end trace 0000000000000000 ]--- Fixes: 0276f69f ("soc: qcom: icc-bwmon: Set default thresholds dynamically") Fixes: b9c2ae6c ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver") Signed-off-by:
Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240613164506.982068-1-quic_sibis@quicinc.comSigned-off-by:
-
Bjorn Andersson authored
Merge SMEM and SCM patches related to GPU features through a topic branch to make it possible to share these with the msm-next DRM tree.
-
Konrad Dybcio authored
Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely identifying the specific SKU and the precise speed bin (in the general meaning of this word, anyway): a pair of values called Product Code and Feature Code. Based on this information, we can deduce the available frequencies for things such as Adreno. In the case of Adreno specifically, Pcode is useless for non-prototype SoCs. Introduce a getter for the feature code and export it. Reviewed-by:
-
Konrad Dybcio authored
In preparation for parsing the chip "feature code" (FC) and "product code" (PC) (essentially the parameters that let us conclusively characterize the sillicon we're running on, including various speed bins), move the socinfo version defines to the public header. Signed-off-by:
-
Connor Abbott authored
This will used by drm/msm to initialize GPU registers that Qualcomm's firmware doesn't make writeable to the kernel. Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Reviewed-by:
-
- 13 Jun, 2024 2 commits
-
-
Luca Weiss authored
Add support for using the mbox interface instead of manually writing to the syscon. With this change the driver will attempt to get the mailbox first, and if that fails it will fall back to the existing way of using qcom,ipc-* properties and converting to syscon. Reviewed-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20240606-smsm-mbox-v2-2-8abe6b5f01da@z3ntu.xyzSigned-off-by:
-
Luca Weiss authored
The qcom,ipc-N properties are essentially providing a reference to a mailbox, so allow using the mboxes property to do the same in a more structured way. Since multiple SMSM hosts are supported, we need to be able to provide the correct mailbox for each host. The old qcom,ipc-N properties map to the mboxes property by index, starting at 0 since that's a valid SMSM host also. Mark the older qcom,ipc-N as deprecated and update the example with mboxes. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240606-smsm-mbox-v2-1-8abe6b5f01da@z3ntu.xyzSigned-off-by:
-
- 06 Jun, 2024 1 commit
-
-
Jeff Johnson authored
make allmodconfig && make W=1 C=1 warns: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/soc/qcom/spm.o Add the missing MODULE_DESCRIPTION(), using the same description as the underlying QCOM_SPM Kconfig item. Signed-off-by:
Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by:
-
- 31 May, 2024 2 commits
-
-
Unnathi Chalicheemala authored
Until SM8450, there was only one broadcast region (Broadcast_OR) used to broadcast write and check for status bit 0. >From SM8450 onwards another broadcast region (Broadcast_AND) has been added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence define new regmap structure for Broadcast_AND region and initialize this regmap when HW block version is greater than 4.1, otherwise initialize as a NULL pointer for backwards compatibility. Switch from broadcast_OR to broadcast_AND region (when defined in DT) for checking status bit 1 as Broadcast_OR region checks only for bit 0. Signed-off-by:
Unnathi Chalicheemala <quic_uchalich@quicinc.com> Reviewed-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/9cf19928a67eaa577ae0f02de5bf86276be34ea2.1717014052.git.quic_uchalich@quicinc.comSigned-off-by:
-
Unnathi Chalicheemala authored
The LLCC block in SM8450, SM8550 and SM8650 have a new register space for Broadcast_AND region. This is used to check that all channels have bit set to "1", mainly in SCID activation/deactivation. Previously we were mapping only the Broadcast_OR region assuming there was only one broadcast register region. Now we also map Broadcast_AND region. Signed-off-by:
-
- 30 May, 2024 2 commits
-
-
Tengfei Fan authored
Add llcc configuration support for the SA8775p platform. Signed-off-by:
Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20240529101534.3166507-3-quic_tengfan@quicinc.comSigned-off-by:
-
Tengfei Fan authored
Add the cache controller compatible and register region descriptions for SA8775p platform. Signed-off-by:
-
- 28 May, 2024 3 commits
-
-
Luca Weiss authored
Deprecate the qcom,ipc way of accessing the mailbox in favor of the 'mboxes' property. Update the example to use mboxes. Signed-off-by:
"Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20240425-qcom-ipc-deprecate-v1-2-a8d8034253ea@z3ntu.xyzSigned-off-by:
-
Richard Acayan authored
There is support for SDM670 already, but not recognized by the socinfo driver. Add the table entry so SDM670 can be found in sysfs. Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
-
Richard Acayan authored
The socinfo driver uses SoC IDs from the device tree bindings. Add the SoC ID for SDM670. Signed-off-by:
-
- 27 May, 2024 7 commits
-
-
Kathiravan Thirumoorthy authored
Like all other SoCs in IPQ5332 family, cpufreq for IPQ5321 is also determined by the eFuse, with the maximum limit of 1.1GHz. Add support for the same. Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by:
Mukesh Ojha <quic_mojha@quicinc.com> Signed-off-by:
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20240325-ipq5321-sku-support-v2-3-f30ce244732f@quicinc.comSigned-off-by:
-
Kathiravan Thirumoorthy authored
Add the SoC ID for IPQ5321, which belong to the family of IPQ5332 SoC. Reviewed-by:
-
Kathiravan Thirumoorthy authored
Add the ID for the Qualcomm IPQ5321 SoC. Acked-by:
-
Stephen Boyd authored
Dan pointed out that Smatch is concerned about this code because it uses spin_lock_irqsave() and then calls wait_event_lock_irq() which enables irqs before going to sleep. The comment above the function says it should be called with interrupts enabled, but we simply hope that's true without really confirming that. Let's add a might_sleep() here to confirm that interrupts and preemption aren't disabled. Once we do that, we can change the lock to be non-saving, spin_lock_irq(), to clarify that we don't expect irqs to be disabled. If irqs are disabled by callers they're going to be enabled anyway in the wait_event_lock_irq() call which would be bad. This should make Smatch happier and find bad callers faster with the might_sleep(). We can drop the WARN_ON() in the caller because we have the might_sleep() now, simplifying the code. Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/911181ed-c430-4592-ad26-4dc948834e08@moroto.mountain Fixes: 2bc20f3c ("soc: qcom: rpmh-rsc: Sleep waiting for tcs slots to be free") Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240509184129.3924422-1-swboyd@chromium.orgSigned-off-by:
-
Chen Ni authored
As platform_driver_register() and register_rpmsg_driver() can return error numbers, it should be better to check the return value and deal with the exception. Signed-off-by:
Chen Ni <nichen@iscas.ac.cn> Fixes: 58ef4ece ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Reviewed-by:
-
Unnathi Chalicheemala authored
This flag was never supported by firmware, so remove it. Signed-off-by:
-
Abel Vesa authored
Up until now, all Qualcomm platforms only had maximum 2 ports. The X Elite (x1e80100) adds a third one. Increase the maximum allowed to 3. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
-
