- 01 Apr, 2017 4 commits
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Aneesh Kumar K.V authored
Signed-off-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Aneesh Kumar K.V authored
Now that we use all the available virtual address range, we need to make sure we don't generate VSID such that it overlaps with the reserved vsid range. Reserved vsid range include the virtual address range used by the adjunct partition and also the VRMA virtual segment. We find the context value that can result in generating such a VSID and reserve it early in boot. We don't look at the adjunct range, because for now we disable the adjunct usage in a Linux LPAR via CAS interface. Signed-off-by:
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Aneesh Kumar K.V authored
We optmize the slice page size array copy to paca by copying only the range based on addr_limit. This will require us to not look at page size array beyond addr_limit in PACA on slb fault. To enable that copy task size to paca which will be used during slb fault. Signed-off-by:
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Aneesh Kumar K.V authored
In the followup patch, we will increase the slice array size to handle 512TB range, but will limit the max addr to 128TB. Avoid doing unnecessary computation and avoid doing slice mask related operation above address limit. Signed-off-by:
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- 31 Mar, 2017 28 commits
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Aneesh Kumar K.V authored
We update the hash linux page table layout such that we can support 512TB. But we limit the TASK_SIZE to 128TB. We can switch to 128TB by default without conditional because that is the max virtual address supported by other architectures. We will later add a mechanism to on-demand increase the application's effective address range to 512TB. Having the page table layout changed to accommodate 512TB makes testing large memory configuration easier with less code changes to kernel Signed-off-by:
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Aneesh Kumar K.V authored
This doesn't have any functional change. But helps in avoiding mistakes in case the shift bit changes Signed-off-by:
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Aneesh Kumar K.V authored
Inorder to support large effective address range (512TB), we want to increase the virtual address bits to 68. But we do have platforms like p4 and p5 that can only do 65 bit VA. We support those platforms by limiting context bits on them to 16. The protovsid -> vsid conversion is verified to work with both 65 and 68 bit va values. I also documented the restrictions in a table format as part of code comments. Signed-off-by:
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Michael Ellerman authored
get_kernel_vsid() has a very stern comment saying that it's only valid for kernel addresses, but there's nothing in the code to enforce that. Rather than hoping our callers are well behaved, add a check and return a VSID of 0 (invalid). Signed-off-by: -
Aneesh Kumar K.V authored
Currently we use the top 4 context ids (0x7fffc-0x7ffff) for the kernel. Kernel VSIDs are built using these top context values and effective the segement ID. In subsequent patches we want to increase the max effective address to 512TB. We will achieve that by increasing the effective segment IDs there by increasing virtual address range. We will be switching to a 68bit virtual address in the following patch. But platforms like Power4 and Power5 only support a 65 bit virtual address. We will handle that by limiting the context bits to 16 instead of 19 on those platforms. That means the max context id will have a different value on different platforms. So that we don't have to deal with the kernel context ids changing between different platforms, move the kernel context ids down to use context ids 1-4. We can't use segment 0 of context-id 0, because that maps to VSID 0, which we want to keep as invalid, so we avoid context-id 0 entirely. Similarly we can't use the last segment of the maximum context, so we avoid it too. Signed-off-by:
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Michael Ellerman authored
Complete the split of the radix vs hash mm context initialisation. This is mostly code movement, with the exception that we now limit the context allocation to PRTB_ENTRIES - 1 on radix. Signed-off-by: -
Michael Ellerman authored
The min and max context id values used in alloc_context_id() are currently the right values for use on hash, and happen to also be safe for use on radix. But we need to change that in a subsequent patch, so make the min/max ids parameters and pull the hash values into hsah__alloc_context_id(). Signed-off-by: -
Michael Ellerman authored
KVM wants to be able to allocate an MMU context id, which it does currently by calling __init_new_context(). We're about to rework that code, so provide a wrapper for KVM so it can not worry about the details. Signed-off-by: -
Aneesh Kumar K.V authored
We now get output like below which is much better. [ 0.935306] good_mask low_slice: 0-15 [ 0.935360] good_mask high_slice: 0-511 Compared to [ 0.953414] good_mask:1111111111111111 - 1111111111111......... I also fixed an error with slice_dbg printing. Signed-off-by:
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Aneesh Kumar K.V authored
This structure definition need not be in a header since this is used only by slice.c file. So move it to slice.c. This also allow us to use SLICE_NUM_HIGH instead of 64. I also switch the low_slices type to u64 from u16. This doesn't have an impact on size of struct due to padding added with u16 type. This helps in using bitmap printing function for printing slice mask. Signed-off-by:
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Aneesh Kumar K.V authored
Remove the checks that TASK_SIZE_USER64 is smaller than H_PGTABLE_RANGE and USER_VSID_RANGE. In a following patch we will deliberately add support for a TASK_SIZE smaller than both ranges, so this will no longer be an error condition. Signed-off-by:
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Aneesh Kumar K.V authored
We also update the function arg to struct mm_struct. Move this so that function finds the definition of struct mm_struct. No functional change in this patch. Signed-off-by:
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Aneesh Kumar K.V authored
This avoid copying the slice_mask struct as function return value Signed-off-by:
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Aneesh Kumar K.V authored
In followup patch we want to increase the va range which will result in us requiring high_slices to have more than 64 bits. To enable this convert high_slices to bitmap. We keep the number bits same in this patch and later change that to higher value Signed-off-by:
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Aneesh Kumar K.V authored
We don't support the full 57 bits of physical address and hence can overload the top bits of RPN as hash specific pte bits. Add a BUILD_BUG_ON() to enforce the relationship between H_PAGE_F_SECOND and H_PAGE_F_GIX. Signed-off-by:
Paul Mackerras <paulus@ozlabs.org> [mpe: Move the BUILD_BUG_ON() into hash_utils_64.c and comment it] Signed-off-by:
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Aneesh Kumar K.V authored
Max value supported by hardware is 51 bits address. Radix page table define a slot of 57 bits for future expansion. We restrict the value supported in linux kernel 53 bits, so that we can use the bits between 57-53 for storing hash linux page table bits. This is done in the next patch. This will free up the software page table bits to be used for features that are needed for both hash and radix. The current hash linux page table format doesn't have any free software bits. Moving hash linux page table specific bits to top of RPN field free up the software bits for other purpose. Signed-off-by:
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Aneesh Kumar K.V authored
Reviewed-by:
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Aneesh Kumar K.V authored
Conditional PTE bit definition is confusing and results in coding error. Reviewed-by:
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Aneesh Kumar K.V authored
Without this if firmware reports 1MB page size support we will crash trying to use 1MB as hugetlb page size. echo 300 > /sys/kernel/mm/hugepages/hugepages-1024kB/nr_hugepages kernel BUG at ./arch/powerpc/include/asm/hugetlb.h:19! ..... .... [c0000000e2c27b30] c00000000029dae8 .hugetlb_fault+0x638/0xda0 [c0000000e2c27c30] c00000000026fb64 .handle_mm_fault+0x844/0x1d70 [c0000000e2c27d70] c00000000004805c .do_page_fault+0x3dc/0x7c0 [c0000000e2c27e30] c00000000000ac98 handle_page_fault+0x10/0x30 With fix, we don't enable 1MB as hugepage size. bash-4.2# cd /sys/kernel/mm/hugepages/ bash-4.2# ls hugepages-16384kB hugepages-16777216kB Signed-off-by:
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Aneesh Kumar K.V authored
With this we have on powernv and pseries /proc/cpuinfo reporting timebase : 512000000 platform : PowerNV model : 8247-22L machine : PowerNV 8247-22L firmware : OPAL MMU : Hash Reviewed-by:
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Aneesh Kumar K.V authored
This bit is only used by radix and it is nice to follow the naming style of having bit name start with H_/R_ depending on which translation mode they are used. No functional change in this patch. Reviewed-by:
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Aneesh Kumar K.V authored
Define everything based on bits present in pgtable.h. This will help in easily identifying overlapping bits between hash/radix. No functional change with this patch. Reviewed-by:
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Aneesh Kumar K.V authored
For low slice, max addr should be less than 4G. Without limiting this correctly we will end up with a low slice mask which has 17th bit set. This is not a problem with the current code because our low slice mask is of type u16. But in later patch I am switching low slice mask to u64 type and having the 17bit set result in wrong slice mask which in turn results in mmap failures. Reviewed-by:
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Aneesh Kumar K.V authored
BOOKE code is dead code as per the Kconfig details. So make it simpler by enabling MM_SLICE only for book3s_64. The changes w.r.t nohash is just removing deadcode. W.r.t ppc64, 4k without hugetlb will now enable MM_SLICE. But that is good, because we reduce one extra variant which probably is not getting tested much. Reviewed-by:
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Yang Shi authored
sam440ep_setup_rtc() is just called by machine_device_initcall() so make it __init. Signed-off-by:
Yang Shi <yang.shi@windriver.com> Signed-off-by:
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Hari Bathini authored
With the unnecessary restriction to reserve memory for fadump at the top of RAM forgone, update the documentation accordingly. Signed-off-by:
Hari Bathini <hbathini@linux.vnet.ibm.com> Signed-off-by:
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Hari Bathini authored
Currently, the area to preserve boot memory is reserved at the top of RAM. This leaves fadump vulnerable to memory hot-remove operations. As memory for fadump has to be reserved early in the boot process, fadump can't be registered after a memory hot-remove operation. Though this problem can't be eleminated completely, the impact can be minimized by reserving memory at an offset closer to bottom of the RAM. The offset for fadump memory reservation can be any value greater than fadump boot memory size. Signed-off-by:
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Vipin K Parashar authored
OPAL returns OPAL_WRONG_STATE upon failing to provide sensor data due to core sleeping/offline. Add a check in opal_get_sensor_data() for sensor read failure with OPAL_WRONG_STATE return code and return -EIO. Signed-off-by:
Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by:
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- 28 Mar, 2017 1 commit
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Thadeu Lima de Souza Cascardo authored
For the current task, the kernel stack would only tell the last time the process was rescheduled, if ever. Use the current stack pointer for the current task. Otherwise, every once in a while, the stacktrace printed when reading /proc/self/stack would look like the process is running in userspace, while it's not, which some may consider as a bug. This is also consistent with some other architectures, like x86 and arm, at least. Signed-off-by:
Thadeu Lima de Souza Cascardo <cascardo@canonical.com> Signed-off-by:
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- 27 Mar, 2017 7 commits
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Michael Ellerman authored
cpu_ready_for_interrupts() is called after feature patching, so there's no need to use early_cpu_has_feature(). Signed-off-by: -
Anton Blanchard authored
The config option for the POWER8 crc32c recently changed from CONFIG_CRYPT_CRC32C_VPMSUM to CONFIG_CRYPTO_CRC32C_VPMSUM. Update the configs. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Anton Blanchard authored
Most people use perf these days, so save about 31kB by making oprofile a module. Signed-off-by:
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Anton Blanchard authored
It turns out cloud-config uses ISO9660 filesystems to inject configuration data into cloud images. The cloud-config failures when ISO9660_FS is not enabled are cryptic, and building it in makes mainline testing easier, so re-enable it. Signed-off-by:
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Michael Neuling authored
POWER9 adds form 1 scoms. The form of the indirection is specified in the top nibble of the scom address. Currently we do some (ugly) bit mangling so that we can fit a 64 bit scom address into the debugfs interface. The current code only shifts the top bit (indirect bit). This patch changes it to shift the whole top nibble so that the form of the indirection is also shifted. This patch is backwards compatible with older scoms. (This change isn't required in the arch/powerpc/platforms/powernv/opal-prd.c scom interface as it passes the whole 64bit scom address without any bit mangling) Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Oliver O'Halloran authored
Currently the code to perform an OPAL call is duplicated between the normal path and path taken when tracepoints are enabled. There's no real need for this and combining them makes opal_tracepoint_entry considerably easier to understand. Signed-off-by:
Oliver O'Halloran <oohall@gmail.com> Signed-off-by:
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Guilherme G. Piccoli authored
Currently the xmon debugger is set only via kernel boot command-line. It's disabled by default, and can be enabled with "xmon=on" on the command-line. Also, xmon may be accessed via sysrq mechanism. But we cannot enable/disable xmon in runtime, it needs kernel reload. This patch introduces a debugfs entry for xmon, allowing user to query its current state and change it if desired. Basically, the "xmon" file to read from/write to is under the debugfs mount point, on powerpc directory. It's a simple attribute, value 0 meaning xmon is disabled and value 1 the opposite. Writing these states to the file will take immediate effect in the debugger. Signed-off-by:
Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com> Signed-off-by:
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