- 24 May, 2017 40 commits
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Rex Zhu authored
Bug: SWDEV-117987: Always on CU mask broken for gfx7+ Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Rex Zhu authored
Signed-off-by:
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Xiangliang Yu authored
Change place of virt_init_setting function so that can cover the cg and pg flags configuration. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
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Xiangliang Yu authored
GPU hypervisor cover all settings of CG and PG, so guest doesn't need to do anything. Bypass it. Signed-off-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
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Christian König authored
Only per family registers are still used. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Christian König authored
I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by:
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Rex Zhu authored
Signed-off-by:
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Rex Zhu authored
Signed-off-by:
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Xiaojie Yuan authored
Signed-off-by:
Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
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Xiaojie Yuan authored
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names v3: fix num_pins for tahiti, pitcairn, verde and oland Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Acked-by:
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Alex Deucher authored
I'm not sure if the order matters, but it seems like it makes more sense to set this after the range is programmed. v2: rebase (Alex) Signed-off-by: -
Rex Zhu authored
add set_doorbell functions for mec and cpg. Signed-off-by:
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Alex Deucher authored
This could be used in Andres' priority scheduling patch as well. Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Alex Deucher authored
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by:
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Alex Deucher authored
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by:
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Alex Deucher authored
It's global, not queue specific, so move it out of the kiq register init function. Tested-and-Reviewed-by:
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Alex Deucher authored
No need to reset the wptr and clear the rings. The UNMAP_QUEUES packet writes the current MQD state back the MQD on suspend, so there is no need to reset it as well. Signed-off-by: -
Alex Deucher authored
Use the UNMAP_QUEUES packet to have the KIQ properly disable them. Reviewed-by:
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Alex Deucher authored
Rather than open coding them. Reviewed-by:
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Alex Deucher authored
As the KCQ setup. This way we only have to wait once for the entire MEC. Reviewed-by:
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Alex Deucher authored
Rather than waiting for each queue. Reviewed-by:
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Alex Deucher authored
One for KIQ and one for the KCQ. This simplifies the logic and allows for future optimizations. Reviewed-by:
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Alex Deucher authored
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by:
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Alex Deucher authored
Re-enable GFX PG. It's working properly with MEC now that KIQ is enabled. Reviewed-by:Samuel Li <samuel.li@amd.com> This reverts commit e9ef19aa1bdeac380662a112f1d03a7c3477527f.
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David Panariti authored
KIQ is the Kernel Interface Queue for managing the MEC. Rather than setting up rings via direct MMIO of ring registers, the rings are configured via special packets sent to the KIQ. The allows the MEC to better manage shared resources and certain power events. v2: squash in s3/s4 fix from Rex v3: further fixes from Rex Signed-off-by:
David Panariti <David.Panariti@amd.com> Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Alex Deucher authored
Add missing chips to the doorbell range setup. These were missed in the KIQ code. Fixes power and performance regressions with KIQ. Spotted by Rex. Tested-and-Reviewed-by:
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Alex Deucher authored
Need to properly set the MTYPE and ROQ space setting. This should fix performance regressions with KIQ enabled. Reviewed-by:
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Eric Huang authored
This resolves pcie low speed problem. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Rex Zhu authored
need update smu firmware to version 0x1c20. Signed-off-by:
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Rex Zhu authored
Signed-off-by:
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Rex Zhu authored
Handle the latest powerplay table format; includes Boost State support. Signed-off-by:
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Rex Zhu authored
We need a mask. Signed-off-by:
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Rex Zhu authored
Typo in the mask. Signed-off-by:
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Rex Zhu authored
Add a function to look up the AVFS fuse values for vega10 These are used to populate the avfs fuse table in the smu. Signed-off-by:
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Eric Huang authored
This implements the workload specific interface of optimized compute power profile for Vega10. v2: squash in fix (Tom) Signed-off-by:
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Alex Deucher authored
Taken care of by gpu info firmware now. v2: rebase v3: rework based on latest firmware Reviewed-by:
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Alex Deucher authored
And populate the gfx structures from it. v2: update the structures updated by the table v3: rework based on new table structure v4: simplify things Reviewed-by:
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Alex Deucher authored
Add a new gpu info firmware to store gpu specific configuration data. This allows us to store hw constants in a unified place. v2: adjust structure and elements v3: further restructure Reviewed-by:
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Dan Carpenter authored
Smatch complains about a signedness bug here: vega10_hwmgr.c:4202 vega10_force_clock_level() warn: always true condition '(i >= 0) => (0-u32max >= 0)' Fixes: 7b52db39 ("drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.") Signed-off-by:Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Chunming Zhou authored
[ 338.384770] BUG: unable to handle kernel NULL pointer dereference at (null) [ 338.384817] IP: [< (null)>] (null) [ 338.385505] RIP: 0010:[<0000000000000000>] [< (null)>] (null) [ 338.385950] Call Trace: [ 338.385993] [<ffffffffa05d2313>] ? amdgpu_vm_flush+0x283/0x400 [amdgpu] [ 338.386025] [<ffffffff811818d3>] ? printk+0x4d/0x4f [ 338.386074] [<ffffffffa05d4906>] amdgpu_ib_schedule+0x4a6/0x4d0 [amdgpu] [ 338.386140] [<ffffffffa0673e54>] amdgpu_job_run+0x64/0x180 [amdgpu] [ 338.386203] [<ffffffffa0672e09>] amd_sched_main+0x2e9/0x4a0 [amdgpu] [ 338.386232] [<ffffffff810bfce0>] ? prepare_to_wait_event+0x110/0x110 [ 338.386295] [<ffffffffa0672b20>] ? amd_sched_select_entity+0xe0/0xe0 [amdgpu] [ 338.386327] [<ffffffff8109b423>] kthread+0xd3/0xf0 [ 338.386349] [<ffffffff8109b350>] ? kthread_park+0x60/0x60 [ 338.386376] [<ffffffff817e1ee5>] ret_from_fork+0x25/0x30 [ 338.386401] Code: Bad RIP value. [ 338.386420] RIP [< (null)>] (null) [ 338.386443] RSP <ffffc90001bd7d40> [ 338.386458] CR2: 0000000000000000 [ 338.398508] ---[ end trace 4c66fcdc74b9a0a2 ]--- Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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