- 09 Jun, 2023 40 commits
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Lijo Lazar authored
It adds message support for FW notification on driver unload. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Asad Kamal authored
Add mem temperature as part of hw mon attributes for GC version 9.4.3 Signed-off-by:
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Asad Kamal authored
Update hw mon attributes for GC Version 9.4.3 to valid ones on APU and Non APU systems v2: Group checks along existing one Added power limit & mclock for gc version 9.4.3 Signed-off-by:
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Lijo Lazar authored
PMFW will initialize the power limit values even if PPT throttler feature is disabled. Fetch the limit value from FW. Signed-off-by:
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Lijo Lazar authored
Use the interface version directly from PMFW interface header file rather than keeping another definition in common smu13 file. Signed-off-by:
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Asad kamal authored
Add interrupt handler for thermal throttler events from PMFW on SMUv13.0.6 Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Asad kamal authored
Update driver interface for SMU v13.0.6 to be compatible with PMFW v85.48 version Signed-off-by:
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Asad kamal authored
Update gfx clock frequency from metric table for SMU v13.0.6 Signed-off-by:
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Asad kamal authored
Update driver metrics table for SMU v13.0.6 to be compatible with PMFW v85.47 version Signed-off-by:
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Stanley.Yang authored
It should change logical instance to device instance to query ras info Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Le Ma authored
Avoid to mislead users as it's not a real error. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Signed-off-by:
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Mukul Joshi authored
Increase Max GPU instances to 64 to handle multi-socket system with GFX 9.4.3 asic. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Le Ma authored
On newer GPUs, the number of kernel rings are increased. Signed-off-by:
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Rajneesh Bhardwaj authored
On GFXIP9.4.3 APP APU where there is no dedicated VRAM domain handle VRAM BO allocation requests on CPU domain and validate them on GTT. Support for handling multi-socket and multi-numa partitions within a socket will be added by future patches, this enables 1P NPS1 asic bringup configuration. Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Rajneesh Bhardwaj authored
This adds dummy vram manager to support ASICs that do not have a dedicated or carvedout vram domain. Reviewed-by:
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Rajneesh Bhardwaj authored
[For 1P NPS1 mode driver bringup] Changes required to initialize the amdgpu driver with frontdoor firmware loading and discovery=2 with the native mode SBIOS that enables CPU GPU unified interleaved memory. sudo modprobe amdgpu discovery=2 Once PSP TMR region is reported via the ACPI interface, the dependency on the ip_discovery.bin will be removed. Choice of where to allocate driver table is given to each IP version. In general, both GTT and VRAM domains will be considered. If one of the tables has a strict restriction for VRAM domain, then only VRAM domain is considered. Reviewed-by:
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Asad kamal authored
Enable clock gating on IH v4.4.2 versions. Signed-off-by:
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Hawking Zhang authored
Persistent edc harvesting is supported in APP APU Signed-off-by:
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Hawking Zhang authored
Initialize mmhub v1_8 ras function. Signed-off-by:
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Hawking Zhang authored
Add reset_ras_error_status callback for mmhub v1_8. It will be used to reset mmhub error status. Signed-off-by:
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Hawking Zhang authored
Add query_ras_error_status callback for mmhub v1_8. It will be used to log mmhub error status. Signed-off-by:
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Hawking Zhang authored
Add reset_ras_error_count callback for mmhub v1_8. It will be used to reset mmhub ras error count. Signed-off-by:
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Hawking Zhang authored
Add query_ras_error_count callback for mmhub v1_8. It will be used to query and log mmhub error count and memory block. Signed-off-by:
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Hawking Zhang authored
add new ras error status registers introduced in mmhub v1_8_0 to log mmea and mm_cane ras err, including MMEAx_UE|CE_ERR_STATUS_LO|HI MM_CANE_UE|CE_ERR_STATUS_LO|HI Signed-off-by:
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Hawking Zhang authored
Initialize sdma v4_4_2 ras function and interrupt handler. Signed-off-by:
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Hawking Zhang authored
Add reset_ras_error_count callback for sdma v4_4_2. It will be used to reset sdma ras error count. Signed-off-by:
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Hawking Zhang authored
Add query_ras_error_count callback for sdma v4_4_2. It will be used to query and log sdma uncorrectable error count and memory block. Signed-off-by:
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Hawking Zhang authored
SDMA_UE_ERR_STATUS_HI|LO are introduced in v4_4_2 to replace SDMA_EDC_COUNTER/COUNTER2 registers to log SDMA RAS errors Signed-off-by:
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Hawking Zhang authored
Add common helper to reset ras error status. It applies to IP blocks that follow the new ras error logging register design, and need to write 0 to reset the error status. For IP blocks that don't support the new design, please still implement ip specific helper. Signed-off-by:
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Hawking Zhang authored
Add common helper to query ras error status and log error information, including memory block id and erorr count. The helpers are applicable to IP blocks that follow the new ras error logging design. For IP blocks that don't support the new design, please still implement ip specific helper to query ras error. v2: optimize struct amdgpu_ras_err_status_reg_entry and the implementaion in helper (Lijo/Tao) Signed-off-by:
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Lijo Lazar authored
Enable clock gating on SDMAv4.4.2 versions. Leave memory light sleep to default. Signed-off-by:
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Le Ma authored
With SDMA_CTNL.CTXEMPTY_INT_ENABLE set, the F32 clock can be gated when SDMA finishes all job and goes to idle. And no specific interrupt handling is required in driver. Signed-off-by:
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Sonny Jiang authored
Add support for vcn_4_0_3 video codec query Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Jonathan Kim authored
If a CPU and GPU are xGMI connected but the GPU is hiveless with respect to other GPUs, create a new CPU-GPU hive using the GPU's PCI device location ID as the new hive ID to maintain fine grain memory access usage. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Philip Yang authored
kfd node allocation outside kfd->num_nodes loop is not needed and causes memory leak because kfd->num_nodes is at least equal to 1. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Rajneesh Bhardwaj authored
This allows backing ttm_tt structure with pages from different NUMA pools. Tested-by:
Graham Sider <graham.sider@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Lijo Lazar authored
For MQD init, an XCC's queue is selected with GRBM select. However, for initialization of MQD, values read from logical XCC0 registers are used. This results in garbage values being read from XCC0 whose queue is not selected. Change to read from the right XCC for MQD initialization. Signed-off-by:
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Harish Kasiviswanathan authored
‘for’ loop initial declarations are only allowed in C99 or C11 mode Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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Lijo Lazar authored
Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove programming that is not meant for GC 9.4.3. Signed-off-by:
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Lijo Lazar authored
Program different ranges in each XCC with MEC_DOORBELL_RANGE_LOWER/HIGHER. Keeping the same range causes CPF in other XCCs also to be busy when an IB packet is submitted to KCQ. Only the XCC which processes the packet comes back to idle afterwards and this causes other CPs not be idle. This in turn affects clockgating behavior as RLC doesn't get idle interrupt. LOWER/HIGHER covers only KIQ/KCQs which are per XCC queues. Assigning different ranges doesn't seem to have any side effect as user queue ranges are outside of this range. User queue tests - PM4 through KFD and AQL through rocr - have the same results after this change. Signed-off-by:
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