- 08 Jul, 2015 1 commit
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Paulo Zanoni authored
Because it makes more sense there, IMHO. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 07 Jul, 2015 3 commits
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Daniel Vetter authored
After the register save/restore code is gone there's just one user left and it just obfuscates that one. Remove it. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Reviewed-by:
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Daniel Vetter authored
Burning cpu cycles isn't awesome, so use sleeps instead. Signed-off-by:
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Daniel Vetter authored
Since that's really what we want to test for. Note remove the gen5 case doesn't change anything: In intel_setup_outputs ilk is handled already in the HAS_PCH_SPLIT case, and the register save/restore code touches registers which simply doesn't exist anymore at all. v2: Drop UMS parts. v3: Update commit message to reflect that the reg save/restore code is gone (Ville). Reviewed-by:
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- 06 Jul, 2015 36 commits
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Ville Syrjälä authored
Follow the correct pipe vs port disable sequence for the PCH LVDS ports, ie. disable the port after the pipe. Other PCH port were already converted in the following commits: 1ea56e26 drm/i915: Disable CRT port after pipe on PCH platforms 3c65d1d1 drm/i915: Disable SDVO port after the pipe on PCH platforms a4790cec drm/i915: Disable HDMI port after the pipe on PCH platforms 08aff3fe drm/i915: Move DP port disable to post_disable for pch platforms but LVDS was forgotten. Signed-off-by:
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Matt Roper authored
intel_atomic_setup_scalers() dereferences 'plane' before the plane has been assigned. The plane ID assignment doing this dereference is only needed for debugging messages later in the function, so just move the assignment farther down the function to a point where plane will no longer be NULL. This was introduced in: commit 133b0d12 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Mon Jun 15 12:33:39 2015 +0200 drm/i915: Clean up intel_atomic_setup_scalers slightly. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Reported-by:Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Mika Kuoppala authored
Now when we have requests this deep on call chain, we can mark the elsp being submitted when it actually is. Remove temp variable and readjust commenting to more closely fit to the code. v2: Avoid tmp variable and reduce number of writes (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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Mika Kuoppala authored
Pass around requests to carry context deeper in callchain. Signed-off-by:
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Mika Kuoppala authored
Pass around requests to carry context deeper in callchain. Signed-off-by:
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Mika Kuoppala authored
Pass around requests to carry context deeper in callchain. Signed-off-by:
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Mika Kuoppala authored
In preparation to make intel_lr_context_pin|unpin to accept requests, assign ringbuf into request before we call the pinning. v2: No need to unset ringbuf on error path (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Mika Kuoppala authored
Pass around requests to carry context deeper in callchain. Signed-off-by:
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Mika Kuoppala authored
Pass around requests to carry context deeper in callchain. Signed-off-by:
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Niu,Bing authored
It is found that i915 will not reset gpu under execlist mode when unload module. that will lead to some issues when unload/load module with different submission mode. e.g. from execlist mode to ring buffer mode via loading/unloading i915. Because HW is not in a reset state and registers are not clean under such condition. Signed-off-by:
Niu,Bing <bing.niu@intel.com> Reviewed-by:
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Arun Siluvery authored
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL instruction but there is a slight complication as this is applied in WA batch where the values are only initialized once. Dave identified an issue with the current implementation where the register value is read once at the beginning and it is reused; this patch corrects this by saving the register value to memory, update register with the bit of our interest and restore it back with original value. This implementation uses MI_LOAD_REGISTER_MEM which is currently only used by command parser and was using a default length of 0. This is now updated with correct length and moved to appropriate place. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by:
Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by:
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Paulo Zanoni authored
Now all the functions called by other files check whether FBC has been initialized. This allows us to drop the checks on the static functions. v2: - s/HAS_FBC/dev_priv->display.enable_fbc/ everywhere but the init function (Chris). Suggested-by:
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Paulo Zanoni authored
Everything is covered either by fbc.lock or mm.stolen_lock, and intel_fbc.c is already responsible for grabbing the appropriate locks when it needs them. Reviewed-by:
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Paulo Zanoni authored
So don't grab the lock before calling the function. Reviewed-by:
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Paulo Zanoni authored
So release the lock earlier. Reviewed-by:
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Paulo Zanoni authored
Make sure we're not going to have weird races in really weird cases where a lot of different CRTCs are doing rendering and modesets at the same time. With this change and the stolen_lock from the previous patch, we can start removing the struct_mutex locking we have around FBC in the next patches. v2: - Rebase (6 months later) - Also lock debugfs and stolen. v3: - Don't lock a single value read (Chris). - Replace lockdep assertions with WARNs (Daniel). - Improve commit message. - Don't forget intel_pre_plane_update() locking. v4: - Don't remove struct_mutex at intel_pre_plane_update() (Chris). - Add comment regarding locking dependencies (Chris). - Rebase after the stolen code rework. - Rebase again after drm-intel-nightly changes. v5: - Rebase after the new stolen_lock patch. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4) Signed-off-by:
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Paulo Zanoni authored
Which should protect dev_priv->mm.stolen usage. This will allow us to simplify the relationship between stolen memory, FBC and struct_mutex. v2: - Rebase after the stolen_remove_node() dev_priv patch move. - I realized that after we fixed a few things related to the FBC CFB size checks, we're not reallocating the CFB anymore with FBC enabled, so we can just move all the locking to i915_gem_stolen.c and stop worrying about freezing all the stolen alocations while freeing/rellocating the CFB. This allows us to fix the "Too coarse" observation from Chris. Suggested-by: -
Paulo Zanoni authored
With the abstractions created by the last patch, we can move this code and the only thing inside intel_fbc.c that knows about dev_priv->mm is the code that reads stolen_base. We also had to move a call to i915_gem_stolen_cleanup_compression() - now called intel_fbc_cleanup_cfb() - outside i915_gem_stolen.c. v2: - Rebase after the remove_node() changes on the previous patch. Requested-by:
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Paulo Zanoni authored
We want to move the FBC code out of i915_gem_stolen.c, but that code directly adds/removes stolen memory nodes. Let's create this abstraction, so i915_gme_stolen.c is still in control of all the stolen memory handling. The abstraction will also allow us to add locking assertions later. v2: - Add dev_priv as remove_node() argument since we'll need it later (Chris). Requested-by: -
Ville Syrjälä authored
Kill the extra intel_pre_plane_update() I accidentally added in commit 852eb00d Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Jun 24 22:00:07 2015 +0300 drm/i915: Try to make sure cxsr is disabled around plane enable/disable This fixes a load of warnings from the frontbuffer tracking. Testcase: igt/kms_frontbuffer_tracking/fbc-1p-rte Tested-by:
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Jani Nikula authored
Adding support for did2, or the extended support display devices ID list, increases the total to 15. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Acked-by:
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Jani Nikula authored
Make it easier to handle the extended didl. No functional changes. Signed-off-by:
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Jani Nikula authored
Conform to same style as the rest of the driver. Signed-off-by:
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Jani Nikula authored
Inluding extended didl and cpdl fields Present since opregion version 3.0. Signed-off-by:
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Jani Nikula authored
Signed-off-by:
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Jani Nikula authored
Add an overview of the drm/i915 hotplug handling. Signed-off-by:
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Jani Nikula authored
Clarify that audio enable/disable sequences are part of the modeset sequence. Signed-off-by:
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Paulo Zanoni authored
drivers/gpu/drm/i915/intel_ddi.c: In function ‘intel_prepare_ddi’: drivers/gpu/drm/i915/intel_ddi.c:517:6: warning: ‘ddi_translations_fdi’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (ddi_translations_fdi) ^ drivers/gpu/drm/i915/intel_ddi.c:446:30: note: ‘ddi_translations_fdi’ was declared here const struct ddi_buf_trans *ddi_translations_fdi; ^ This line used to be there, but was removed by: commit f8896f5d Author: David Weinehall <david.weinehall@linux.intel.com> Date: Thu Jun 25 11:11:03 2015 +030 drm/i915/skl: Buffer translation improvements Cc: David Weinehall <david.weinehall@linux.intel.com> Signed-off-by: -
Abdiel Janulgue authored
Ensures that the batch buffer is executed by the resource streamer. And will let userspace know whether Resource Streamer is supported in the kernel. v2: Don't skip 1<<15 for the exec flags (Jani Nikula) v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson) (from getparam patch) v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after I915_PARAM_HAS_GPU_RESET. v3: Only advertise RS support for hardware that supports it. v4: Add HAS_RESOURCE_STREAMER() macro (Chris) Testcase: igt/gem_exec_params Cc: Jani Nikula <jani.nikula@intel.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [danvet: squash in getparam patch since it'd break bisect, suggested by Chris.] Signed-off-by:
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Abdiel Janulgue authored
GEN8 and above uses Execlists by default instead of the legacy ringbuffer for batch execution. This patch enables the resource streamer bits when required. Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com> This version also adds the required bits to enable GEN8 Resource Streamer context save and restore for Execlists. Cc: ville.syrjala@linux.intel.com Signed-off-by:
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Abdiel Janulgue authored
Also clarify comments on context size that the extra state for Resource Streamer is included. v2: Don't remove the extended save/restore enabled for older platforms. (Ville) Use new MI_SET_CONTEXT defines for HSW RS save/restore state instead of extended save/restore. (Daniel) Suggested-by: -
Abdiel Janulgue authored
Adds support for enabling the resource streamer on the legacy ringbuffer for HSW and GEN8. Reviewed-by:
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Vandana Kannan authored
This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review comment addressed - dcoampovr_en_h variable not required Based on a discussion with Siva, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment v3: Move DCO amplitude default value to i915_reg.h. Suggested by Siva. Signed-off-by:
Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2] [danvet: Spell out BUN since not everyone knows what this means.] Signed-off-by:
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Ville Syrjälä authored
HDMI 12bpc should be working fine now. Let it loose. This reverts commit 5e3daaca. v2: Rebased due to CHV/BXT port clock check improvemnts Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Ville Syrjälä authored
CHV/BXT DPLL can't generate frequencies in the 216-240 MHz range. Account for that when checking whether the HDMI port clock is valid. This is particularly important for BXT since it can otherwise do 12bpc, and standard 1920x1080p60 CEA modes land right in the middle of that range when the clock gets multiplied to account for 12bpc. With the extra checks we will now filter out any mode where both 8bpc and 12bpc clock are within the gap. During modeset we then pick whichever mode works, favoring 12bpc if both are possible. 12bpc isn't supported on CHV so we simply end up filtering out any mode where the 8bpc port clock is in the gap. v2: Fix crtc_clock vs. port_clock fumble in compute_config() (Imre) Signed-off-by:
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Ville Syrjälä authored
Increase the HDMI port minimum port clock from 20 to 25 MHz. This is is the minimum listed in the DVI/HDMI specs, and it's also the documented minimum DPLL frequency for most of our platforms. Signed-off-by:
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