Commit 88dcc723 authored by Kirill Smelkov's avatar Kirill Smelkov

X test for bug described in prev commit

parent adfec875
...@@ -115,6 +115,7 @@ func TestCache(t *testing.T) { ...@@ -115,6 +115,7 @@ func TestCache(t *testing.T) {
hello := []byte("hello") hello := []byte("hello")
world := []byte("world!!") world := []byte("world!!")
zz := []byte("zz")
www := []byte("www") www := []byte("www")
tstor := &tStorage{ tstor := &tStorage{
...@@ -123,7 +124,8 @@ func TestCache(t *testing.T) { ...@@ -123,7 +124,8 @@ func TestCache(t *testing.T) {
{4, hello, nil}, {4, hello, nil},
{7, nil, ioerr}, {7, nil, ioerr},
{10, world, nil}, {10, world, nil},
{18, www, nil}, {16, zz, nil},
{18, www, nil}, // XXX +2
}, },
}, },
} }
...@@ -288,8 +290,8 @@ func TestCache(t *testing.T) { ...@@ -288,8 +290,8 @@ func TestCache(t *testing.T) {
checkOCE(1, rce1_b4, rce1_b7, rce1_b8, rce1_b10, rce1_b12) checkOCE(1, rce1_b4, rce1_b7, rce1_b8, rce1_b10, rce1_b12)
checkMRU(12, rce1_b12, rce1_b10, rce1_b8, rce1_b7, rce1_b4) checkMRU(12, rce1_b12, rce1_b10, rce1_b8, rce1_b7, rce1_b4)
// simulate case where <14 and <16 were loaded in parallel, both are ready // simulate case where <14 (α) and <16 (β) were loaded in parallel, both are ready
// but <14 takes oce lock first before <16 and so <12 is not yet merged // but <14 (α) takes oce lock first before <16 and so <12 is not yet merged
// with <16 -> <12 and <14 should be merged into <16. // with <16 -> <12 and <14 should be merged into <16.
// (manually add rce1_b16 so it is not merged with <12) // (manually add rce1_b16 so it is not merged with <12)
...@@ -331,6 +333,32 @@ func TestCache(t *testing.T) { ...@@ -331,6 +333,32 @@ func TestCache(t *testing.T) {
checkOCE(1, rce1_b4, rce1_b7, rce1_b8, rce1_b10, rce1_b16) checkOCE(1, rce1_b4, rce1_b7, rce1_b8, rce1_b10, rce1_b16)
checkMRU(12, rce1_b16, rce1_b10, rce1_b8, rce1_b7, rce1_b4) checkMRU(12, rce1_b16, rce1_b10, rce1_b8, rce1_b7, rce1_b4)
// similar race in between <17 and <18 but now β (<18) takes oce lock first:
rce1_b17, new17 := c.lookupRCE(xidlt(1,17))
ok1(new17)
rce1_b18, new18 := c.lookupRCE(xidlt(1,18))
ok1(new18)
// (<17 loads but not yet takes oce lock)
rce1_b17.serial = 16
rce1_b17.data = zz
close(rce1_b17.ready)
ok1(rce1_b17.loaded())
checkOCE(1, rce1_b4, rce1_b7, rce1_b8, rce1_b10, rce1_b16, rce1_b17, rce1_b18)
checkMRU(12, rce1_b16, rce1_b10, rce1_b8, rce1_b7, rce1_b4) // no <17 and <18 yet
// (<18 loads and takes oce lock first - merge <17 with <18)
c.loadRCE(rce1_b18, 1)
checkRCE(rce1_b18, 18, 16, zz, nil)
checkRCE(rce1_b17, 17, 16, zz, nil)
checkOCE(1, rce1_b4, rce1_b7, rce1_b8, rce1_b10, rce1_b16, rce1_b18)
checkMRU(14, rce1_b18, rce1_b16, rce1_b10, rce1_b8, rce1_b7, rce1_b4)
// XXX temp
return
/*
// load =17 -> <16 merged with <18 // load =17 -> <16 merged with <18
checkLoad(xideq(1,17), nil, 0, &zodb.ErrXidMissing{xideq(1,17)}) checkLoad(xideq(1,17), nil, 0, &zodb.ErrXidMissing{xideq(1,17)})
ok1(len(oce1.rcev) == 5) ok1(len(oce1.rcev) == 5)
...@@ -432,6 +460,7 @@ func TestCache(t *testing.T) { ...@@ -432,6 +460,7 @@ func TestCache(t *testing.T) {
checkLoad(xidlt(1,18), world, 10, nil) checkLoad(xidlt(1,18), world, 10, nil)
checkMRU(15, rce1_b18, rce1_b7, rce1_b9, rce1_b20, rce1_b10, rce1_b8, rce1_b4) checkMRU(15, rce1_b18, rce1_b7, rce1_b9, rce1_b20, rce1_b10, rce1_b8, rce1_b4)
*/
// XXX verify LRU eviction // XXX verify LRU eviction
......
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