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config-amarisoft
Commit 1bd8c3dd authored by Lu Xu's avatar Lu Xu 👀
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Amarisoft 2021-09-18 config

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enb/drb.cfg
View file @ 1bd8c3dd
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
/**************************************** GBR */ /**************************************** GBR */
{ {
qci: 1, /* UM - real time (RTP for VOIP) */ qci: 1, /* UM - real time (RTP for VOIP) */
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_Size: 7, pdcp_SN_Size: 7,
...@@ -23,6 +24,23 @@ ...@@ -23,6 +24,23 @@
}, },
*/ */
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 12,
pdcp_SN_SizeDL: 12,
statusReportRequired: false,
outOfOrderDelivery: false,
/* ROHC header compression */
/*
headerCompression: {
maxCID: 15,
profile0x0001: true, // RTP profile
profile0x0002: true, // UDP profile
profile0x0004: false, // IP profile
},
*/
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 5, sn_FieldLength: 5,
...@@ -45,10 +63,20 @@ ...@@ -45,10 +63,20 @@
}, },
{ {
qci: 2, /* UM - real time (video) */ qci: 2, /* UM - real time (video) */
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 150, /* in ms, 0 means infinity */ discardTimer: 150, /* in ms, 0 means infinity */
pdcp_SN_Size: 12, pdcp_SN_Size: 12,
}, },
nr_pdcp_config: {
discardTimer: 150, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: false,
outOfOrderDelivery: false,
t_Reordering: 0,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 10, sn_FieldLength: 10,
...@@ -73,6 +101,15 @@ ...@@ -73,6 +101,15 @@
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_Size: 12, pdcp_SN_Size: 12,
}, },
nr_pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: false,
outOfOrderDelivery: false,
t_Reordering: 0,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 10, sn_FieldLength: 10,
...@@ -97,6 +134,14 @@ ...@@ -97,6 +134,14 @@
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
statusReportRequired: true, statusReportRequired: true,
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: true,
outOfOrderDelivery: false,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_am: { ul_am: {
t_PollRetransmit: 80, /* in ms */ t_PollRetransmit: 80, /* in ms */
...@@ -120,6 +165,7 @@ ...@@ -120,6 +165,7 @@
}, },
{ {
qci: 65, /* UM - real time (MC-PTT voice) */ qci: 65, /* UM - real time (MC-PTT voice) */
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_Size: 7, pdcp_SN_Size: 7,
...@@ -133,6 +179,24 @@ ...@@ -133,6 +179,24 @@
}, },
*/ */
}, },
nr_pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 12,
pdcp_SN_SizeDL: 12,
statusReportRequired: false,
outOfOrderDelivery: false,
t_Reordering: 0,
/* ROHC header compression */
/*
headerCompression: {
maxCID: 15,
profile0x0001: true, // RTP profile
profile0x0002: true, // UDP profile
profile0x0004: false, // IP profile
},
*/
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 5, sn_FieldLength: 5,
...@@ -155,10 +219,20 @@ ...@@ -155,10 +219,20 @@
}, },
{ {
qci: 66, /* UM - real time (non MC-PTT voice) */ qci: 66, /* UM - real time (non MC-PTT voice) */
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 150, /* in ms, 0 means infinity */ discardTimer: 150, /* in ms, 0 means infinity */
pdcp_SN_Size: 12, pdcp_SN_Size: 12,
}, },
nr_pdcp_config: {
discardTimer: 150, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: false,
outOfOrderDelivery: false,
t_Reordering: 0,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 10, sn_FieldLength: 10,
...@@ -181,10 +255,20 @@ ...@@ -181,10 +255,20 @@
}, },
{ {
qci: 67, /* UM - Mission Critical Video user plane */ qci: 67, /* UM - Mission Critical Video user plane */
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_Size: 12, pdcp_SN_Size: 12,
}, },
nr_pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: false,
outOfOrderDelivery: false,
t_Reordering: 0,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 10, sn_FieldLength: 10,
...@@ -210,6 +294,14 @@ ...@@ -210,6 +294,14 @@
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
statusReportRequired: true, statusReportRequired: true,
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: true,
outOfOrderDelivery: false,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_am: { ul_am: {
t_PollRetransmit: 80, /* in ms */ t_PollRetransmit: 80, /* in ms */
...@@ -237,6 +329,14 @@ ...@@ -237,6 +329,14 @@
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
statusReportRequired: true, statusReportRequired: true,
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: true,
outOfOrderDelivery: false,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_am: { ul_am: {
t_PollRetransmit: 80, /* in ms */ t_PollRetransmit: 80, /* in ms */
...@@ -264,6 +364,15 @@ ...@@ -264,6 +364,15 @@
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_Size: 12, pdcp_SN_Size: 12,
}, },
nr_pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: false,
outOfOrderDelivery: false,
t_Reordering: 0,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_um: { ul_um: {
sn_FieldLength: 10, sn_FieldLength: 10,
...@@ -288,6 +397,14 @@ ...@@ -288,6 +397,14 @@
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
statusReportRequired: true, statusReportRequired: true,
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: true,
outOfOrderDelivery: false,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_am: { ul_am: {
t_PollRetransmit: 80, /* in ms */ t_PollRetransmit: 80, /* in ms */
...@@ -353,6 +470,14 @@ ...@@ -353,6 +470,14 @@
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
statusReportRequired: true, statusReportRequired: true,
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: true,
outOfOrderDelivery: false,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_am: { ul_am: {
t_PollRetransmit: 80, /* in ms */ t_PollRetransmit: 80, /* in ms */
...@@ -380,6 +505,14 @@ ...@@ -380,6 +505,14 @@
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
statusReportRequired: true, statusReportRequired: true,
}, },
nr_pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18,
pdcp_SN_SizeDL: 18,
statusReportRequired: true,
outOfOrderDelivery: false,
restrict_to_ng_enb: true,
},
rlc_config: { rlc_config: {
ul_am: { ul_am: {
t_PollRetransmit: 80, /* in ms */ t_PollRetransmit: 80, /* in ms */
......
enb/drb_nr.cfg
View file @ 1bd8c3dd
...@@ -10,11 +10,10 @@ ...@@ -10,11 +10,10 @@
{ {
qci: 1, /* UM - real time (RTP for VOIP) */ qci: 1, /* UM - real time (RTP for VOIP) */
use_for_en_dc: false, use_for_en_dc: false,
#if EPS_FALLBACK > 0 #if EPS_FALLBACK > 0
trigger_eps_fallback: true, trigger_eps_fallback: true,
#endif #endif
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 12, pdcp_SN_SizeUL: 12,
...@@ -50,6 +49,11 @@ ...@@ -50,6 +49,11 @@
}, },
{ {
qci: 2, /* UM - real time (video) */ qci: 2, /* UM - real time (video) */
use_for_en_dc: false,
#if EPS_FALLBACK > 0
trigger_eps_fallback: true,
#endif
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 150, /* in ms, 0 means infinity */ discardTimer: 150, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18, pdcp_SN_SizeUL: 18,
...@@ -133,6 +137,10 @@ ...@@ -133,6 +137,10 @@
{ {
qci: 65, /* UM - real time (MC-PTT voice) */ qci: 65, /* UM - real time (MC-PTT voice) */
use_for_en_dc: false, use_for_en_dc: false,
#if EPS_FALLBACK > 0
trigger_eps_fallback: true,
#endif
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 12, pdcp_SN_SizeUL: 12,
...@@ -169,6 +177,10 @@ ...@@ -169,6 +177,10 @@
{ {
qci: 66, /* UM - real time (non MC-PTT voice) */ qci: 66, /* UM - real time (non MC-PTT voice) */
use_for_en_dc: false, use_for_en_dc: false,
#if EPS_FALLBACK > 0
trigger_eps_fallback: true,
#endif
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 150, /* in ms, 0 means infinity */ discardTimer: 150, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18, pdcp_SN_SizeUL: 18,
...@@ -196,6 +208,10 @@ ...@@ -196,6 +208,10 @@
{ {
qci: 67, /* UM - Mission Critical Video user plane */ qci: 67, /* UM - Mission Critical Video user plane */
use_for_en_dc: false, use_for_en_dc: false,
#if EPS_FALLBACK > 0
trigger_eps_fallback: true,
#endif
ims_dedicated_bearer: true,
pdcp_config: { pdcp_config: {
discardTimer: 100, /* in ms, 0 means infinity */ discardTimer: 100, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18, pdcp_SN_SizeUL: 18,
...@@ -401,7 +417,6 @@ ...@@ -401,7 +417,6 @@
}, },
{ {
qci: 70, /* AM - MC data */ qci: 70, /* AM - MC data */
use_for_en_dc: false,
pdcp_config: { pdcp_config: {
discardTimer: 0, /* in ms, 0 means infinity */ discardTimer: 0, /* in ms, 0 means infinity */
pdcp_SN_SizeUL: 18, pdcp_SN_SizeUL: 18,
......
enb/enb-2cc.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
......
enb/enb-2cell-ho.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#define N_ANTENNA_DL 1 // Values: 1 (SISO), 2 (MIMO 2x2) #define N_ANTENNA_DL 1 // Values: 1 (SISO), 2 (MIMO 2x2)
#define N_ANTENNA_UL 1 // Values: 1, 2 #define N_ANTENNA_UL 1 // Values: 1, 2
#define CHANNEL_SIM 0 // Values: 0 (channel simulator disabled), 1 (channel simulator enabled) #define CHANNEL_SIM 0 // Values: 0 (channel simulator disabled), 1 (channel simulator enabled)
#define NG_ENB 0 // 1 for ng-eNB
{ {
/* Log filter: syntax: layer.field=value[,...] /* Log filter: syntax: layer.field=value[,...]
...@@ -58,6 +59,15 @@ ...@@ -58,6 +59,15 @@
mme_addr: "127.0.1.100", mme_addr: "127.0.1.100",
}, },
], ],
#if NG_ENB == 1
amf_list: [
{
/* address of AMF for NGAP connection. Must be modified if the AMF
runs on a different host. */
amf_addr: "127.0.1.100",
},
],
#endif
/* GTP bind address (=address of the ethernet interface connected to /* GTP bind address (=address of the ethernet interface connected to
the MME). Must be modified if the MME runs on a different host. */ the MME). Must be modified if the MME runs on a different host. */
gtp_addr: "127.0.1.1", gtp_addr: "127.0.1.1",
...@@ -91,7 +101,10 @@ ...@@ -91,7 +101,10 @@
dl_earfcn: 1575, dl_earfcn: 1575,
#endif #endif
cell_id: 0x1a2e002, cell_id: 0x1a2e002,
tac: 1 tac: 1,
#if NG_ENB == 1
tac_5gc: 10,
#endif
}, },
], ],
}, },
...@@ -118,7 +131,10 @@ ...@@ -118,7 +131,10 @@
dl_earfcn: 3100, dl_earfcn: 3100,
#endif #endif
cell_id: 0x1a2e001, cell_id: 0x1a2e001,
tac: 1 tac: 1,
#if NG_ENB == 1
tac_5gc: 10,
#endif
}, },
], ],
} }
...@@ -131,6 +147,12 @@ ...@@ -131,6 +147,12 @@
plmn_list: [ plmn_list: [
"00101", "00101",
], ],
#if NG_ENB == 1
plmn_list_5gc: [ {
tac: 10,
plmn_ids: [{ plmn: "00101", reserved: false }],
}],
#endif
n_antenna_dl: N_ANTENNA_DL, /* number of DL antennas */ n_antenna_dl: N_ANTENNA_DL, /* number of DL antennas */
n_antenna_ul: N_ANTENNA_UL, /* number of UL antennas */ n_antenna_ul: N_ANTENNA_UL, /* number of UL antennas */
......
enb/enb-3cc.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
......
enb/enb-catm1-nbiot.cfg
View file @ 1bd8c3dd
/* lteenb configuration file example for Category M1 UEs /* lteenb configuration file example for Category M1 UEs
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
...@@ -461,6 +461,7 @@ ...@@ -461,6 +461,7 @@
//br_dl_sf_bitmap : "0001110000011100000111000001110000011100", //br_dl_sf_bitmap : "0001110000011100000111000001110000011100",
}, },
edrx: true
}, },
#endif #endif
} }
enb/enb-catm1.cfg
View file @ 1bd8c3dd
/* lteenb configuration file example for Category M1 UEs /* lteenb configuration file example for Category M1 UEs
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
...@@ -352,5 +352,7 @@ ...@@ -352,5 +352,7 @@
allowing higher throughput (up to 3 DL and UL subframes every 8 subframes) */ allowing higher throughput (up to 3 DL and UL subframes every 8 subframes) */
//br_dl_sf_bitmap : "0001110000011100000111000001110000011100", //br_dl_sf_bitmap : "0001110000011100000111000001110000011100",
}, },
edrx: true
}, },
} }
enb/enb-mbms.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
{ {
......
enb/enb-nbiot-standalone.cfg
View file @ 1bd8c3dd
/* lteenb configuration file example for NB-IoT (standalone mode) /* lteenb configuration file example for NB-IoT (standalone mode)
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2016-2021 Amarisoft * Copyright (C) 2016-2021 Amarisoft
*/ */
{ {
......
enb/enb-nbiot.cfg
View file @ 1bd8c3dd
/* lteenb configuration file example for NB-IoT (in-band, guard-band and standalone mode) /* lteenb configuration file example for NB-IoT (in-band, guard-band and standalone mode)
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2016-2021 Amarisoft * Copyright (C) 2016-2021 Amarisoft
*/ */
......
enb/enb-tm-pdsch.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
......
enb/enb.default.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
#define TDD 1 // Values: 0 (FDD), 1(TDD) #define TDD 0 // Values: 0 (FDD), 1(TDD)
#define N_RB_DL 100 // Values: 6 (1.4 MHz), 15 (3MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz) #define N_RB_DL 25 // Values: 6 (1.4 MHz), 15 (3MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz)
#define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2) #define N_ANTENNA_DL 1 // Values: 1 (SISO), 2 (MIMO 2x2)
#define N_ANTENNA_UL 2 // Values: 1, 2 #define N_ANTENNA_UL 1 // Values: 1, 2
#define CHANNEL_SIM 0 // Values: 0 (channel simulator disabled), 1 (channel simulator enabled) #define CHANNEL_SIM 0 // Values: 0 (channel simulator disabled), 1 (channel simulator enabled)
#define NG_ENB 0 // 1 for ng-eNB
{ {
/* Log filter: syntax: layer.field=value[,...] /* Log filter: syntax: layer.field=value[,...]
...@@ -51,6 +52,15 @@ ...@@ -51,6 +52,15 @@
mme_addr: "127.0.1.100", mme_addr: "127.0.1.100",
}, },
], ],
#if NG_ENB == 1
amf_list: [
{
/* address of AMF for NGAP connection. Must be modified if the AMF
runs on a different host. */
amf_addr: "127.0.1.100",
},
],
#endif
/* GTP bind address (=address of the ethernet interface connected to /* GTP bind address (=address of the ethernet interface connected to
the MME). Must be modified if the MME runs on a different host. */ the MME). Must be modified if the MME runs on a different host. */
gtp_addr: "127.0.1.1", gtp_addr: "127.0.1.1",
...@@ -65,10 +75,16 @@ ...@@ -65,10 +75,16 @@
plmn_list: [ plmn_list: [
"00101", "00101",
], ],
#if NG_ENB == 1
plmn_list_5gc: [ {
tac: 10,
plmn_ids: [{ plmn: "00101", reserved: false }],
}],
#endif
#if TDD == 1 #if TDD == 1
dl_earfcn: 38050, /* 2600 MHz (band 38) */ //dl_earfcn: 38050, /* 2600 MHz (band 38) */
//dl_earfcn: 40620, /* 2593 MHz (band 41) */ dl_earfcn: 40620, /* 2593 MHz (band 41) */
//dl_earfcn: 42590, /* 3500 MHz (band 42) */ //dl_earfcn: 42590, /* 3500 MHz (band 42) */
#else #else
//dl_earfcn: 300, /* DL center frequency: 2132 MHz (Band 1) */ //dl_earfcn: 300, /* DL center frequency: 2132 MHz (Band 1) */
......
enb/gnb-2cc-nsa.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* LTE cell MIMO 2x2 + 2CC NR cell */ * LTE cell MIMO 2x2 + 2CC NR cell */
#define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD) #define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD)
#define NR_TDD 0 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 0 // Values: 0 (NR FDD), 1(NR TDD)
#define NR_TDD_CONFIG 2 // Values: 1, 2 or 3 #define NR_TDD_CONFIG 2 // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define N_RB_DL 100 // Values: 6 (1.4MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz) #define N_RB_DL 100 // Values: 6 (1.4MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz)
#define N_ANTENNA_DL 4 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define N_ANTENNA_DL 4 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define N_ANTENNA_UL 1 // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX) #define N_ANTENNA_UL 1 // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX)
#define NR_BANDWIDTH 100 // NR cell bandwidth #define NR_BANDWIDTH 100 // NR cell bandwidth
#define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
{ {
log_options: "all.level=debug,all.max_size=1", log_options: "all.level=debug,all.max_size=1",
...@@ -356,6 +357,19 @@ ...@@ -356,6 +357,19 @@
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 0, ul_symbols: 0,
#elif NR_TDD_CONFIG == 4
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
#endif #endif
}, },
}, },
...@@ -381,13 +395,17 @@ ...@@ -381,13 +395,17 @@
prach: { prach: {
#if NR_TDD == 1 #if NR_TDD == 1
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -423,20 +441,8 @@ ...@@ -423,20 +441,8 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if NR_TDD == 1
#if NR_TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif NR_TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif NR_TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
...@@ -671,32 +677,30 @@ ...@@ -671,32 +677,30 @@
freq_hopping: true, freq_hopping: true,
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -712,9 +716,8 @@ ...@@ -712,9 +716,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-2cc-sa.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* NR SA 2CC FDD or TDD cell */ * NR SA 2CC FDD or TDD cell */
#define TDD 0 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 0 // Values: 0 (NR FDD), 1(NR TDD)
#define TDD_CONFIG 2 // Values: 1, 2 or 3 #define NR_TDD_CONFIG 2 // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define N_ANTENNA_DL 1 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define N_ANTENNA_DL 1 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define N_ANTENNA_UL 1 // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX) #define N_ANTENNA_UL 1 // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX)
#define BANDWIDTH 20 // NR cell bandwidth #define NR_BANDWIDTH 20 // NR cell bandwidth
#define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
{ {
log_options: "all.level=debug,all.max_size=1", log_options: "all.level=debug,all.max_size=1",
...@@ -64,7 +65,7 @@ ...@@ -64,7 +65,7 @@
{cell_id: 2}, {cell_id: 2},
], ],
#if TDD == 1 #if NR_TDD == 1
band: 78, band: 78,
dl_nr_arfcn: 621300, dl_nr_arfcn: 621300,
#else #else
...@@ -80,7 +81,7 @@ ...@@ -80,7 +81,7 @@
{cell_id: 1}, {cell_id: 1},
], ],
#if TDD == 1 #if NR_TDD == 1
band: 78, band: 78,
dl_nr_arfcn: 627300, dl_nr_arfcn: 627300,
#else #else
...@@ -92,34 +93,47 @@ ...@@ -92,34 +93,47 @@
nr_cell_default: { nr_cell_default: {
subcarrier_spacing: 30, /* kHz */ subcarrier_spacing: 30, /* kHz */
bandwidth: BANDWIDTH, /* MHz */ bandwidth: NR_BANDWIDTH, /* MHz */
n_antenna_dl: N_ANTENNA_DL, n_antenna_dl: N_ANTENNA_DL,
n_antenna_ul: N_ANTENNA_UL, n_antenna_ul: N_ANTENNA_UL,
/* force the timing TA offset (optional) */ /* force the timing TA offset (optional) */
// n_timing_advance_offset: 39936, // n_timing_advance_offset: 39936,
#if TDD == 1 #if NR_TDD == 1
tdd_ul_dl_config: { tdd_ul_dl_config: {
pattern1: { pattern1: {
#if TDD_CONFIG == 1 #if NR_TDD_CONFIG == 1
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: /* 6 */ 2, dl_symbols: /* 6 */ 2,
ul_slots: 2, ul_slots: 2,
ul_symbols: 0, ul_symbols: 0,
#elif TDD_CONFIG == 2 #elif NR_TDD_CONFIG == 2
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: 6, dl_symbols: 6,
ul_slots: 2, ul_slots: 2,
ul_symbols: 4, ul_symbols: 4,
#elif TDD_CONFIG == 3 #elif NR_TDD_CONFIG == 3
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 6, dl_slots: 6,
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 0, ul_symbols: 0,
#elif NR_TDD_CONFIG == 4
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
#endif #endif
}, },
}, },
...@@ -173,14 +187,18 @@ ...@@ -173,14 +187,18 @@
//pdsch_harq_ack_max: 2, //pdsch_harq_ack_max: 2,
prach: { prach: {
#if TDD == 1 #if NR_TDD == 1
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -221,21 +239,9 @@ ...@@ -221,21 +239,9 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if TDD == 1
#if TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
si_mcs: 6, si_mcs: 6,
/* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed /* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed
...@@ -469,32 +475,30 @@ ...@@ -469,32 +475,30 @@
freq_hopping: true, freq_hopping: true,
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -510,9 +514,8 @@ ...@@ -510,9 +514,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-dss.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* LTE FDD cell + NR FDD cell at the same frequency * LTE FDD cell + NR FDD cell at the same frequency
*/ */
...@@ -6,8 +6,8 @@ ...@@ -6,8 +6,8 @@
/* Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) */ /* Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) */
#define N_ANTENNA_DL 1 #define N_ANTENNA_DL 1
/* define it to allow SA NR (otherwise NSA NR) */ /* Values: 0 (NSA NR), 1 (SA and NSA NR) */
#define ALLOW_SA #define ALLOW_SA 1
/* define it to disable LTE-CRS: schedule NR only in LTE MBMS subframes */ /* define it to disable LTE-CRS: schedule NR only in LTE MBMS subframes */
//#define MBMS_ONLY //#define MBMS_ONLY
...@@ -59,7 +59,7 @@ ...@@ -59,7 +59,7 @@
/* high 24 bits of SIB1.cellIdentifier */ /* high 24 bits of SIB1.cellIdentifier */
enb_id: 0x1A2D0, enb_id: 0x1A2D0,
#ifdef ALLOW_SA #if ALLOW_SA
gnb_id_bits: 28, gnb_id_bits: 28,
gnb_id: 0x12345, gnb_id: 0x12345,
...@@ -93,7 +93,7 @@ ...@@ -93,7 +93,7 @@
nr_cell_list: [ nr_cell_list: [
{ {
rf_port: 0, rf_port: 0,
#ifdef ALLOW_SA #if ALLOW_SA
plmn_list: [ { plmn_list: [ {
tac: 100, tac: 100,
plmn: "00101", plmn: "00101",
...@@ -275,7 +275,7 @@ ...@@ -275,7 +275,7 @@
ssb_pos_bitmap: "0001", ssb_pos_bitmap: "0001",
ssb_period: 20, /* in ms */ ssb_period: 20, /* in ms */
#ifdef ALLOW_SA #if ALLOW_SA
cell_barred: false, cell_barred: false,
intra_freq_reselection: true, intra_freq_reselection: true,
q_rx_lev_min: -70, q_rx_lev_min: -70,
...@@ -313,7 +313,7 @@ ...@@ -313,7 +313,7 @@
}, },
pdcch: { pdcch: {
#ifdef ALLOW_SA #if ALLOW_SA
n_rb_coreset0: 48, n_rb_coreset0: 48,
n_symb_coreset0: 1, n_symb_coreset0: 1,
search_space0_index: 1, /* 1 symbol, starting at symbol 1 for odd SSB */ search_space0_index: 1, /* 1 symbol, starting at symbol 1 for odd SSB */
...@@ -353,9 +353,8 @@ ...@@ -353,9 +353,8 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
k1: 4,
mcs_table: "qam256", mcs_table: "qam256",
#if N_ANTENNA_DL >= 2 #if N_ANTENNA_DL >= 2
x_overhead: 12, /* 12 REs reserved for LTE CRS */ x_overhead: 12, /* 12 REs reserved for LTE CRS */
...@@ -363,7 +362,7 @@ ...@@ -363,7 +362,7 @@
x_overhead: 6, /* 6 REs reserved for LTE CRS */ x_overhead: 6, /* 6 REs reserved for LTE CRS */
#endif #endif
rar_mcs: 2, rar_mcs: 2,
#ifdef ALLOW_SA #if ALLOW_SA
si_mcs: 6, si_mcs: 6,
#endif #endif
/* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed /* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed
...@@ -428,9 +427,8 @@ ...@@ -428,9 +427,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-nsa-ho-lte.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* 2 LTE cell + NR cell */ * 2 LTE cell + NR cell */
#define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD) #define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD)
#define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD)
#define NR_TDD_CONFIG 2 // Values: 1, 2 or 3 #define NR_TDD_CONFIG 2 // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define N_RB_DL 100 // Values: 6 (1.4MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz) #define N_RB_DL 100 // Values: 6 (1.4MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz)
#define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define NR_BANDWIDTH 40 // NR cell bandwidth. With the PCIe SDR50 board, up to 50 MHz is supported. #define NR_BANDWIDTH 40 // NR cell bandwidth. With the PCIe SDR50 board, up to 50 MHz is supported.
// With the PCIe SDR100 board, up to 100 MHz is supported. // With the PCIe SDR100 board, up to 100 MHz is supported.
#define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
{ {
//log_options: "all.level=debug,all.max_size=1", //log_options: "all.level=debug,all.max_size=1",
...@@ -388,6 +389,19 @@ ...@@ -388,6 +389,19 @@
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 2, ul_symbols: 2,
#elif NR_TDD_CONFIG == 4
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
#endif #endif
}, },
}, },
...@@ -413,13 +427,17 @@ ...@@ -413,13 +427,17 @@
prach: { prach: {
#if NR_TDD == 1 #if NR_TDD == 1
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -457,20 +475,8 @@ ...@@ -457,20 +475,8 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if NR_TDD == 1
#if NR_TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif NR_TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif NR_TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
...@@ -705,32 +711,30 @@ ...@@ -705,32 +711,30 @@
freq_hopping: true, freq_hopping: true,
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -745,6 +749,8 @@ ...@@ -745,6 +749,8 @@
srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ],
#elif NR_TDD_CONFIG == 3 #elif NR_TDD_CONFIG == 3
srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ],
#elif NR_TDD_CONFIG == 4
srs_symbols: [ 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 ],
#endif #endif
srs_resource: [ srs_resource: [
{ {
...@@ -772,9 +778,8 @@ ...@@ -772,9 +778,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-nsa.cfg
View file @ 1bd8c3dd
This diff is collapsed.
enb/gnb-pscell-change.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* LTE cell + 2 NR cell */ * LTE cell + 2 NR cell */
#define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD) #define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD)
#define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD)
#define NR_TDD_CONFIG 2 // Values: 1, 2 or 3 #define NR_TDD_CONFIG 2 // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define N_RB_DL 100 // Values: 6 (1.4MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz) #define N_RB_DL 100 // Values: 6 (1.4MHz), 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz)
#define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define NR_BANDWIDTH 40 // NR cell bandwidth. With the PCIe SDR50 board, up to 50 MHz is supported. #define NR_BANDWIDTH 40 // NR cell bandwidth. With the PCIe SDR50 board, up to 50 MHz is supported.
// With the PCIe SDR100 board, up to 100 MHz is supported. // With the PCIe SDR100 board, up to 100 MHz is supported.
#define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
{ {
//log_options: "all.level=debug,all.max_size=1", //log_options: "all.level=debug,all.max_size=1",
...@@ -98,6 +99,7 @@ ...@@ -98,6 +99,7 @@
#else #else
band: 7, band: 7,
dl_nr_arfcn: 528000, /* 2640 MHz */ dl_nr_arfcn: 528000, /* 2640 MHz */
ssb_subcarrier_spacing: 15,
#endif #endif
ncell_list: [ ncell_list: [
...@@ -114,8 +116,9 @@ ...@@ -114,8 +116,9 @@
band: 78, band: 78,
dl_nr_arfcn: 640000, /* 3600 MHz */ dl_nr_arfcn: 640000, /* 3600 MHz */
#else #else
band: 5, band: 7,
dl_nr_arfcn: 532000, /* 2660 MHz */ dl_nr_arfcn: 532000, /* 2660 MHz */
ssb_subcarrier_spacing: 15,
#endif #endif
ncell_list: [ ncell_list: [
...@@ -366,6 +369,19 @@ ...@@ -366,6 +369,19 @@
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 2, ul_symbols: 2,
#elif NR_TDD_CONFIG == 4
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
#endif #endif
}, },
}, },
...@@ -391,13 +407,17 @@ ...@@ -391,13 +407,17 @@
prach: { prach: {
#if NR_TDD == 1 #if NR_TDD == 1
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -435,20 +455,8 @@ ...@@ -435,20 +455,8 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if NR_TDD == 1
#if NR_TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif NR_TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif NR_TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
...@@ -683,32 +691,30 @@ ...@@ -683,32 +691,30 @@
freq_hopping: true, freq_hopping: true,
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -723,6 +729,8 @@ ...@@ -723,6 +729,8 @@
srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ],
#elif NR_TDD_CONFIG == 3 #elif NR_TDD_CONFIG == 3
srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ],
#elif NR_TDD_CONFIG == 4
srs_symbols: [ 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 ],
#endif #endif
srs_resource: [ srs_resource: [
{ {
...@@ -750,9 +758,8 @@ ...@@ -750,9 +758,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-sa-ho.cfg
View file @ 1bd8c3dd
...@@ -3,11 +3,12 @@ ...@@ -3,11 +3,12 @@
* NR SA 2 cells, FDD or TDD, for HO */ * NR SA 2 cells, FDD or TDD, for HO */
#define TDD 0 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 0 // Values: 0 (NR FDD), 1(NR TDD)
#define TDD_CONFIG 2 // Values: 1, 2 or 3 #define NR_TDD_CONFIG 2 // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define N_ANTENNA_UL 1 // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX) #define N_ANTENNA_UL 1 // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX)
#define BANDWIDTH 20 // NR cell bandwidth #define NR_BANDWIDTH 20 // NR cell bandwidth
#define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
{ {
log_options: "all.level=debug,all.max_size=1", log_options: "all.level=debug,all.max_size=1",
...@@ -64,7 +65,7 @@ ...@@ -64,7 +65,7 @@
{cell_id: 2}, {cell_id: 2},
], ],
#if TDD == 1 #if NR_TDD == 1
band: 78, band: 78,
dl_nr_arfcn: 621300, dl_nr_arfcn: 621300,
#else #else
...@@ -80,7 +81,7 @@ ...@@ -80,7 +81,7 @@
{cell_id: 1}, {cell_id: 1},
], ],
#if TDD == 1 #if NR_TDD == 1
band: 78, band: 78,
dl_nr_arfcn: 627300, dl_nr_arfcn: 627300,
#else #else
...@@ -92,34 +93,47 @@ ...@@ -92,34 +93,47 @@
nr_cell_default: { nr_cell_default: {
subcarrier_spacing: 30, /* kHz */ subcarrier_spacing: 30, /* kHz */
bandwidth: BANDWIDTH, /* MHz */ bandwidth: NR_BANDWIDTH, /* MHz */
n_antenna_dl: N_ANTENNA_DL, n_antenna_dl: N_ANTENNA_DL,
n_antenna_ul: N_ANTENNA_UL, n_antenna_ul: N_ANTENNA_UL,
/* force the timing TA offset (optional) */ /* force the timing TA offset (optional) */
// n_timing_advance_offset: 39936, // n_timing_advance_offset: 39936,
#if TDD == 1 #if NR_TDD == 1
tdd_ul_dl_config: { tdd_ul_dl_config: {
pattern1: { pattern1: {
#if TDD_CONFIG == 1 #if NR_TDD_CONFIG == 1
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: /* 6 */ 2, dl_symbols: /* 6 */ 2,
ul_slots: 2, ul_slots: 2,
ul_symbols: 0, ul_symbols: 0,
#elif TDD_CONFIG == 2 #elif NR_TDD_CONFIG == 2
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: 6, dl_symbols: 6,
ul_slots: 2, ul_slots: 2,
ul_symbols: 4, ul_symbols: 4,
#elif TDD_CONFIG == 3 #elif NR_TDD_CONFIG == 3
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 6, dl_slots: 6,
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 0, ul_symbols: 0,
#elif NR_TDD_CONFIG == 4
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
#endif #endif
}, },
}, },
...@@ -173,14 +187,18 @@ ...@@ -173,14 +187,18 @@
//pdsch_harq_ack_max: 2, //pdsch_harq_ack_max: 2,
prach: { prach: {
#if TDD == 1 #if NR_TDD == 1
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -222,19 +240,8 @@ ...@@ -222,19 +240,8 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if TDD == 1
#if TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
...@@ -470,32 +477,30 @@ ...@@ -470,32 +477,30 @@
freq_hopping: true, freq_hopping: true,
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -511,9 +516,8 @@ ...@@ -511,9 +516,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-sa-lte-ho.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* LTE cell + NR SA cell */ * LTE cell + NR SA cell */
#define N_CELL 2 #define N_CELL 2
#define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD) #define TDD 0 // Values: 0 (LTE FDD), 1(LTE TDD)
#define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD)
#define N_RB_DL 100 // Values: 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz) #define N_RB_DL 100 // Values: 25 (5MHz), 50 (10MHz), 75 (15MHz), 100 (20MHz)
#define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2) #define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2)
#define N_ANTENNA_UL 1 // Values: 1, 2 #define N_ANTENNA_UL 1 // Values: 1, 2
#define NR_TDD_CONFIG 2 // Values: 1, 2 or 3 NR TDD Config #define NR_TDD_CONFIG 2 // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define NR_BANDWIDTH 20 // NR cell bandwidth #define NR_BANDWIDTH 20 // NR cell bandwidth
#define EPS_FALLBACK 0 // Values: 0 (disable EPS fallback), 1 (enable EPS fallback) #define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
#define EPS_FALLBACK 0 // Values: 0 (disable EPS fallback), 1 (enable EPS fallback)
/* define to 1 to enable periodic SRS with N_ANTENNA_UL ports. Uplink /* define to 1 to enable periodic SRS with N_ANTENNA_UL ports. Uplink
SU-MIMO is also enabled if N_ANTENNA_UL >= 2. Not all UEs support SU-MIMO is also enabled if N_ANTENNA_UL >= 2. Not all UEs support
...@@ -113,6 +114,9 @@ ...@@ -113,6 +114,9 @@
meas_gap_config: "gp0", meas_gap_config: "gp0",
ho_from_meas: true, ho_from_meas: true,
#if EPS_FALLBACK > 0
eps_fallback_fast_return_preferred_method: "handover",
#endif
} }
], /* cell_list */ ], /* cell_list */
...@@ -126,9 +130,9 @@ ...@@ -126,9 +130,9 @@
rat: "eutra", rat: "eutra",
n_id_cell: 1, n_id_cell: 1,
#if TDD == 1 #if TDD == 1
dl_earfcn: 40620, /* 2593 MHz (band 41) */ dl_earfcn: 40620, /* 2593 MHz (band 41) */
#else #else
dl_earfcn: 300, /* DL center frequency: 2140 MHz (Band 1) */ dl_earfcn: 300, /* DL center frequency: 2140 MHz (Band 1) */
#endif #endif
cell_id: 0x1a2d001, cell_id: 0x1a2d001,
tac: 1, tac: 1,
...@@ -206,6 +210,10 @@ ...@@ -206,6 +210,10 @@
filename: "sib23.asn", filename: "sib23.asn",
si_periodicity: 16, /* frames */ si_periodicity: 16, /* frames */
}, },
/*{
filename: "sib24.asn",
si_periodicity: 16
}*/
], ],
#if N_RB_DL == 6 #if N_RB_DL == 6
...@@ -397,6 +405,19 @@ ...@@ -397,6 +405,19 @@
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 2, ul_symbols: 2,
#elif NR_TDD_CONFIG == 4
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
#endif #endif
}, },
}, },
...@@ -432,17 +453,10 @@ ...@@ -432,17 +453,10 @@
si_periodicity: 16, si_periodicity: 16,
}, },
{ {
filename: "sib3_nr.asn", filename: "sib5_nr.asn",
si_periodicity: 16, si_periodicity: 16,
}, },
{ ],*/
filename: "sib4_nr.asn",
si_periodicity: 32,
},
],
sib9: {
si_periodicity: 32
},*/
si_window_length: 40, si_window_length: 40,
cell_barred: false, cell_barred: false,
...@@ -464,13 +478,17 @@ ...@@ -464,13 +478,17 @@
prach: { prach: {
#if NR_TDD == 1 #if NR_TDD == 1
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -512,20 +530,8 @@ ...@@ -512,20 +530,8 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if NR_TDD == 1
#if NR_TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif NR_TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif NR_TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
...@@ -761,32 +767,30 @@ ...@@ -761,32 +767,30 @@
freq_hopping: true, freq_hopping: true,
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -798,6 +802,8 @@ ...@@ -798,6 +802,8 @@
srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ],
#elif NR_TDD_CONFIG == 3 #elif NR_TDD_CONFIG == 3
srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ],
#elif NR_TDD_CONFIG == 4
srs_symbols: [ 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 ],
#endif #endif
srs_resource: [ srs_resource: [
{ {
...@@ -825,9 +831,8 @@ ...@@ -825,9 +831,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-sa.cfg
View file @ 1bd8c3dd
/* lteenb configuration file version 2021-03-17 /* lteenb configuration file version 2021-09-18
* Copyright (C) 2019-2021 Amarisoft * Copyright (C) 2019-2021 Amarisoft
* NR SA FDD or TDD cell */ * NR SA FDD or TDD cell */
#define TDD 1 // Values: 0 (NR FDD), 1(NR TDD) #define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD)
#define TDD_CONFIG 2 // Values: 1, 2 or 3 #define FR2 0 // Values: 0 (FR1), 1 (FR2)
#define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define NR_TDD_CONFIG 2 // Values: FR1: 1, 2, 3, 4 (compatible with LTE TDD config 2) FR2: 10
#define N_ANTENNA_UL 1 // Values: 1, 2, 4 #define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define BANDWIDTH 20 // NR cell bandwidth #define N_ANTENNA_UL 1 // Values: 1, 2, 4
#define NR_BANDWIDTH 20 // NR cell bandwidth
#define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4
/* define to 1 to enable periodic SRS with N_ANTENNA_UL ports. Uplink /* define to 1 to enable periodic SRS with N_ANTENNA_UL ports. Uplink
SU-MIMO is also enabled if N_ANTENNA_UL >= 2. Not all UEs support SU-MIMO is also enabled if N_ANTENNA_UL >= 2. Not all UEs support
...@@ -57,6 +59,21 @@ ...@@ -57,6 +59,21 @@
nr_support: true, nr_support: true,
rf_ports: [
{
#if FR2
/* an external frequency translator must be used for FR2 */
rf_dl_freq: 3500, /* MHz */
rf_ul_freq: 3500, /* MHz */
/* uncomment to have a higher per-UE bitrate at the expense of
higher gNB real time constraints. The default value is 4
ms. 1 ms gives the maximum per-UE bitrate. */
// rx_to_tx_latency: 1, /* ms */
#endif
},
],
/* list of cells */ /* list of cells */
cell_list: [], cell_list: [],
...@@ -64,53 +81,90 @@ ...@@ -64,53 +81,90 @@
{ {
rf_port: 0, rf_port: 0,
cell_id: 0x01, cell_id: 0x01,
#if TDD == 1 #if NR_TDD == 1
#if FR2
band: 257,
dl_nr_arfcn: 2079167, /* 28000.08 MHz */
subcarrier_spacing: 120, /* kHz */
ssb_pos_bitmap: "0100000000000000000000000000000000000000000000000000000000000000",
#else
band: 78, band: 78,
dl_nr_arfcn: 632628, /* 3489.42 MHz */ dl_nr_arfcn: 632628, /* 3489.42 MHz */
subcarrier_spacing: 30, /* kHz */
ssb_pos_bitmap: "10000000",
#endif
#else #else
band: 7, band: 7,
dl_nr_arfcn: 536020, /* 2680 MHz */ dl_nr_arfcn: 536020, /* 2680 MHz */
ssb_subcarrier_spacing: 15, ssb_subcarrier_spacing: 15,
subcarrier_spacing: 30, /* kHz */
ssb_pos_bitmap: "1000",
#endif #endif
}, },
], /* nr_cell_list */ ], /* nr_cell_list */
nr_cell_default: { nr_cell_default: {
subcarrier_spacing: 30, /* kHz */ bandwidth: NR_BANDWIDTH, /* MHz */
bandwidth: BANDWIDTH, /* MHz */
n_antenna_dl: N_ANTENNA_DL, n_antenna_dl: N_ANTENNA_DL,
n_antenna_ul: N_ANTENNA_UL, n_antenna_ul: N_ANTENNA_UL,
/* force the timing TA offset (optional) */ /* force the timing TA offset (optional) */
// n_timing_advance_offset: 39936, // n_timing_advance_offset: 39936,
/* subframe offset to align with the LTE TDD pattern (optional) */
#if TDD == 1 // subframe_offset: 2,
#if NR_TDD == 1
tdd_ul_dl_config: { tdd_ul_dl_config: {
#if NR_TDD_CONFIG == 1
pattern1: { pattern1: {
#if TDD_CONFIG == 1
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: /* 6 */ 2, dl_symbols: /* 6 */ 2,
ul_slots: 2, ul_slots: 2,
ul_symbols: 2, ul_symbols: 2,
#elif TDD_CONFIG == 2 },
#elif NR_TDD_CONFIG == 2
pattern1: {
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: 6, dl_symbols: 6,
ul_slots: 2, ul_slots: 2,
ul_symbols: 4, ul_symbols: 4,
#elif TDD_CONFIG == 3 },
#elif NR_TDD_CONFIG == 3
pattern1: {
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 6, dl_slots: 6,
dl_symbols: 2, dl_symbols: 2,
ul_slots: 3, ul_slots: 3,
ul_symbols: 2, ul_symbols: 2,
#endif
}, },
#elif NR_TDD_CONFIG == 4
pattern1: {
period: 3, /* in ms */
dl_slots: 3,
dl_symbols: 6,
ul_symbols: 4,
ul_slots: 2,
},
pattern2: {
period: 2, /* in ms */
dl_slots: 4,
dl_symbols: 0,
ul_symbols: 0,
ul_slots: 0,
},
#elif NR_TDD_CONFIG == 10
/* only for FR2 */
pattern1: {
period: 0.625, /* in ms */
dl_slots: 3,
dl_symbols: 10,
ul_slots: 1,
ul_symbols: 2,
},
#endif
}, },
ssb_pos_bitmap: "10000000",
#else
ssb_pos_bitmap: "1000",
#endif #endif
ssb_period: 20, /* in ms */ ssb_period: 20, /* in ms */
n_id_cell: 500, n_id_cell: 500,
...@@ -171,19 +225,32 @@ ...@@ -171,19 +225,32 @@
//pdsch_harq_ack_max: 2, //pdsch_harq_ack_max: 2,
prach: { prach: {
#if TDD == 1 #if NR_TDD == 1
#if FR2
prach_config_index: 149, /* format C0, every 4 frames */
msg1_subcarrier_spacing: 120, /* kHz */
#else
#if NR_TDD_CONFIG == 4
prach_config_index: 156, /* format B4, subframe 2 */
#else
prach_config_index: 160, /* format B4, subframe 9 */ prach_config_index: 160, /* format B4, subframe 9 */
#endif
msg1_subcarrier_spacing: 30, /* kHz */ msg1_subcarrier_spacing: 30, /* kHz */
#endif
#else #else
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, /* in dBm */ preamble_received_target_power: -110, /* in dBm */
preamble_trans_max: 7, preamble_trans_max: 7,
power_ramping_step: 4, /* in dB */ power_ramping_step: 4, /* in dB */
#if FR2
ra_response_window: 40, /* in slots */
#else
ra_response_window: 20, /* in slots */ ra_response_window: 20, /* in slots */
#endif
restricted_set_config: "unrestricted_set", restricted_set_config: "unrestricted_set",
ra_contention_resolution_timer: 64, /* in ms */ ra_contention_resolution_timer: 64, /* in ms */
ssb_per_prach_occasion: 1, ssb_per_prach_occasion: 1,
...@@ -191,14 +258,12 @@ ...@@ -191,14 +258,12 @@
}, },
pdcch: { pdcch: {
n_rb_coreset0: 48,
n_symb_coreset0: 1,
search_space0_index: 0, search_space0_index: 0,
dedicated_coreset: { dedicated_coreset: {
rb_start: -1, /* -1 to have the maximum bandwidth */ rb_start: -1, /* -1 to have the maximum bandwidth */
l_crb: -1, /* -1 means all the bandwidth */ l_crb: -1, /* -1 means all the bandwidth */
duration: 1, duration: 0, /* 0 means to automatically set it from the coreset bandwidth */
precoder_granularity: "sameAsREG_bundle", precoder_granularity: "sameAsREG_bundle",
}, },
...@@ -220,21 +285,9 @@ ...@@ -220,21 +285,9 @@
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
k0: 0, /* delay in slots from DCI to PDSCH */ /* k0 delay in slots from DCI to PDSCH: automatic setting */
/* delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
#if TDD == 1
#if TDD_CONFIG == 1
k1: [ 8, 7, 7, 6, 5, 4, 12 /* , 11 */ ],
#elif TDD_CONFIG == 2
k1: [ 8, 7, 7, 6, 5, 4, 12, 11 ],
#elif TDD_CONFIG == 3
k1: [ 7, 6, 6, 5, 5, 4 ],
#endif
#else
k1: 4,
#endif
mcs_table: "qam256", mcs_table: "qam256",
rar_mcs: 2, rar_mcs: 2,
si_mcs: 6, si_mcs: 6,
/* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed /* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed
...@@ -279,7 +332,9 @@ ...@@ -279,7 +332,9 @@
offset: 1, /* != 0 to avoid collision with SSB */ offset: 1, /* != 0 to avoid collision with SSB */
qcl_info_periodic_csi_rs: 0, qcl_info_periodic_csi_rs: 0,
}, },
#define USE_TRS #if FR2 == 0
#define USE_TRS
#endif
#ifdef USE_TRS #ifdef USE_TRS
/* TRS : period of 40 ms, slots 1 & 2, symbols 4 and 8 */ /* TRS : period of 40 ms, slots 1 & 2, symbols 4 and 8 */
{ {
...@@ -466,34 +521,35 @@ ...@@ -466,34 +521,35 @@
n_cs: 3, n_cs: 3,
n_occ: 3, n_occ: 3,
freq_hopping: true, freq_hopping: true,
#if USE_SRS && NR_TDD == 0
n_symb: 13,
#endif
}, },
#endif #endif
#if 1 #if NR_LONG_PUCCH_FORMAT == 2
pucch2: { pucch2: {
n_symb: 2, n_symb: 2,
n_prb: 1, n_prb: 1,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: false,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 3
#if 0
pucch3: { pucch3: {
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
n_prb: 1, n_prb: 1,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #elif NR_LONG_PUCCH_FORMAT == 4
#if 0
pucch4: { pucch4: {
occ_len: 4, occ_len: 4,
bpsk: false, bpsk: false,
additional_dmrs: false, additional_dmrs: false,
freq_hopping: true, freq_hopping: true,
simultaneous_harq_ack_csi: false, simultaneous_harq_ack_csi: true,
max_code_rate: 0.25, max_code_rate: 0.25,
}, },
#endif #endif
...@@ -501,10 +557,18 @@ ...@@ -501,10 +557,18 @@
#if USE_SRS #if USE_SRS
srs: { srs: {
#if TDD_CONFIG == 1 || TDD_CONFIG == 2 #if NR_TDD
#if NR_TDD_CONFIG == 1 || NR_TDD_CONFIG == 2
srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ],
#elif TDD_CONFIG == 3 #elif NR_TDD_CONFIG == 3
srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ], srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ],
#elif NR_TDD_CONFIG == 4
srs_symbols: [ 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 ],
#elif NR_TDD_CONFIG == 10
srs_symbols: [ 0, 0, 0, 2, 0 ],
#endif
#else
srs_symbols: [ 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 ],
#endif #endif
srs_resource: [ srs_resource: [
{ {
...@@ -532,9 +596,8 @@ ...@@ -532,9 +596,8 @@
mcs_table: "qam256", /* without transform precoding */ mcs_table: "qam256", /* without transform precoding */
mcs_table_tp: "qam256", /* with transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */
ldpc_max_its: 5, ldpc_max_its: 5,
k2: 4, /* delay in slots from DCI to PUSCH */ /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
p0_nominal_with_grant: -76, p0_nominal_with_grant: -76,
msg3_k2: 7,
msg3_mcs: 4, msg3_mcs: 4,
msg3_delta_power: 0, /* in dB */ msg3_delta_power: 0, /* in dB */
beta_offset_ack_index: 9, beta_offset_ack_index: 9,
......
enb/gnb-tm-pdsch.cfg
View file @ 1bd8c3dd
/* gNodeB test mode for PDSCH or PUSCH */ /* gNodeB test mode for PDSCH */
{ {
// log_options: "all.level=debug,all.max_size=0", // log_options: "all.level=debug,all.max_size=0",
log_options: "all.level=error,all.max_size=0,nas.level=debug,nas.max_size=1,s1ap.level=debug,rrc.level=debug,rrc.max_size=1", log_options: "all.level=error,all.max_size=0,nas.level=debug,nas.max_size=1,s1ap.level=debug,rrc.level=debug,rrc.max_size=1",
log_filename: "/tmp/enb0.log", log_filename: "/tmp/gnb0.log",
#define FR2 0 /* 0=FR1, 1=FR2 */
#if FR2
/* FR2 parameters */
#define TDD 1
#define BANDWIDTH 50 /* MHz */
#define SCS 120 /* kHz */
#else
/* FR1 parameters */
#define TDD 0 #define TDD 0
#define FR2 0 #define BANDWIDTH 20 /* MHz */
/* test PUSCH (1) or of PDSCH (0) */ #define SCS 30 /* kHz */
#define TM_PUSCH 0 #endif
/* the signal is replicated on all the TX antennas */
#define N_ANTENNA_DL 1
/* Test models from TS 38.141-1 section 4.9.2.2 */
#define TEST_MODEL "UE-SIM"
//#define TEST_MODEL "FR1-TM1.1"
//#define TEST_MODEL "FR1-TM1.2"
//#define TEST_MODEL "FR1-TM2"
//#define TEST_MODEL "FR1-TM2a"
//#define TEST_MODEL "FR1-TM3.1"
//#define TEST_MODEL "FR1-TM3.1a"
//#define TEST_MODEL "FR1-TM3.2"
//#define TEST_MODEL "FR1-TM3.3"
/* RF driver configuration */
#if 1 #if TEST_MODEL == "UE-SIM"
#define SSB_ENABLED 1
#else
#define SSB_ENABLED 0 /* no SSB is generated */
#endif
/* RF driver configuration */
rf_driver: { rf_driver: {
name: "sdr", name: "sdr",
...@@ -22,20 +51,25 @@ ...@@ -22,20 +51,25 @@
}, },
tx_gain: 90.0, /* TX gain (in dB) */ tx_gain: 90.0, /* TX gain (in dB) */
rx_gain: 20.0, /* RX gain (in dB) */ rx_gain: 20.0, /* RX gain (in dB) */
#else
include "rf_driver/1chan.cfg",
#endif
// rx_gain: 30.0, /* RX gain (in dB) -> 10 dB for PHR limit with 30 dB attenuator */
#if FR2
rf_ports: [ rf_ports: [
{ {
#if FR2
/* an external frequency translator must be used */ /* an external frequency translator must be used */
rf_dl_freq: 3500, rf_dl_freq: 3500,
rf_ul_freq: 3500, rf_ul_freq: 3500,
#endif
#if N_ANTENNA_DL >= 2
/* use the channel simulator to replicate the signal on all the
TX antennas */
n_antenna_dl: N_ANTENNA_DL,
channel_dl: {
type: "awgn",
noise_level: -200, /* no noise by default */
},
#endif
} }
], ],
#endif
/* address of MME for S1AP connection. Must be modified if the MME /* address of MME for S1AP connection. Must be modified if the MME
runs on a different host. */ runs on a different host. */
...@@ -62,30 +96,68 @@ ...@@ -62,30 +96,68 @@
band: 257, band: 257,
dl_nr_arfcn: 2079167, /* 28000.08 MHz */ dl_nr_arfcn: 2079167, /* 28000.08 MHz */
ssb_nr_arfcn: 2079167, ssb_nr_arfcn: 2079167,
subcarrier_spacing: 120, /* kHz */ ssb_subcarrier_spacing: 120, /* kHz */
bandwidth: 50, /* MHz */ #if SSB_ENABLED
ssb_pos_bitmap: "0100000000000000000000000000000000000000000000000000000000000000",
#else
ssb_pos_bitmap: "0000000000000000000000000000000000000000000000000000000000000000",
#endif
#else #else
band: 78, band: 78,
dl_nr_arfcn: 633332, /* 3499.98 MHz */ dl_nr_arfcn: 633332, /* 3499.98 MHz */
ssb_nr_arfcn: 633332, ssb_nr_arfcn: 633332,
subcarrier_spacing: 30, /* kHz */ ssb_subcarrier_spacing: 30, /* kHz */
bandwidth: 20, /* MHz */ #if SSB_ENABLED
ssb_pos_bitmap: "10000000",
#else
ssb_pos_bitmap: "00000000",
#endif
#endif #endif
#else #else
band: 2, band: 2,
dl_nr_arfcn: 396000, /* 1980 MHz */ dl_nr_arfcn: 396000, /* 1980 MHz */
ssb_nr_arfcn: 396000, ssb_nr_arfcn: 396000,
ssb_subcarrier_spacing: 15, /* kHz */ ssb_subcarrier_spacing: 15, /* kHz */
subcarrier_spacing: 30, /* kHz */ #if SSB_ENABLED
bandwidth: 20, /* MHz */ ssb_pos_bitmap: "1000",
#else
ssb_pos_bitmap: "0000",
#endif
#endif #endif
no_ssb_allowed: true,
ssb_period: 10, /* in ms */
subcarrier_spacing: SCS, /* kHz */
bandwidth: BANDWIDTH, /* MHz */
n_antenna_dl: 1, /* 1-8 */ n_antenna_dl: 1, /* 1-8 */
n_antenna_ul: 1, /* 1-8 */ n_antenna_ul: 1, /* 1-8 */
n_id_cell: 500, n_id_cell: 500,
#if TDD #if TDD
#if FR2 #if FR2
#if SCS == 60
tdd_ul_dl_config: {
pattern1: {
period: 1.25, /* in ms */
dl_slots: 3,
dl_symbols: 10,
ul_slots: 1,
ul_symbols: 2,
},
},
#elif SCS == 120
#if 0
tdd_ul_dl_config: {
pattern1: {
period: 1.25, /* in ms */
dl_slots: 7,
dl_symbols: 6,
ul_slots: 2,
ul_symbols: 4,
},
},
#else
/* alternate 120 kHz TDD configuration */
tdd_ul_dl_config: { tdd_ul_dl_config: {
pattern1: { pattern1: {
period: 0.625, /* in ms */ period: 0.625, /* in ms */
...@@ -95,23 +167,42 @@ ...@@ -95,23 +167,42 @@
ul_symbols: 2, ul_symbols: 2,
}, },
}, },
ssb_pos_bitmap: "0100000000000000000000000000000000000000000000000000000000000000", #endif
#endif /* SCS */
#else #else
#if SCS == 15
tdd_ul_dl_config: {
pattern1: {
period: 5, /* in ms */
dl_slots: 3,
dl_symbols: 10,
ul_slots: 1,
ul_symbols: 2,
},
},
#elif SCS == 30
tdd_ul_dl_config: { tdd_ul_dl_config: {
pattern1: { pattern1: {
period: 5, /* in ms */ period: 5, /* in ms */
dl_slots: 7, dl_slots: 7,
dl_symbols: 6, dl_symbols: 6,
ul_slots: 2, ul_slots: 2,
ul_symbols: 0, ul_symbols: 4,
}, },
}, },
ssb_pos_bitmap: "10000000", #elif SCS == 60
#endif tdd_ul_dl_config: {
#else pattern1: {
ssb_pos_bitmap: "1000", period: 5, /* in ms */
#endif dl_slots: 14,
ssb_period: 10, /* in ms */ dl_symbols: 12,
ul_slots: 4,
ul_symbols: 8,
},
},
#endif /* SCS */
#endif /* !FR2 */
#endif /* TDD */
p_max: 10, /* dBm */ p_max: 10, /* dBm */
...@@ -133,7 +224,7 @@ ...@@ -133,7 +224,7 @@
prach_config_index: 16, /* subframe 1 every frame */ prach_config_index: 16, /* subframe 1 every frame */
#endif #endif
msg1_fdm: 1, msg1_fdm: 1,
msg1_frequency_start: 0, msg1_frequency_start: -1,
zero_correlation_zone_config: 15, zero_correlation_zone_config: 15,
preamble_received_target_power: -110, preamble_received_target_power: -110,
preamble_trans_max: 7, preamble_trans_max: 7,
...@@ -150,25 +241,33 @@ ...@@ -150,25 +241,33 @@
}, },
pdcch: { pdcch: {
rb_start: -1, common_coreset: {
l_crb: -1, /* -1 means all the bandwidth */ rb_start: 0,
duration: 1, l_crb: 6,
#if TEST_MODEL == "UE-SIM"
duration: 1,
#else
duration: 2,
#endif
precoder_granularity: "sameAsREG_bundle",
},
css: { css: {
n_candidates: [ 0, 4, 2, 1, 0 ], n_candidates: [ 1, 0, 0, 0, 0 ],
}, },
rar_al_index: 2, rar_al_index: 0,
uss: { uss: {
n_candidates: [ 0, 2, 1, 0, 0 ], n_candidates: [ 1, 0, 0, 0, 0 ],
dci_0_1_and_1_1: true, dci_0_1_and_1_1: true,
#if TEST_MODEL != "UE-SIM"
force_cce0: true, /* force PDCCH in CCE 0 */
#endif
}, },
al_index: 1, al_index: 0,
}, },
pdsch: { pdsch: {
mapping_type: "typeA", mapping_type: "typeA",
start_symb: 1,
n_symb: 13,
dmrs_add_pos: 1, dmrs_add_pos: 1,
dmrs_type: 1, dmrs_type: 1,
dmrs_max_len: 1, dmrs_max_len: 1,
...@@ -182,18 +281,50 @@ ...@@ -182,18 +281,50 @@
#endif #endif
#else #else
k1: 4, k1: 4,
#endif #endif /* TDD */
/* hardcoded scheduling parameters */ /* hardcoded scheduling parameters */
mcs: 28, #if TEST_MODEL == "UE-SIM"
mcs: 28, /* 256QAM */
#elif TEST_MODEL == "FR1-TM1.1"
mcs: 3, /* QPSK */
#elif TEST_MODEL == "FR1-TM1.2"
mcs: 3, /* QPSK */
#elif TEST_MODEL == "FR1-TM2"
mcs: 14, /* 64QAM */
#elif TEST_MODEL == "FR1-TM2a"
mcs: 23, /* 256QAM */
#elif TEST_MODEL == "FR1-TM3.1"
mcs: 14, /* 64QAM */
#elif TEST_MODEL == "FR1-TM3.1a"
mcs: 23, /* 256QAM */
#elif TEST_MODEL == "FR1-TM3.2"
mcs: 3, /* QPSK */
#elif TEST_MODEL == "FR1-TM3.3"
mcs: 3, /* QPSK */
#else
#error unsupported test model
#endif
rar_mcs: 2, rar_mcs: 2,
fer: 0, fer: 0,
fixed_rb_alloc: true, fixed_rb_alloc: true,
#if TEST_MODEL == "UE-SIM"
rb_start: 0, rb_start: 0,
#if FR2 #if FR2
l_crb: 32, l_crb: 32,
#else #else
l_crb: 51, l_crb: 51,
#endif #endif /* FR2 */
#elif TEST_MODEL == "FR1-TM2" || TEST_MODEL == "FR1-TM2a"
/* Note: adjust according to the bandwidth and SCS (period = 10 ms) */
rb_start: [ 0, 25, 50, 0, 25, 50, 0, 25, 50,
0, 25, 50, 0, 25, 50, 0, 25, 50,
0, 25 ],
l_crb: 1,
#else /* other test models */
rb_start: 0,
l_crb: 3,
#endif /* TEST_MODEL */
}, },
pucch: { pucch: {
...@@ -253,17 +384,47 @@ ...@@ -253,17 +384,47 @@
phr_tx_power_factor_change: "dB3" phr_tx_power_factor_change: "dB3"
}, },
test_mode: { /* additional PDSCH with RNTI=0 and optionally RNTI=1 for boosted PRBS */
#if TM_PUSCH #if TEST_MODEL != "UE-SIM" && TEST_MODEL != "FR1-TM2" && TEST_MODEL != "FR1-TM2a"
type: "pusch", tm_pdsch: {
rnti: 0x100, rb_start: 3,
#if TEST_MODEL == "FR1-TM1.1"
mcs: 3, /* QPSK */
#elif TEST_MODEL == "FR1-TM1.2"
mcs: 3, /* QPSK */
boosted_ratio: 0.4,
boosted_power: 3, /* dB */
deboosted_mcs: 3, /* QPSK */
#elif TEST_MODEL == "FR1-TM3.1"
mcs: 14, /* 64QAM */
#elif TEST_MODEL == "FR1-TM3.1a"
mcs: 23, /* 256QAM */
#elif TEST_MODEL == "FR1-TM3.2"
mcs: 7, /* 16QAM */
boosted_ratio: 0.6,
boosted_power: -3, /* dB */
deboosted_mcs: 3, /* QPSK */
#elif TEST_MODEL == "FR1-TM3.3"
mcs: 3, /* QPSK */
boosted_ratio: 0.5,
boosted_power: -6, /* dB */
deboosted_mcs: 3, /* QPSK */
#else #else
#error unsupported test model
#endif
},
#endif /* !UE-SIM */
test_mode: {
type: "pdsch", type: "pdsch",
rnti: 0x100,
random_data: false, /* if true, send random data instead of zeros */ random_data: false, /* if true, send random data instead of zeros */
#if FR2 #if FR2
pdsch_harq_ack_disable: true, /* needed to use all DL slots */ pdsch_harq_ack_disable: true, /* needed to use all DL slots */
#endif #endif
#if TEST_MODEL == "UE-SIM"
rnti: 0x100,
#else
rnti: 0x2,
#endif #endif
}, },
......
enb/sdr/1chan.cfg
View file @ 1bd8c3dd
/* Parameters for SDR device version 2021-03-17 /* Parameters for SDR device version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
rf_driver: { rf_driver: {
......
enb/sdr/2cc-mimo.cfg
View file @ 1bd8c3dd
/* Parameters for SDR device version 2021-03-17 /* Parameters for SDR device version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
rf_driver: { rf_driver: {
......
enb/sdr/3cc-mimo.cfg
View file @ 1bd8c3dd
/* Parameters for SDR device version 2021-03-17 /* Parameters for SDR device version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
rf_driver: { rf_driver: {
......
enb/sdr/luna-cfg.sh 0 → 100755
View file @ 1bd8c3dd
#!/bin/bash
# Copyright (C) 2021 Amarisoft
# Luna configurator wrapper version 2021-09-18
set -e
# Default params
# Override them in enb configuration file, rf_driver/config_script_param section
OUT_FREQ="28000"
LUNA_DEV="/dev/ttyACM0"
SDR_NUM="0"
PARAMS="$1"
SDR_DEV="$2"
IN_FREQ="$3"
IFS=';' read -ra LIST <<< "$PARAMS "
for l in $LIST ; do
for p in $l ; do
eval "$p"
done
if [ "$SDR_DEV" = "/dev/sdr${SDR_NUM}" ] ; then
LO_FREQ=$(( $OUT_FREQ - ($IN_FREQ / 1000000) ))
echo "Configure LUNA for device $SDR_DEV, LO=${LO_FREQ}MHz"
$(dirname $0)/luna-cfg $LUNA_DEV $LO_FREQ
fi
done
exit 0
enb/sib24.asn
View file @ 1bd8c3dd
...@@ -8,9 +8,10 @@ ...@@ -8,9 +8,10 @@
{ {
carrierFreq-r15 632544, carrierFreq-r15 632544,
subcarrierSpacingSSB-r15 kHz30, subcarrierSpacingSSB-r15 kHz30,
cellReselectionPriority-r15 7,
threshX-High-r15 0, threshX-High-r15 0,
threshX-Low-r15 0, threshX-Low-r15 0,
q-RxLevMin-r15 -70, q-RxLevMin-r15 -40,
p-MaxNR-r15 10, p-MaxNR-r15 10,
deriveSSB-IndexFromCell-r15 TRUE deriveSSB-IndexFromCell-r15 TRUE
} }
......
enb/sib2_nr.asn
View file @ 1bd8c3dd
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
}, },
cellReselectionServingFreqInfo { cellReselectionServingFreqInfo {
threshServingLowP 0, threshServingLowP 0,
cellReselectionPriority 4 cellReselectionPriority 6
}, },
intraFreqCellReselectionInfo { intraFreqCellReselectionInfo {
q-RxLevMin -70, q-RxLevMin -70,
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
periodicityAndOffset sf20: 0, periodicityAndOffset sf20: 0,
duration sf1 duration sf1
}, },
ssb-ToMeasure shortBitmap: '1000'B, ssb-ToMeasure mediumBitmap: '10000000'B,
deriveSSB-IndexFromCell TRUE deriveSSB-IndexFromCell TRUE
} }
} }
......
enb/sib5_nr.asn
View file @ 1bd8c3dd
...@@ -9,9 +9,10 @@ ...@@ -9,9 +9,10 @@
carrierFreq 300, carrierFreq 300,
allowedMeasBandwidth mbw100, allowedMeasBandwidth mbw100,
presenceAntennaPort1 TRUE, presenceAntennaPort1 TRUE,
cellReselectionPriority 7,
threshX-High 0, threshX-High 0,
threshX-Low 0, threshX-Low 0,
q-RxLevMin -70, q-RxLevMin -40,
q-QualMin -34, q-QualMin -34,
p-MaxEUTRA 10 p-MaxEUTRA 10
} }
......
mme/epdg.pem 0 → 100644
View file @ 1bd8c3dd
-----BEGIN CERTIFICATE-----
MIIDcTCCAlmgAwIBAgIUPtvvnOaxFyZ16srNuTJAV4eY0pIwDQYJKoZIhvcNAQEL
BQAwVTELMAkGA1UEBhMCRlIxFzAVBgNVBAgMDkhhdXRzLWRlLVNlaW5lMRkwFwYD
VQQHDBBMZXZhbGxvaXMtUGVycmV0MRIwEAYDVQQKDAlBbWFyaXNvZnQwHhcNMjEw
MjE0MTQzNzEwWhcNMjIwMjE0MTQzNzEwWjBVMQswCQYDVQQGEwJGUjEXMBUGA1UE
CAwOSGF1dHMtZGUtU2VpbmUxGTAXBgNVBAcMEExldmFsbG9pcy1QZXJyZXQxEjAQ
BgNVBAoMCUFtYXJpc29mdDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEB
AKESvClBnBauDkrTkQucrshP9m07ZHN1A9DawFXtIUFJj8Ot3Dr2xjCq2UXD5zYQ
4g64BBAUVYsXT+Bw9vFe028qNEGo6frNAqtU9jDw0ctok+oq1YWoNBxwfkYuztmS
dFyOvjpN4QtFSUAFzO9HWUwzG6euzAcrMuBc5td2mca01eukjnpt+SL4hrqi3zSg
FCSNCwd3sdlvo3EM5h0i1amGXfOhUpuDqiSgBbaDGlJITbcbzfsSxo7KEkbK6iln
hWTrwQnAbgonMrxVwzGNFEehBzSlusHXDOGNEV49JUL94feZmE1j/FeArd0HGr7N
jywrxpkWm6x7OUVeviN6AoUCAwEAAaM5MDcwNQYDVR0RBC4wLIIqZXBkZy5lcGMu
bW5jMDAxLm1jYzAwMS5wdWIuM2dwcG5ldHdvcmsub3JnMA0GCSqGSIb3DQEBCwUA
A4IBAQCgHgx4gQWkM+6nYBhaaBhZbAkAfv69PVup9GzPjgc578Ul+N9j1ptWo4vX
jJKIntN0+AFfU5QMxL6aSlqHycWB0PpZl8DjTxiD6NKvMOrW6KIdKfbhVbl6G6xT
Enb6BP4qt+5MTbxxLCpSsxNSOFMt7tsJB6AeJO1L8V8ZePJZQscKpMeGRPgSR2aX
g071rFC0cEAAecLLYPL8SVZKkGxlA0R0gPsO/TTmND5A+kO6PSXs8oSW+MZ8RZl1
utKhcOESPvZLVzCGgWnix3PxrNOhdcW1kaLOhjz6Tr4/EvxR2BBLXTG9jiRt81AU
jfbCmKvSItJEDYZa4+VxPVCOqXNl
-----END CERTIFICATE-----
mme/ims.default.cfg
View file @ 1bd8c3dd
/* lteims configuration file /* lteims configuration file
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
{ {
...@@ -42,16 +42,21 @@ ...@@ -42,16 +42,21 @@
"tel:+666", "tel:+666",
{impu: "tel:404", code: 404}, /* 404 test */ {impu: "tel:404", code: 404}, /* 404 test */
{impu: "urn:service:sos", anonymous: true, authentication: false}, /* Emergency call */ {impu: "urn:service:sos", anonymous: true, authentication: false}, /* Emergency call */
{impu: "urn:service:sos.police", anonymous: true, authentication: false}, /* Emergency call */
], ],
/* Delay */ /* Delay */
//sms_expires: 86400, //sms_expires: 86400,
//binding_expires: 3600, //binding_expires: 3600,
precondition: true, /* true: 3GPP mode, false: IETF mode */ /* on: 3GPP mode allowed
* silent: 3GPP mode forced
* off: IETF mode
*/
precondition: "on",
"100rel": true, "100rel": true,
/* IPSec */ /* IPsec */
ipsec_aalg_list: ["hmac-md5-96", "hmac-sha-1-96"], ipsec_aalg_list: ["hmac-md5-96", "hmac-sha-1-96"],
ipsec_ealg_list: ["null", "aes-cbc", "des-cbc", "des-ede3-cbc"], ipsec_ealg_list: ["null", "aes-cbc", "des-cbc", "des-ede3-cbc"],
......
mme/mme-ifup
View file @ 1bd8c3dd
...@@ -16,7 +16,7 @@ if [ "$type" = "ipv4" ] ; then ...@@ -16,7 +16,7 @@ if [ "$type" = "ipv4" ] ; then
# Configure interface # Configure interface
ifconfig ${ifname} ${ifaddr}/${mask} up ifconfig ${ifname} ${ifaddr}/${mask} up
ipt=$(iptables -S | grep "\-A INPUT \-i ${ifname} \-j ACCEPT") ipt=$(iptables -w 5 -S | grep "\-A INPUT \-i ${ifname} \-j ACCEPT")
if [ "$ipt" = "" ] ; then if [ "$ipt" = "" ] ; then
iptables -I INPUT -i ${ifname} -j ACCEPT iptables -I INPUT -i ${ifname} -j ACCEPT
fi fi
...@@ -36,9 +36,9 @@ else ...@@ -36,9 +36,9 @@ else
# Add route for all prefixes # Add route for all prefixes
ip -6 route add ${addr1}/${mask} dev ${ifname} ip -6 route add ${addr1}/${mask} dev ${ifname}
ipt=$(ip6tables -S | grep "\-A INPUT \-i ${ifname} \-j ACCEPT") ipt=$(ip6tables -w 5 -S | grep "\-A INPUT \-i ${ifname} \-j ACCEPT")
if [ "$ipt" = "" ] ; then if [ "$ipt" = "" ] ; then
ip6tables -I INPUT -i ${ifname} -j ACCEPT ip6tables -w 5 -I INPUT -i ${ifname} -j ACCEPT
fi fi
fi fi
mme/mme-ims.cfg
View file @ 1bd8c3dd
/* ltemme configuration file for ims /* ltemme configuration file for ims
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
{ {
...@@ -33,9 +33,12 @@ ...@@ -33,9 +33,12 @@
mme_group_id: 32769, mme_group_id: 32769,
mme_code: 1, mme_code: 1,
ims_vops: true, /* IMS supported */ ims_vops_eps: true, /* IMS supported */
ims_vops_5gs_3gpp: true, /* IMS supported */
ims_vops_5gs_n3gpp: true, /* IMS supported */
//emc_bs: true, /* emergency calls supported */ //emc_bs: true, /* emergency calls supported */
//emc: 1, /* NR connected to 5GCN emergency calls supported */ //emc: 3, /* NR/E-UTRA connected to 5GCN emergency calls supported */
//emc_n3gpp: true, /* non-3GPP emergency calls supported */
emergency_number_list: [ emergency_number_list: [
/* Category bits: (Table 10.5.135d/3GPP TS 24.008) /* Category bits: (Table 10.5.135d/3GPP TS 24.008)
Bit 1 Police Bit 1 Police
...@@ -85,6 +88,15 @@ ...@@ -85,6 +88,15 @@
} }
],*/ ],*/
/* ePDG configuration */
//epdg: {
// bind_addr: "127.0.1.100:500",
// esp_duration: 900,
// certificate: "epdg.pem",
// /* required for some buggy Mediatek phones */
// //omit_auth_in_first_auth_rsp: true
//},
/* Public Data Networks. The first one is the default. */ /* Public Data Networks. The first one is the default. */
pdn_list: [ pdn_list: [
{ {
......
mme/mme.default.cfg
View file @ 1bd8c3dd
/* ltemme configuration file /* ltemme configuration file
* version 2021-03-17 * version 2021-09-18
* Copyright (C) 2015-2021 Amarisoft * Copyright (C) 2015-2021 Amarisoft
*/ */
{ {
...@@ -33,6 +33,15 @@ ...@@ -33,6 +33,15 @@
mme_group_id: 32769, mme_group_id: 32769,
mme_code: 1, mme_code: 1,
/* ePDG configuration */
//epdg: {
// bind_addr: "127.0.1.100:500",
// esp_duration: 900,
// certificate: "epdg.pem",
// /* required for some buggy Mediatek phones */
// //omit_auth_in_first_auth_rsp: true
//},
/* network name and network short name sent in the EMM information /* network name and network short name sent in the EMM information
message to the UE */ message to the UE */
network_name: "Amarisoft Network", network_name: "Amarisoft Network",
......
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