flexcan.c 58.1 KB
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// SPDX-License-Identifier: GPL-2.0
//
// flexcan.c - FLEXCAN CAN controller driver
//
// Copyright (c) 2005-2006 Varma Electronics Oy
// Copyright (c) 2009 Sascha Hauer, Pengutronix
// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
// Copyright (c) 2014 David Jander, Protonic Holland
//
// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
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#include <linux/bitfield.h>
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#include <linux/can.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
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#include <linux/can/led.h>
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#include <linux/can/rx-offload.h>
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#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#define DRV_NAME			"flexcan"

/* 8 for RX fifo and 2 error handling */
#define FLEXCAN_NAPI_WEIGHT		(8 + 2)

/* FLEXCAN module configuration register (CANMCR) bits */
#define FLEXCAN_MCR_MDIS		BIT(31)
#define FLEXCAN_MCR_FRZ			BIT(30)
#define FLEXCAN_MCR_FEN			BIT(29)
#define FLEXCAN_MCR_HALT		BIT(28)
#define FLEXCAN_MCR_NOT_RDY		BIT(27)
#define FLEXCAN_MCR_WAK_MSK		BIT(26)
#define FLEXCAN_MCR_SOFTRST		BIT(25)
#define FLEXCAN_MCR_FRZ_ACK		BIT(24)
#define FLEXCAN_MCR_SUPV		BIT(23)
#define FLEXCAN_MCR_SLF_WAK		BIT(22)
#define FLEXCAN_MCR_WRN_EN		BIT(21)
#define FLEXCAN_MCR_LPM_ACK		BIT(20)
#define FLEXCAN_MCR_WAK_SRC		BIT(19)
#define FLEXCAN_MCR_DOZE		BIT(18)
#define FLEXCAN_MCR_SRX_DIS		BIT(17)
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#define FLEXCAN_MCR_IRMQ		BIT(16)
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#define FLEXCAN_MCR_LPRIO_EN		BIT(13)
#define FLEXCAN_MCR_AEN			BIT(12)
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#define FLEXCAN_MCR_FDEN		BIT(11)
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/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
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#define FLEXCAN_MCR_MAXMB(x)		((x) & 0x7f)
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#define FLEXCAN_MCR_IDAM_A		(0x0 << 8)
#define FLEXCAN_MCR_IDAM_B		(0x1 << 8)
#define FLEXCAN_MCR_IDAM_C		(0x2 << 8)
#define FLEXCAN_MCR_IDAM_D		(0x3 << 8)
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/* FLEXCAN control register (CANCTRL) bits */
#define FLEXCAN_CTRL_PRESDIV(x)		(((x) & 0xff) << 24)
#define FLEXCAN_CTRL_RJW(x)		(((x) & 0x03) << 22)
#define FLEXCAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
#define FLEXCAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
#define FLEXCAN_CTRL_BOFF_MSK		BIT(15)
#define FLEXCAN_CTRL_ERR_MSK		BIT(14)
#define FLEXCAN_CTRL_CLK_SRC		BIT(13)
#define FLEXCAN_CTRL_LPB		BIT(12)
#define FLEXCAN_CTRL_TWRN_MSK		BIT(11)
#define FLEXCAN_CTRL_RWRN_MSK		BIT(10)
#define FLEXCAN_CTRL_SMP		BIT(7)
#define FLEXCAN_CTRL_BOFF_REC		BIT(6)
#define FLEXCAN_CTRL_TSYN		BIT(5)
#define FLEXCAN_CTRL_LBUF		BIT(4)
#define FLEXCAN_CTRL_LOM		BIT(3)
#define FLEXCAN_CTRL_PROPSEG(x)		((x) & 0x07)
#define FLEXCAN_CTRL_ERR_BUS		(FLEXCAN_CTRL_ERR_MSK)
#define FLEXCAN_CTRL_ERR_STATE \
	(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
	 FLEXCAN_CTRL_BOFF_MSK)
#define FLEXCAN_CTRL_ERR_ALL \
	(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)

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/* FLEXCAN control register 2 (CTRL2) bits */
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#define FLEXCAN_CTRL2_ECRWRE		BIT(29)
#define FLEXCAN_CTRL2_WRMFRZ		BIT(28)
#define FLEXCAN_CTRL2_RFFN(x)		(((x) & 0x0f) << 24)
#define FLEXCAN_CTRL2_TASD(x)		(((x) & 0x1f) << 19)
#define FLEXCAN_CTRL2_MRP		BIT(18)
#define FLEXCAN_CTRL2_RRS		BIT(17)
#define FLEXCAN_CTRL2_EACEN		BIT(16)
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#define FLEXCAN_CTRL2_ISOCANFDEN	BIT(12)
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/* FLEXCAN memory error control register (MECR) bits */
#define FLEXCAN_MECR_ECRWRDIS		BIT(31)
#define FLEXCAN_MECR_HANCEI_MSK		BIT(19)
#define FLEXCAN_MECR_FANCEI_MSK		BIT(18)
#define FLEXCAN_MECR_CEI_MSK		BIT(16)
#define FLEXCAN_MECR_HAERRIE		BIT(15)
#define FLEXCAN_MECR_FAERRIE		BIT(14)
#define FLEXCAN_MECR_EXTERRIE		BIT(13)
#define FLEXCAN_MECR_RERRDIS		BIT(9)
#define FLEXCAN_MECR_ECCDIS		BIT(8)
#define FLEXCAN_MECR_NCEFAFRZ		BIT(7)

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/* FLEXCAN error and status register (ESR) bits */
#define FLEXCAN_ESR_TWRN_INT		BIT(17)
#define FLEXCAN_ESR_RWRN_INT		BIT(16)
#define FLEXCAN_ESR_BIT1_ERR		BIT(15)
#define FLEXCAN_ESR_BIT0_ERR		BIT(14)
#define FLEXCAN_ESR_ACK_ERR		BIT(13)
#define FLEXCAN_ESR_CRC_ERR		BIT(12)
#define FLEXCAN_ESR_FRM_ERR		BIT(11)
#define FLEXCAN_ESR_STF_ERR		BIT(10)
#define FLEXCAN_ESR_TX_WRN		BIT(9)
#define FLEXCAN_ESR_RX_WRN		BIT(8)
#define FLEXCAN_ESR_IDLE		BIT(7)
#define FLEXCAN_ESR_TXRX		BIT(6)
#define FLEXCAN_EST_FLT_CONF_SHIFT	(4)
#define FLEXCAN_ESR_FLT_CONF_MASK	(0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
#define FLEXCAN_ESR_FLT_CONF_ACTIVE	(0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
#define FLEXCAN_ESR_FLT_CONF_PASSIVE	(0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
#define FLEXCAN_ESR_BOFF_INT		BIT(2)
#define FLEXCAN_ESR_ERR_INT		BIT(1)
#define FLEXCAN_ESR_WAK_INT		BIT(0)
#define FLEXCAN_ESR_ERR_BUS \
	(FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
	 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
	 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
#define FLEXCAN_ESR_ERR_STATE \
	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
#define FLEXCAN_ESR_ERR_ALL \
	(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
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#define FLEXCAN_ESR_ALL_INT \
	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
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	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
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/* FLEXCAN Bit Timing register (CBT) bits */
#define FLEXCAN_CBT_BTF			BIT(31)
#define FLEXCAN_CBT_EPRESDIV_MASK	GENMASK(30, 21)
#define FLEXCAN_CBT_ERJW_MASK		GENMASK(20, 16)
#define FLEXCAN_CBT_EPROPSEG_MASK	GENMASK(15, 10)
#define FLEXCAN_CBT_EPSEG1_MASK		GENMASK(9, 5)
#define FLEXCAN_CBT_EPSEG2_MASK		GENMASK(4, 0)

/* FLEXCAN FD control register (FDCTRL) bits */
#define FLEXCAN_FDCTRL_FDRATE		BIT(31)
#define FLEXCAN_FDCTRL_MBDSR1		GENMASK(20, 19)
#define FLEXCAN_FDCTRL_MBDSR0		GENMASK(17, 16)
#define FLEXCAN_FDCTRL_MBDSR_8		0x0
#define FLEXCAN_FDCTRL_MBDSR_12		0x1
#define FLEXCAN_FDCTRL_MBDSR_32		0x2
#define FLEXCAN_FDCTRL_MBDSR_64		0x3

/* FLEXCAN FD Bit Timing register (FDCBT) bits */
#define FLEXCAN_FDCBT_FPRESDIV_MASK	GENMASK(29, 20)
#define FLEXCAN_FDCBT_FRJW_MASK		GENMASK(18, 16)
#define FLEXCAN_FDCBT_FPROPSEG_MASK	GENMASK(14, 10)
#define FLEXCAN_FDCBT_FPSEG1_MASK	GENMASK(7, 5)
#define FLEXCAN_FDCBT_FPSEG2_MASK	GENMASK(2, 0)

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/* FLEXCAN interrupt flag register (IFLAG) bits */
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/* Errata ERR005829 step7: Reserve first valid MB */
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#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO		8
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#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP	0
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#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST	(FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
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#define FLEXCAN_IFLAG_MB(x)		BIT_ULL(x)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
#define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)

/* FLEXCAN message buffers */
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#define FLEXCAN_MB_CODE_MASK		(0xf << 24)
#define FLEXCAN_MB_CODE_RX_BUSY_BIT	(0x1 << 24)
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#define FLEXCAN_MB_CODE_RX_INACTIVE	(0x0 << 24)
#define FLEXCAN_MB_CODE_RX_EMPTY	(0x4 << 24)
#define FLEXCAN_MB_CODE_RX_FULL		(0x2 << 24)
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#define FLEXCAN_MB_CODE_RX_OVERRUN	(0x6 << 24)
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#define FLEXCAN_MB_CODE_RX_RANSWER	(0xa << 24)

#define FLEXCAN_MB_CODE_TX_INACTIVE	(0x8 << 24)
#define FLEXCAN_MB_CODE_TX_ABORT	(0x9 << 24)
#define FLEXCAN_MB_CODE_TX_DATA		(0xc << 24)
#define FLEXCAN_MB_CODE_TX_TANSWER	(0xe << 24)

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#define FLEXCAN_MB_CNT_EDL		BIT(31)
#define FLEXCAN_MB_CNT_BRS		BIT(30)
#define FLEXCAN_MB_CNT_ESI		BIT(29)
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#define FLEXCAN_MB_CNT_SRR		BIT(22)
#define FLEXCAN_MB_CNT_IDE		BIT(21)
#define FLEXCAN_MB_CNT_RTR		BIT(20)
#define FLEXCAN_MB_CNT_LENGTH(x)	(((x) & 0xf) << 16)
#define FLEXCAN_MB_CNT_TIMESTAMP(x)	((x) & 0xffff)

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#define FLEXCAN_TIMEOUT_US		(250)
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/* FLEXCAN hardware feature flags
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 *
 * Below is some version info we got:
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 *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 *                                Filter? connected?  Passive detection  ception in MB
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 *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
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 *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
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 *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
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 *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
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 *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
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 * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
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 *
 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 */
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/* [TR]WRN_INT not connected */
#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
 /* Disable RX FIFO Global mask */
#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
/* Enable EACEN and RRS bit in ctrl2 */
#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3)
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/* Disable non-correctable errors interrupt and freeze mode */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
/* Use timestamp based offloading */
#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
/* No interrupt for error passive */
#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
/* default to BE register access */
#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
/* Setup stop mode to support wakeup */
#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)
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/* Support CAN-FD mode */
#define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
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/* Structure of the message buffer */
struct flexcan_mb {
	u32 can_ctrl;
	u32 can_id;
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	u32 data[];
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};

/* Structure of the hardware registers */
struct flexcan_regs {
	u32 mcr;		/* 0x00 */
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	u32 ctrl;		/* 0x04 - Not affected by Soft Reset */
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	u32 timer;		/* 0x08 */
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	u32 tcr;		/* 0x0c */
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	u32 rxgmask;		/* 0x10 - Not affected by Soft Reset */
	u32 rx14mask;		/* 0x14 - Not affected by Soft Reset */
	u32 rx15mask;		/* 0x18 - Not affected by Soft Reset */
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	u32 ecr;		/* 0x1c */
	u32 esr;		/* 0x20 */
	u32 imask2;		/* 0x24 */
	u32 imask1;		/* 0x28 */
	u32 iflag2;		/* 0x2c */
	u32 iflag1;		/* 0x30 */
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	union {			/* 0x34 */
		u32 gfwr_mx28;	/* MX28, MX53 */
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		u32 ctrl2;	/* MX6, VF610 - Not affected by Soft Reset */
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	};
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	u32 esr2;		/* 0x38 */
	u32 imeur;		/* 0x3c */
	u32 lrfr;		/* 0x40 */
	u32 crcr;		/* 0x44 */
	u32 rxfgmask;		/* 0x48 */
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	u32 rxfir;		/* 0x4c - Not affected by Soft Reset */
	u32 cbt;		/* 0x50 - Not affected by Soft Reset */
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	u32 _reserved2;		/* 0x54 */
	u32 dbg1;		/* 0x58 */
	u32 dbg2;		/* 0x5c */
	u32 _reserved3[8];	/* 0x60 */
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	u8 mb[2][512];		/* 0x80 - Not affected by Soft Reset */
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	/* FIFO-mode:
	 *			MB
	 * 0x080...0x08f	0	RX message buffer
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	 * 0x090...0x0df	1-5	reserved
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	 * 0x0e0...0x0ff	6-7	8 entry ID table
	 *				(mx25, mx28, mx35, mx53)
	 * 0x0e0...0x2df	6-7..37	8..128 entry ID table
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	 *				size conf'ed via ctrl2::RFFN
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	 *				(mx6, vf610)
	 */
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	u32 _reserved4[256];	/* 0x480 */
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	u32 rximr[64];		/* 0x880 - Not affected by Soft Reset */
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	u32 _reserved5[24];	/* 0x980 */
	u32 gfwr_mx6;		/* 0x9e0 - MX6 */
	u32 _reserved6[63];	/* 0x9e4 */
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	u32 mecr;		/* 0xae0 */
	u32 erriar;		/* 0xae4 */
	u32 erridpr;		/* 0xae8 */
	u32 errippr;		/* 0xaec */
	u32 rerrar;		/* 0xaf0 */
	u32 rerrdr;		/* 0xaf4 */
	u32 rerrsynr;		/* 0xaf8 */
	u32 errsr;		/* 0xafc */
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	u32 _reserved7[64];	/* 0xb00 */
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	u32 fdctrl;		/* 0xc00 - Not affected by Soft Reset */
	u32 fdcbt;		/* 0xc04 - Not affected by Soft Reset */
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	u32 fdcrc;		/* 0xc08 */
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};

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static_assert(sizeof(struct flexcan_regs) == 0x4 + 0xc08);

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struct flexcan_devtype_data {
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	u32 quirks;		/* quirks needed for different IP cores */
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};

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struct flexcan_stop_mode {
	struct regmap *gpr;
	u8 req_gpr;
	u8 req_bit;
	u8 ack_gpr;
	u8 ack_bit;
};

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struct flexcan_priv {
	struct can_priv can;
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	struct can_rx_offload offload;
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	struct device *dev;
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	struct flexcan_regs __iomem *regs;
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	struct flexcan_mb __iomem *tx_mb;
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	struct flexcan_mb __iomem *tx_mb_reserved;
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	u8 tx_mb_idx;
	u8 mb_count;
	u8 mb_size;
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	u8 clk_src;	/* clock source of CAN Protocol Engine */

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	u64 rx_mask;
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	u64 tx_mask;
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	u32 reg_ctrl_default;

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	struct clk *clk_ipg;
	struct clk *clk_per;
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	const struct flexcan_devtype_data *devtype_data;
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	struct regulator *reg_xceiver;
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	struct flexcan_stop_mode stm;
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	/* Read and Write APIs */
	u32 (*read)(void __iomem *addr);
	void (*write)(u32 val, void __iomem *addr);
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};

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static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
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	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
		FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
};

static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
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	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
		FLEXCAN_QUIRK_BROKEN_PERR_STATE,
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};
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static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
};
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static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
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	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
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		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
		FLEXCAN_QUIRK_SETUP_STOP_MODE,
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};
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static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
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	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
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		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
		FLEXCAN_QUIRK_BROKEN_PERR_STATE,
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};
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static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
};

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static const struct can_bittiming_const flexcan_bittiming_const = {
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	.name = DRV_NAME,
	.tseg1_min = 4,
	.tseg1_max = 16,
	.tseg2_min = 2,
	.tseg2_max = 8,
	.sjw_max = 4,
	.brp_min = 1,
	.brp_max = 256,
	.brp_inc = 1,
};

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static const struct can_bittiming_const flexcan_fd_bittiming_const = {
	.name = DRV_NAME,
	.tseg1_min = 2,
	.tseg1_max = 96,
	.tseg2_min = 2,
	.tseg2_max = 32,
	.sjw_max = 16,
	.brp_min = 1,
	.brp_max = 1024,
	.brp_inc = 1,
};

static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
	.name = DRV_NAME,
	.tseg1_min = 2,
	.tseg1_max = 39,
	.tseg2_min = 2,
	.tseg2_max = 8,
	.sjw_max = 4,
	.brp_min = 1,
	.brp_max = 1024,
	.brp_inc = 1,
};

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/* FlexCAN module is essentially modelled as a little-endian IP in most
 * SoCs, i.e the registers as well as the message buffer areas are
 * implemented in a little-endian fashion.
 *
 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 * module in a big-endian fashion (i.e the registers as well as the
 * message buffer areas are implemented in a big-endian way).
 *
 * In addition, the FlexCAN module can be found on SoCs having ARM or
 * PPC cores. So, we need to abstract off the register read/write
 * functions, ensuring that these cater to all the combinations of module
 * endianness and underlying CPU endianness.
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 */
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static inline u32 flexcan_read_be(void __iomem *addr)
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{
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	return ioread32be(addr);
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}

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static inline void flexcan_write_be(u32 val, void __iomem *addr)
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{
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	iowrite32be(val, addr);
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}
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static inline u32 flexcan_read_le(void __iomem *addr)
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{
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	return ioread32(addr);
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}

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static inline void flexcan_write_le(u32 val, void __iomem *addr)
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{
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	iowrite32(val, addr);
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}

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static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
						 u8 mb_index)
{
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	u8 bank_size;
	bool bank;

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	if (WARN_ON(mb_index >= priv->mb_count))
		return NULL;

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	bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;

	bank = mb_index >= bank_size;
	if (bank)
		mb_index -= bank_size;

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	return (struct flexcan_mb __iomem *)
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		(&priv->regs->mb[bank][priv->mb_size * mb_index]);
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}

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static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
{
	struct flexcan_regs __iomem *regs = priv->regs;
	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;

	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
		udelay(10);

	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
		return -ETIMEDOUT;

	return 0;
}

static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
{
	struct flexcan_regs __iomem *regs = priv->regs;
	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;

	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
		udelay(10);

	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
		return -ETIMEDOUT;

	return 0;
}

495 496 497 498 499 500 501 502 503 504 505 506 507 508 509
static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
{
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg_mcr;

	reg_mcr = priv->read(&regs->mcr);

	if (enable)
		reg_mcr |= FLEXCAN_MCR_WAK_MSK;
	else
		reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;

	priv->write(reg_mcr, &regs->mcr);
}

510
static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
511 512 513 514 515 516 517 518 519 520 521
{
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg_mcr;

	reg_mcr = priv->read(&regs->mcr);
	reg_mcr |= FLEXCAN_MCR_SLF_WAK;
	priv->write(reg_mcr, &regs->mcr);

	/* enable stop request */
	regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
			   1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
522

523
	return flexcan_low_power_enter_ack(priv);
524 525
}

526
static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
527 528 529 530 531 532 533 534 535 536 537
{
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg_mcr;

	/* remove stop request */
	regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
			   1 << priv->stm.req_bit, 0);

	reg_mcr = priv->read(&regs->mcr);
	reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
	priv->write(reg_mcr, &regs->mcr);
538

539
	return flexcan_low_power_exit_ack(priv);
540 541
}

542 543 544 545 546
static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
{
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);

547
	priv->write(reg_ctrl, &regs->ctrl);
548 549 550 551 552 553 554
}

static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
{
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);

555
	priv->write(reg_ctrl, &regs->ctrl);
556 557
}

558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578
static int flexcan_clks_enable(const struct flexcan_priv *priv)
{
	int err;

	err = clk_prepare_enable(priv->clk_ipg);
	if (err)
		return err;

	err = clk_prepare_enable(priv->clk_per);
	if (err)
		clk_disable_unprepare(priv->clk_ipg);

	return err;
}

static void flexcan_clks_disable(const struct flexcan_priv *priv)
{
	clk_disable_unprepare(priv->clk_per);
	clk_disable_unprepare(priv->clk_ipg);
}

579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594
static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
{
	if (!priv->reg_xceiver)
		return 0;

	return regulator_enable(priv->reg_xceiver);
}

static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
{
	if (!priv->reg_xceiver)
		return 0;

	return regulator_disable(priv->reg_xceiver);
}

595
static int flexcan_chip_enable(struct flexcan_priv *priv)
596
{
597
	struct flexcan_regs __iomem *regs = priv->regs;
598 599
	u32 reg;

600
	reg = priv->read(&regs->mcr);
601
	reg &= ~FLEXCAN_MCR_MDIS;
602
	priv->write(reg, &regs->mcr);
603

604
	return flexcan_low_power_exit_ack(priv);
605 606
}

607
static int flexcan_chip_disable(struct flexcan_priv *priv)
608
{
609
	struct flexcan_regs __iomem *regs = priv->regs;
610 611
	u32 reg;

612
	reg = priv->read(&regs->mcr);
613
	reg |= FLEXCAN_MCR_MDIS;
614
	priv->write(reg, &regs->mcr);
615

616
	return flexcan_low_power_enter_ack(priv);
617 618
}

619 620
static int flexcan_chip_freeze(struct flexcan_priv *priv)
{
621
	struct flexcan_regs __iomem *regs = priv->regs;
622 623 624
	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
	u32 reg;

625
	reg = priv->read(&regs->mcr);
626
	reg |= FLEXCAN_MCR_HALT;
627
	priv->write(reg, &regs->mcr);
628

629
	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
630
		udelay(100);
631

632
	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
633 634 635 636 637 638 639
		return -ETIMEDOUT;

	return 0;
}

static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
{
640
	struct flexcan_regs __iomem *regs = priv->regs;
641 642 643
	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
	u32 reg;

644
	reg = priv->read(&regs->mcr);
645
	reg &= ~FLEXCAN_MCR_HALT;
646
	priv->write(reg, &regs->mcr);
647

648
	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
649
		udelay(10);
650

651
	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
652 653 654 655 656
		return -ETIMEDOUT;

	return 0;
}

657 658
static int flexcan_chip_softreset(struct flexcan_priv *priv)
{
659
	struct flexcan_regs __iomem *regs = priv->regs;
660 661
	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;

662 663
	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
664
		udelay(10);
665

666
	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
667 668 669 670 671
		return -ETIMEDOUT;

	return 0;
}

672 673
static int __flexcan_get_berr_counter(const struct net_device *dev,
				      struct can_berr_counter *bec)
674 675
{
	const struct flexcan_priv *priv = netdev_priv(dev);
676
	struct flexcan_regs __iomem *regs = priv->regs;
677
	u32 reg = priv->read(&regs->ecr);
678 679 680 681 682 683 684

	bec->txerr = (reg >> 0) & 0xff;
	bec->rxerr = (reg >> 8) & 0xff;

	return 0;
}

685 686 687 688 689 690
static int flexcan_get_berr_counter(const struct net_device *dev,
				    struct can_berr_counter *bec)
{
	const struct flexcan_priv *priv = netdev_priv(dev);
	int err;

691 692
	err = pm_runtime_get_sync(priv->dev);
	if (err < 0)
693 694 695 696
		return err;

	err = __flexcan_get_berr_counter(dev, bec);

697
	pm_runtime_put(priv->dev);
698 699 700 701

	return err;
}

702
static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
703 704
{
	const struct flexcan_priv *priv = netdev_priv(dev);
705
	struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
706
	u32 can_id;
707
	u32 data;
708
	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16);
709
	int i;
710 711 712 713 714 715

	if (can_dropped_invalid_skb(dev, skb))
		return NETDEV_TX_OK;

	netif_stop_queue(dev);

716 717
	if (cfd->can_id & CAN_EFF_FLAG) {
		can_id = cfd->can_id & CAN_EFF_MASK;
718 719
		ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
	} else {
720
		can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
721 722
	}

723
	if (cfd->can_id & CAN_RTR_FLAG)
724 725
		ctrl |= FLEXCAN_MB_CNT_RTR;

726
	if (can_is_canfd_skb(skb)) {
727 728
		ctrl |= FLEXCAN_MB_CNT_EDL;

729 730 731 732
		if (cfd->flags & CANFD_BRS)
			ctrl |= FLEXCAN_MB_CNT_BRS;
	}

733 734
	for (i = 0; i < cfd->len; i += sizeof(u32)) {
		data = be32_to_cpup((__be32 *)&cfd->data[i]);
735
		priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
736 737
	}

738 739
	can_put_echo_skb(skb, dev, 0);

740 741
	priv->write(can_id, &priv->tx_mb->can_id);
	priv->write(ctrl, &priv->tx_mb->can_ctrl);
742

743 744 745
	/* Errata ERR005829 step8:
	 * Write twice INACTIVE(0x8) code to first MB.
	 */
746
	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
747
		    &priv->tx_mb_reserved->can_ctrl);
748
	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
749
		    &priv->tx_mb_reserved->can_ctrl);
750

751 752 753
	return NETDEV_TX_OK;
}

754
static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
755 756
{
	struct flexcan_priv *priv = netdev_priv(dev);
757
	struct flexcan_regs __iomem *regs = priv->regs;
758 759
	struct sk_buff *skb;
	struct can_frame *cf;
760
	bool rx_errors = false, tx_errors = false;
761
	u32 timestamp;
762
	int err;
763 764

	timestamp = priv->read(&regs->timer) << 16;
765

766 767
	skb = alloc_can_err_skb(dev, &cf);
	if (unlikely(!skb))
768
		return;
769

770 771 772
	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;

	if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
773
		netdev_dbg(dev, "BIT1_ERR irq\n");
774
		cf->data[2] |= CAN_ERR_PROT_BIT1;
775
		tx_errors = true;
776 777
	}
	if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
778
		netdev_dbg(dev, "BIT0_ERR irq\n");
779
		cf->data[2] |= CAN_ERR_PROT_BIT0;
780
		tx_errors = true;
781 782
	}
	if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
783
		netdev_dbg(dev, "ACK_ERR irq\n");
784
		cf->can_id |= CAN_ERR_ACK;
785
		cf->data[3] = CAN_ERR_PROT_LOC_ACK;
786
		tx_errors = true;
787 788
	}
	if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
789
		netdev_dbg(dev, "CRC_ERR irq\n");
790
		cf->data[2] |= CAN_ERR_PROT_BIT;
791
		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
792
		rx_errors = true;
793 794
	}
	if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
795
		netdev_dbg(dev, "FRM_ERR irq\n");
796
		cf->data[2] |= CAN_ERR_PROT_FORM;
797
		rx_errors = true;
798 799
	}
	if (reg_esr & FLEXCAN_ESR_STF_ERR) {
800
		netdev_dbg(dev, "STF_ERR irq\n");
801
		cf->data[2] |= CAN_ERR_PROT_STUFF;
802
		rx_errors = true;
803 804 805 806 807 808 809 810
	}

	priv->can.can_stats.bus_error++;
	if (rx_errors)
		dev->stats.rx_errors++;
	if (tx_errors)
		dev->stats.tx_errors++;

811 812 813
	err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
	if (err)
		dev->stats.rx_fifo_errors++;
814 815
}

816
static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
817 818
{
	struct flexcan_priv *priv = netdev_priv(dev);
819
	struct flexcan_regs __iomem *regs = priv->regs;
820 821
	struct sk_buff *skb;
	struct can_frame *cf;
822
	enum can_state new_state, rx_state, tx_state;
823
	int flt;
824
	struct can_berr_counter bec;
825
	u32 timestamp;
826
	int err;
827

828 829
	flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
	if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
830
		tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
831
			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
832
		rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
833
			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
834
		new_state = max(tx_state, rx_state);
835
	} else {
836
		__flexcan_get_berr_counter(dev, &bec);
837
		new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
838
			CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
839 840 841
		rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
		tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
	}
842 843 844

	/* state hasn't changed */
	if (likely(new_state == priv->can.state))
845
		return;
846

847 848
	timestamp = priv->read(&regs->timer) << 16;

849 850
	skb = alloc_can_err_skb(dev, &cf);
	if (unlikely(!skb))
851
		return;
852

853 854 855 856 857
	can_change_state(dev, cf, tx_state, rx_state);

	if (unlikely(new_state == CAN_STATE_BUS_OFF))
		can_bus_off(dev);

858 859 860
	err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
	if (err)
		dev->stats.rx_fifo_errors++;
861
}
862

863 864 865 866 867 868 869 870 871 872 873 874
static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
{
	u64 reg = 0;

	if (upper_32_bits(mask))
		reg = (u64)priv->read(addr - 4) << 32;
	if (lower_32_bits(mask))
		reg |= priv->read(addr);

	return reg & mask;
}

875 876 877 878 879 880 881 882
static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
{
	if (upper_32_bits(val))
		priv->write(upper_32_bits(val), addr - 4);
	if (lower_32_bits(val))
		priv->write(lower_32_bits(val), addr);
}

883 884 885 886 887
static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
{
	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
}

888 889 890 891 892
static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
{
	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
}

893 894 895
static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
{
	return container_of(offload, struct flexcan_priv, offload);
896 897
}

898 899 900
static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
					    unsigned int n, u32 *timestamp,
					    bool drop)
901
{
902
	struct flexcan_priv *priv = rx_offload_to_priv(offload);
903
	struct flexcan_regs __iomem *regs = priv->regs;
904
	struct flexcan_mb __iomem *mb;
905
	struct sk_buff *skb;
906
	struct canfd_frame *cfd;
907
	u32 reg_ctrl, reg_id, reg_iflag1;
908 909
	int i;

910 911 912 913 914
	if (unlikely(drop)) {
		skb = ERR_PTR(-ENOBUFS);
		goto mark_as_read;
	}

915
	mb = flexcan_get_mb(priv, n);
916

917 918 919 920
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
		u32 code;

		do {
921
			reg_ctrl = priv->read(&mb->can_ctrl);
922 923 924 925 926 927
		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);

		/* is this MB empty? */
		code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
		if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
		    (code != FLEXCAN_MB_CODE_RX_OVERRUN))
928
			return NULL;
929 930 931 932 933 934 935

		if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
			/* This MB was overrun, we lost data */
			offload->dev->stats.rx_over_errors++;
			offload->dev->stats.rx_errors++;
		}
	} else {
936
		reg_iflag1 = priv->read(&regs->iflag1);
937
		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
938
			return NULL;
939

940
		reg_ctrl = priv->read(&mb->can_ctrl);
941
	}
942

943 944 945 946
	if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
		skb = alloc_canfd_skb(offload->dev, &cfd);
	else
		skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
947
	if (unlikely(!skb)) {
948 949 950 951
		skb = ERR_PTR(-ENOMEM);
		goto mark_as_read;
	}

952 953 954
	/* increase timstamp to full 32 bit */
	*timestamp = reg_ctrl << 16;

955
	reg_id = priv->read(&mb->can_id);
956
	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
957
		cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
958
	else
959
		cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
960

961 962
	if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
		cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
963 964 965

		if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
			cfd->flags |= CANFD_BRS;
966 967 968 969 970 971 972 973 974
	} else {
		cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf);

		if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
			cfd->can_id |= CAN_RTR_FLAG;
	}

	if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
		cfd->flags |= CANFD_ESI;
975

976
	for (i = 0; i < cfd->len; i += sizeof(u32)) {
977
		__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
978
		*(__be32 *)(cfd->data + i) = data;
979
	}
980

981
 mark_as_read:
982 983 984
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
		flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
	else
985
		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
986

987 988 989 990 991 992
	/* Read the Free Running Timer. It is optional but recommended
	 * to unlock Mailbox as soon as possible and make it available
	 * for reception.
	 */
	priv->read(&regs->timer);

993
	return skb;
994 995 996 997 998 999 1000
}

static irqreturn_t flexcan_irq(int irq, void *dev_id)
{
	struct net_device *dev = dev_id;
	struct net_device_stats *stats = &dev->stats;
	struct flexcan_priv *priv = netdev_priv(dev);
1001
	struct flexcan_regs __iomem *regs = priv->regs;
1002
	irqreturn_t handled = IRQ_NONE;
1003 1004
	u64 reg_iflag_tx;
	u32 reg_esr;
1005
	enum can_state last_state = priv->can.state;
1006

1007
	/* reception interrupt */
1008
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1009
		u64 reg_iflag_rx;
1010 1011
		int ret;

1012
		while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1013 1014
			handled = IRQ_HANDLED;
			ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1015
								   reg_iflag_rx);
1016 1017 1018 1019
			if (!ret)
				break;
		}
	} else {
1020 1021 1022
		u32 reg_iflag1;

		reg_iflag1 = priv->read(&regs->iflag1);
1023 1024 1025 1026
		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
			handled = IRQ_HANDLED;
			can_rx_offload_irq_offload_fifo(&priv->offload);
		}
1027

1028 1029 1030
		/* FIFO overflow interrupt */
		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
			handled = IRQ_HANDLED;
1031 1032
			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
				    &regs->iflag1);
1033 1034 1035
			dev->stats.rx_over_errors++;
			dev->stats.rx_errors++;
		}
1036 1037
	}

1038
	reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1039

1040
	/* transmission complete interrupt */
1041
	if (reg_iflag_tx & priv->tx_mask) {
1042
		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1043

1044
		handled = IRQ_HANDLED;
1045 1046
		stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
							       0, reg_ctrl << 16);
1047
		stats->tx_packets++;
1048
		can_led_event(dev, CAN_LED_EVENT_TX);
1049 1050

		/* after sending a RTR frame MB is in RX mode */
1051
		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1052
			    &priv->tx_mb->can_ctrl);
1053
		flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1054 1055 1056
		netif_wake_queue(dev);
	}

1057
	reg_esr = priv->read(&regs->esr);
1058

1059 1060
	/* ACK all bus error, state change and wake IRQ sources */
	if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1061
		handled = IRQ_HANDLED;
1062
		priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1063 1064
	}

1065 1066
	/* state change interrupt or broken error state quirk fix is enabled */
	if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1067
	    (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1068
					   FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1069 1070 1071 1072 1073 1074 1075
		flexcan_irq_state(dev, reg_esr);

	/* bus error IRQ - handle if bus error reporting is activated */
	if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
	    (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
		flexcan_irq_bus_err(dev, reg_esr);

1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113
	/* availability of error interrupt among state transitions in case
	 * bus error reporting is de-activated and
	 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
	 *  +--------------------------------------------------------------+
	 *  | +----------------------------------------------+ [stopped /  |
	 *  | |                                              |  sleeping] -+
	 *  +-+-> active <-> warning <-> passive -> bus off -+
	 *        ___________^^^^^^^^^^^^_______________________________
	 *        disabled(1)  enabled             disabled
	 *
	 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
	 */
	if ((last_state != priv->can.state) &&
	    (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
	    !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
		switch (priv->can.state) {
		case CAN_STATE_ERROR_ACTIVE:
			if (priv->devtype_data->quirks &
			    FLEXCAN_QUIRK_BROKEN_WERR_STATE)
				flexcan_error_irq_enable(priv);
			else
				flexcan_error_irq_disable(priv);
			break;

		case CAN_STATE_ERROR_WARNING:
			flexcan_error_irq_enable(priv);
			break;

		case CAN_STATE_ERROR_PASSIVE:
		case CAN_STATE_BUS_OFF:
			flexcan_error_irq_disable(priv);
			break;

		default:
			break;
		}
	}

1114
	return handled;
1115 1116
}

1117
static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1118 1119 1120
{
	const struct flexcan_priv *priv = netdev_priv(dev);
	const struct can_bittiming *bt = &priv->can.bittiming;
1121
	struct flexcan_regs __iomem *regs = priv->regs;
1122 1123
	u32 reg;

1124
	reg = priv->read(&regs->ctrl);
1125 1126 1127 1128
	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
		 FLEXCAN_CTRL_RJW(0x3) |
		 FLEXCAN_CTRL_PSEG1(0x7) |
		 FLEXCAN_CTRL_PSEG2(0x7) |
1129
		 FLEXCAN_CTRL_PROPSEG(0x7));
1130 1131 1132 1133 1134 1135 1136

	reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
		FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
		FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
		FLEXCAN_CTRL_RJW(bt->sjw - 1) |
		FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);

1137 1138 1139 1140 1141 1142 1143 1144
	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
	priv->write(reg, &regs->ctrl);

	/* print chip status */
	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
}

1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
static void flexcan_set_bittiming_cbt(const struct net_device *dev)
{
	struct flexcan_priv *priv = netdev_priv(dev);
	struct can_bittiming *bt = &priv->can.bittiming;
	struct can_bittiming *dbt = &priv->can.data_bittiming;
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg_cbt, reg_fdctrl;

	/* CBT */
	/* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
	 * long. The can_calc_bittiming() tries to divide the tseg1
	 * equally between phase_seg1 and prop_seg, which may not fit
	 * in CBT register. Therefore, if phase_seg1 is more than
	 * possible value, increase prop_seg and decrease phase_seg1.
	 */
	if (bt->phase_seg1 > 0x20) {
		bt->prop_seg += (bt->phase_seg1 - 0x20);
		bt->phase_seg1 = 0x20;
	}

	reg_cbt = FLEXCAN_CBT_BTF |
		FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
		FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
		FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
		FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
		FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);

	netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
	priv->write(reg_cbt, &regs->cbt);

	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1176
		u32 reg_fdcbt, reg_ctrl2;
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194

		if (bt->brp != dbt->brp)
			netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
				    dbt->brp, bt->brp);

		/* FDCBT */
		/* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
		 * 5 bit long. The can_calc_bittiming tries to divide
		 * the tseg1 equally between phase_seg1 and prop_seg,
		 * which may not fit in FDCBT register. Therefore, if
		 * phase_seg1 is more than possible value, increase
		 * prop_seg and decrease phase_seg1
		 */
		if (dbt->phase_seg1 > 0x8) {
			dbt->prop_seg += (dbt->phase_seg1 - 0x8);
			dbt->phase_seg1 = 0x8;
		}

1195 1196 1197 1198 1199 1200 1201 1202
		reg_fdcbt = priv->read(&regs->fdcbt);
		reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
			       FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
			       FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));

		reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1203 1204 1205 1206 1207 1208 1209
			FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
			FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
			FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
			FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);

		netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
		priv->write(reg_fdcbt, &regs->fdcbt);
1210 1211 1212 1213 1214 1215 1216 1217 1218

		/* CTRL2 */
		reg_ctrl2 = priv->read(&regs->ctrl2);
		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
		if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;

		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
		priv->write(reg_ctrl2, &regs->ctrl2);
1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230
	}

	/* FDCTRL */
	reg_fdctrl = priv->read(&regs->fdctrl);
	reg_fdctrl &= ~FLEXCAN_FDCTRL_FDRATE;

	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
		reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;

	netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
	priv->write(reg_fdctrl, &regs->fdctrl);

1231
	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1232 1233
		   __func__,
		   priv->read(&regs->mcr), priv->read(&regs->ctrl),
1234 1235
		   priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
		   priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1236 1237
}

1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
static void flexcan_set_bittiming(struct net_device *dev)
{
	const struct flexcan_priv *priv = netdev_priv(dev);
	struct flexcan_regs __iomem *regs = priv->regs;
	u32 reg;

	reg = priv->read(&regs->ctrl);
	reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
		 FLEXCAN_CTRL_LOM);

1248 1249 1250 1251 1252 1253 1254
	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
		reg |= FLEXCAN_CTRL_LPB;
	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
		reg |= FLEXCAN_CTRL_LOM;
	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
		reg |= FLEXCAN_CTRL_SMP;

1255
	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1256
	priv->write(reg, &regs->ctrl);
1257

1258 1259 1260 1261
	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
		return flexcan_set_bittiming_cbt(dev);
	else
		return flexcan_set_bittiming_ctrl(dev);
1262 1263
}

1264
/* flexcan_chip_start
1265 1266 1267 1268 1269 1270 1271
 *
 * this functions is entered with clocks enabled
 *
 */
static int flexcan_chip_start(struct net_device *dev)
{
	struct flexcan_priv *priv = netdev_priv(dev);
1272
	struct flexcan_regs __iomem *regs = priv->regs;
1273
	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1274
	u64 reg_imask;
1275
	int err, i;
1276
	struct flexcan_mb __iomem *mb;
1277 1278

	/* enable module */
1279 1280 1281
	err = flexcan_chip_enable(priv);
	if (err)
		return err;
1282 1283

	/* soft reset */
1284 1285
	err = flexcan_chip_softreset(priv);
	if (err)
1286
		goto out_chip_disable;
1287 1288 1289

	flexcan_set_bittiming(dev);

1290
	/* MCR
1291 1292 1293 1294 1295
	 *
	 * enable freeze
	 * halt now
	 * only supervisor access
	 * enable warning int
1296
	 * enable individual RX masking
1297 1298
	 * choose format C
	 * set max mailbox number
1299
	 */
1300
	reg_mcr = priv->read(&regs->mcr);
1301
	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1302
	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1303
		FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1304
		FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1305

1306 1307 1308 1309 1310 1311
	/* MCR
	 *
	 * FIFO:
	 * - disable for timestamp mode
	 * - enable for FIFO mode
	 */
1312
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1313
		reg_mcr &= ~FLEXCAN_MCR_FEN;
1314 1315 1316
	else
		reg_mcr |= FLEXCAN_MCR_FEN;

1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
	/* MCR
	 *
	 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
	 *       asserted because this will impede the self reception
	 *       of a transmitted message. This is not documented in
	 *       earlier versions of flexcan block guide.
	 *
	 * Self Reception:
	 * - enable Self Reception for loopback mode
	 *   (by clearing "Self Reception Disable" bit)
	 * - disable for normal operation
	 */
	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
		reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
	else
		reg_mcr |= FLEXCAN_MCR_SRX_DIS;

1334 1335 1336 1337 1338 1339
	/* MCR - CAN-FD */
	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
		reg_mcr |= FLEXCAN_MCR_FDEN;
	else
		reg_mcr &= ~FLEXCAN_MCR_FDEN;

1340
	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1341
	priv->write(reg_mcr, &regs->mcr);
1342

1343
	/* CTRL
1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
	 *
	 * disable timer sync feature
	 *
	 * disable auto busoff recovery
	 * transmit lowest buffer first
	 *
	 * enable tx and rx warning interrupt
	 * enable bus off interrupt
	 * (== FLEXCAN_CTRL_ERR_STATE)
	 */
1354
	reg_ctrl = priv->read(&regs->ctrl);
1355 1356
	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1357
		FLEXCAN_CTRL_ERR_STATE;
1358 1359

	/* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1360 1361 1362
	 * on most Flexcan cores, too. Otherwise we don't get
	 * any error warning or passive interrupts.
	 */
1363
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1364 1365
	    priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
		reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1366 1367
	else
		reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1368 1369 1370

	/* save for later use */
	priv->reg_ctrl_default = reg_ctrl;
1371 1372
	/* leave interrupts disabled for now */
	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1373
	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1374
	priv->write(reg_ctrl, &regs->ctrl);
1375

1376
	if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1377
		reg_ctrl2 = priv->read(&regs->ctrl2);
1378
		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1379
		priv->write(reg_ctrl2, &regs->ctrl2);
1380 1381
	}

1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
		u32 reg_fdctrl;

		reg_fdctrl = priv->read(&regs->fdctrl);
		reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));

		if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
			reg_fdctrl |=
				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
					   FLEXCAN_FDCTRL_MBDSR_64) |
				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
					   FLEXCAN_FDCTRL_MBDSR_64);
		} else {
			reg_fdctrl |=
				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
					   FLEXCAN_FDCTRL_MBDSR_8) |
				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
					   FLEXCAN_FDCTRL_MBDSR_8);
		}

		netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
			   __func__, reg_fdctrl);
		priv->write(reg_fdctrl, &regs->fdctrl);
	}

1408
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1409
		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1410
			mb = flexcan_get_mb(priv, i);
1411
			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1412
				    &mb->can_ctrl);
1413 1414 1415
		}
	} else {
		/* clear and invalidate unused mailboxes first */
1416
		for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1417
			mb = flexcan_get_mb(priv, i);
1418
			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1419
				    &mb->can_ctrl);
1420
		}
1421 1422
	}

1423
	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
1424 1425
	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
		    &priv->tx_mb_reserved->can_ctrl);
1426

1427
	/* mark TX mailbox as INACTIVE */
1428
	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1429
		    &priv->tx_mb->can_ctrl);
1430

1431
	/* acceptance mask/acceptance code (accept everything) */
1432 1433 1434
	priv->write(0x0, &regs->rxgmask);
	priv->write(0x0, &regs->rx14mask);
	priv->write(0x0, &regs->rx15mask);
1435

1436
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1437
		priv->write(0x0, &regs->rxfgmask);
1438

1439
	/* clear acceptance filters */
1440
	for (i = 0; i < priv->mb_count; i++)
1441
		priv->write(0, &regs->rximr[i]);
1442

1443 1444 1445 1446 1447 1448
	/* On Vybrid, disable non-correctable errors interrupt and
	 * freeze mode. It still can correct the correctable errors
	 * when HW supports ECC.
	 *
	 * This also works around errata e5295 which generates false
	 * positive memory errors and put the device in freeze mode.
1449
	 */
1450
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1451
		/* Follow the protocol as described in "Detection
1452
		 * and Correction of Memory Errors" to write to
1453 1454 1455 1456
		 * MECR register (step 1 - 5)
		 *
		 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
		 * 2. set CTRL2[ECRWRE]
1457
		 */
1458
		reg_ctrl2 = priv->read(&regs->ctrl2);
1459
		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1460
		priv->write(reg_ctrl2, &regs->ctrl2);
1461

1462
		/* 3. clear MECR[ECRWRDIS] */
1463
		reg_mecr = priv->read(&regs->mecr);
1464
		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1465
		priv->write(reg_mecr, &regs->mecr);
1466 1467

		/* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1468
		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1469
			      FLEXCAN_MECR_FANCEI_MSK);
1470
		priv->write(reg_mecr, &regs->mecr);
1471 1472 1473 1474 1475 1476 1477 1478 1479

		/* 5. after configuration done, lock MECR by either
		 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
		 */
		reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
		priv->write(reg_mecr, &regs->mecr);

		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
		priv->write(reg_ctrl2, &regs->ctrl2);
1480 1481
	}

1482 1483
	err = flexcan_transceiver_enable(priv);
	if (err)
1484
		goto out_chip_disable;
1485 1486

	/* synchronize with the can bus */
1487 1488 1489
	err = flexcan_chip_unfreeze(priv);
	if (err)
		goto out_transceiver_disable;
1490 1491 1492

	priv->can.state = CAN_STATE_ERROR_ACTIVE;

1493 1494
	/* enable interrupts atomically */
	disable_irq(dev->irq);
1495
	priv->write(priv->reg_ctrl_default, &regs->ctrl);
1496
	reg_imask = priv->rx_mask | priv->tx_mask;
1497 1498
	priv->write(upper_32_bits(reg_imask), &regs->imask2);
	priv->write(lower_32_bits(reg_imask), &regs->imask1);
1499
	enable_irq(dev->irq);
1500 1501

	/* print chip status */
1502
	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1503
		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1504 1505 1506

	return 0;

1507 1508 1509
 out_transceiver_disable:
	flexcan_transceiver_disable(priv);
 out_chip_disable:
1510 1511 1512 1513
	flexcan_chip_disable(priv);
	return err;
}

1514
/* __flexcan_chip_stop
1515
 *
1516
 * this function is entered with clocks enabled
1517
 */
1518
static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1519 1520
{
	struct flexcan_priv *priv = netdev_priv(dev);
1521
	struct flexcan_regs __iomem *regs = priv->regs;
1522
	int err;
1523

1524
	/* freeze + disable module */
1525 1526 1527 1528 1529 1530
	err = flexcan_chip_freeze(priv);
	if (err && !disable_on_error)
		return err;
	err = flexcan_chip_disable(priv);
	if (err && !disable_on_error)
		goto out_chip_unfreeze;
1531

1532
	/* Disable all interrupts */
1533 1534 1535 1536
	priv->write(0, &regs->imask2);
	priv->write(0, &regs->imask1);
	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
		    &regs->ctrl);
1537

1538
	flexcan_transceiver_disable(priv);
1539
	priv->can.state = CAN_STATE_STOPPED;
1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556

	return 0;

 out_chip_unfreeze:
	flexcan_chip_unfreeze(priv);

	return err;
}

static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
{
	return __flexcan_chip_stop(dev, true);
}

static inline int flexcan_chip_stop(struct net_device *dev)
{
	return __flexcan_chip_stop(dev, false);
1557 1558 1559 1560 1561 1562 1563
}

static int flexcan_open(struct net_device *dev)
{
	struct flexcan_priv *priv = netdev_priv(dev);
	int err;

1564 1565 1566 1567 1568 1569
	if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
	    (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
		netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
		return -EINVAL;
	}

1570 1571
	err = pm_runtime_get_sync(priv->dev);
	if (err < 0)
1572 1573
		return err;

1574 1575
	err = open_candev(dev);
	if (err)
1576
		goto out_runtime_put;
1577 1578 1579 1580 1581

	err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
	if (err)
		goto out_close;

1582 1583 1584 1585
	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
		priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
	else
		priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1586 1587
	priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
			 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1588

1589
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1590 1591
		priv->tx_mb_reserved =
			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1592
	else
1593 1594 1595 1596
		priv->tx_mb_reserved =
			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
	priv->tx_mb_idx = priv->mb_count - 1;
	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1597
	priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1598 1599 1600 1601 1602

	priv->offload.mailbox_read = flexcan_mailbox_read;

	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
		priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1603
		priv->offload.mb_last = priv->mb_count - 2;
1604

1605 1606
		priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
					    priv->offload.mb_first);
1607 1608
		err = can_rx_offload_add_timestamp(dev, &priv->offload);
	} else {
1609
		priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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			FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
		err = can_rx_offload_add_fifo(dev, &priv->offload,
					      FLEXCAN_NAPI_WEIGHT);
	}
	if (err)
		goto out_free_irq;

1617 1618 1619
	/* start chip and queuing */
	err = flexcan_chip_start(dev);
	if (err)
1620
		goto out_offload_del;
1621 1622 1623

	can_led_event(dev, CAN_LED_EVENT_OPEN);

1624
	can_rx_offload_enable(&priv->offload);
1625 1626 1627 1628
	netif_start_queue(dev);

	return 0;

1629 1630
 out_offload_del:
	can_rx_offload_del(&priv->offload);
1631 1632
 out_free_irq:
	free_irq(dev->irq, dev);
1633 1634
 out_close:
	close_candev(dev);
1635 1636
 out_runtime_put:
	pm_runtime_put(priv->dev);
1637 1638 1639 1640 1641 1642 1643 1644 1645

	return err;
}

static int flexcan_close(struct net_device *dev)
{
	struct flexcan_priv *priv = netdev_priv(dev);

	netif_stop_queue(dev);
1646
	can_rx_offload_disable(&priv->offload);
1647
	flexcan_chip_stop_disable_on_error(dev);
1648

1649
	can_rx_offload_del(&priv->offload);
1650 1651 1652
	free_irq(dev->irq, dev);

	close_candev(dev);
1653
	pm_runtime_put(priv->dev);
1654

1655 1656
	can_led_event(dev, CAN_LED_EVENT_STOP);

1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683
	return 0;
}

static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
{
	int err;

	switch (mode) {
	case CAN_MODE_START:
		err = flexcan_chip_start(dev);
		if (err)
			return err;

		netif_wake_queue(dev);
		break;

	default:
		return -EOPNOTSUPP;
	}

	return 0;
}

static const struct net_device_ops flexcan_netdev_ops = {
	.ndo_open	= flexcan_open,
	.ndo_stop	= flexcan_close,
	.ndo_start_xmit	= flexcan_start_xmit,
1684
	.ndo_change_mtu = can_change_mtu,
1685 1686
};

1687
static int register_flexcandev(struct net_device *dev)
1688 1689
{
	struct flexcan_priv *priv = netdev_priv(dev);
1690
	struct flexcan_regs __iomem *regs = priv->regs;
1691 1692
	u32 reg, err;

1693
	err = flexcan_clks_enable(priv);
1694 1695 1696
	if (err)
		return err;

1697
	/* select "bus clock", chip must be disabled */
1698 1699
	err = flexcan_chip_disable(priv);
	if (err)
1700 1701
		goto out_clks_disable;

1702
	reg = priv->read(&regs->ctrl);
1703 1704 1705 1706
	if (priv->clk_src)
		reg |= FLEXCAN_CTRL_CLK_SRC;
	else
		reg &= ~FLEXCAN_CTRL_CLK_SRC;
1707
	priv->write(reg, &regs->ctrl);
1708

1709 1710 1711
	err = flexcan_chip_enable(priv);
	if (err)
		goto out_chip_disable;
1712 1713

	/* set freeze, halt and activate FIFO, restrict register access */
1714
	reg = priv->read(&regs->mcr);
1715 1716
	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
		FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1717
	priv->write(reg, &regs->mcr);
1718

1719
	/* Currently we only support newer versions of this core
1720 1721 1722
	 * featuring a RX hardware FIFO (although this driver doesn't
	 * make use of it on some cores). Older cores, found on some
	 * Coldfire derivates are not tested.
1723
	 */
1724
	reg = priv->read(&regs->mcr);
1725
	if (!(reg & FLEXCAN_MCR_FEN)) {
1726
		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1727
		err = -ENODEV;
1728
		goto out_chip_disable;
1729 1730 1731
	}

	err = register_candev(dev);
1732 1733
	if (err)
		goto out_chip_disable;
1734

1735 1736 1737
	/* Disable core and let pm_runtime_put() disable the clocks.
	 * If CONFIG_PM is not enabled, the clocks will stay powered.
	 */
1738
	flexcan_chip_disable(priv);
1739 1740 1741
	pm_runtime_put(priv->dev);

	return 0;
1742

1743 1744 1745 1746
 out_chip_disable:
	flexcan_chip_disable(priv);
 out_clks_disable:
	flexcan_clks_disable(priv);
1747 1748 1749
	return err;
}

1750
static void unregister_flexcandev(struct net_device *dev)
1751 1752 1753 1754
{
	unregister_candev(dev);
}

1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781
static int flexcan_setup_stop_mode(struct platform_device *pdev)
{
	struct net_device *dev = platform_get_drvdata(pdev);
	struct device_node *np = pdev->dev.of_node;
	struct device_node *gpr_np;
	struct flexcan_priv *priv;
	phandle phandle;
	u32 out_val[5];
	int ret;

	if (!np)
		return -EINVAL;

	/* stop mode property format is:
	 * <&gpr req_gpr req_bit ack_gpr ack_bit>.
	 */
	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
					 ARRAY_SIZE(out_val));
	if (ret) {
		dev_dbg(&pdev->dev, "no stop-mode property\n");
		return ret;
	}
	phandle = *out_val;

	gpr_np = of_find_node_by_phandle(phandle);
	if (!gpr_np) {
		dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1782
		return -ENODEV;
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	}

	priv = netdev_priv(dev);
	priv->stm.gpr = syscon_node_to_regmap(gpr_np);
	if (IS_ERR(priv->stm.gpr)) {
		dev_dbg(&pdev->dev, "could not find gpr regmap\n");
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		ret = PTR_ERR(priv->stm.gpr);
		goto out_put_node;
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	}

	priv->stm.req_gpr = out_val[1];
	priv->stm.req_bit = out_val[2];
	priv->stm.ack_gpr = out_val[3];
	priv->stm.ack_bit = out_val[4];

	dev_dbg(&pdev->dev,
		"gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
		gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
		priv->stm.ack_gpr, priv->stm.ack_bit);

	device_set_wakeup_capable(&pdev->dev, true);

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	if (of_property_read_bool(np, "wakeup-source"))
		device_set_wakeup_enable(&pdev->dev, true);

1808
	return 0;
1809

1810 1811 1812
out_put_node:
	of_node_put(gpr_np);
	return ret;
1813 1814
}

1815 1816
static const struct of_device_id flexcan_of_match[] = {
	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
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	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
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	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1821
	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1822
	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1823
	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1824 1825
	{ /* sentinel */ },
};
1826
MODULE_DEVICE_TABLE(of, flexcan_of_match);
1827 1828 1829 1830 1831

static const struct platform_device_id flexcan_id_table[] = {
	{ .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
	{ /* sentinel */ },
};
1832
MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1833

1834
static int flexcan_probe(struct platform_device *pdev)
1835
{
1836
	const struct of_device_id *of_id;
1837
	const struct flexcan_devtype_data *devtype_data;
1838 1839
	struct net_device *dev;
	struct flexcan_priv *priv;
1840
	struct regulator *reg_xceiver;
1841
	struct clk *clk_ipg = NULL, *clk_per = NULL;
1842
	struct flexcan_regs __iomem *regs;
1843
	int err, irq;
1844
	u8 clk_src = 1;
1845 1846
	u32 clock_freq = 0;

1847
	reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
1848 1849
	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
		return -EPROBE_DEFER;
1850
	else if (PTR_ERR(reg_xceiver) == -ENODEV)
1851
		reg_xceiver = NULL;
1852 1853
	else if (IS_ERR(reg_xceiver))
		return PTR_ERR(reg_xceiver);
1854

1855
	if (pdev->dev.of_node) {
1856
		of_property_read_u32(pdev->dev.of_node,
1857
				     "clock-frequency", &clock_freq);
1858 1859 1860
		of_property_read_u8(pdev->dev.of_node,
				    "fsl,clk-source", &clk_src);
	}
1861 1862

	if (!clock_freq) {
1863 1864 1865
		clk_ipg = devm_clk_get(&pdev->dev, "ipg");
		if (IS_ERR(clk_ipg)) {
			dev_err(&pdev->dev, "no ipg clock defined\n");
1866
			return PTR_ERR(clk_ipg);
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		}

		clk_per = devm_clk_get(&pdev->dev, "per");
		if (IS_ERR(clk_per)) {
			dev_err(&pdev->dev, "no per clock defined\n");
1872
			return PTR_ERR(clk_per);
1873
		}
1874
		clock_freq = clk_get_rate(clk_per);
1875 1876 1877
	}

	irq = platform_get_irq(pdev, 0);
1878 1879
	if (irq <= 0)
		return -ENODEV;
1880

1881
	regs = devm_platform_ioremap_resource(pdev, 0);
1882 1883
	if (IS_ERR(regs))
		return PTR_ERR(regs);
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1885 1886 1887
	of_id = of_match_device(flexcan_of_match, &pdev->dev);
	if (of_id) {
		devtype_data = of_id->data;
1888
	} else if (platform_get_device_id(pdev)->driver_data) {
1889
		devtype_data = (struct flexcan_devtype_data *)
1890
			platform_get_device_id(pdev)->driver_data;
1891
	} else {
1892
		return -ENODEV;
1893 1894
	}

1895 1896 1897 1898 1899 1900
	if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
	    !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
		dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
		return -EINVAL;
	}

1901 1902 1903 1904
	dev = alloc_candev(sizeof(struct flexcan_priv), 1);
	if (!dev)
		return -ENOMEM;

1905 1906 1907
	platform_set_drvdata(pdev, dev);
	SET_NETDEV_DEV(dev, &pdev->dev);

1908 1909
	dev->netdev_ops = &flexcan_netdev_ops;
	dev->irq = irq;
1910
	dev->flags |= IFF_ECHO;
1911 1912

	priv = netdev_priv(dev);
1913

1914 1915
	if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
	    devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
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		priv->read = flexcan_read_be;
		priv->write = flexcan_write_be;
	} else {
1919 1920
		priv->read = flexcan_read_le;
		priv->write = flexcan_write_le;
1921 1922
	}

1923
	priv->dev = &pdev->dev;
1924
	priv->can.clock.freq = clock_freq;
1925 1926 1927 1928 1929
	priv->can.do_set_mode = flexcan_set_mode;
	priv->can.do_get_berr_counter = flexcan_get_berr_counter;
	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
		CAN_CTRLMODE_LISTENONLY	| CAN_CTRLMODE_3_SAMPLES |
		CAN_CTRLMODE_BERR_REPORTING;
1930
	priv->regs = regs;
1931 1932
	priv->clk_ipg = clk_ipg;
	priv->clk_per = clk_per;
1933
	priv->clk_src = clk_src;
1934
	priv->devtype_data = devtype_data;
1935
	priv->reg_xceiver = reg_xceiver;
1936

1937
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
1938 1939
		priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
			CAN_CTRLMODE_FD_NON_ISO;
1940 1941 1942 1943 1944 1945 1946
		priv->can.bittiming_const = &flexcan_fd_bittiming_const;
		priv->can.data_bittiming_const =
			&flexcan_fd_data_bittiming_const;
	} else {
		priv->can.bittiming_const = &flexcan_bittiming_const;
	}

1947 1948 1949 1950
	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

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	err = register_flexcandev(dev);
	if (err) {
		dev_err(&pdev->dev, "registering netdev failed\n");
		goto failed_register;
	}

1957
	of_can_transceiver(dev);
1958 1959
	devm_can_led_init(dev);

1960 1961 1962 1963 1964 1965
	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
		err = flexcan_setup_stop_mode(pdev);
		if (err)
			dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
	}

1966 1967 1968 1969 1970 1971 1972
	return 0;

 failed_register:
	free_candev(dev);
	return err;
}

1973
static int flexcan_remove(struct platform_device *pdev)
1974 1975 1976 1977
{
	struct net_device *dev = platform_get_drvdata(pdev);

	unregister_flexcandev(dev);
1978
	pm_runtime_disable(&pdev->dev);
1979 1980
	free_candev(dev);

1981 1982 1983
	return 0;
}

1984
static int __maybe_unused flexcan_suspend(struct device *device)
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1985
{
1986
	struct net_device *dev = dev_get_drvdata(device);
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1987
	struct flexcan_priv *priv = netdev_priv(dev);
1988
	int err;
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1989 1990

	if (netif_running(dev)) {
1991 1992 1993 1994 1995
		/* if wakeup is enabled, enter stop mode
		 * else enter disabled mode.
		 */
		if (device_may_wakeup(device)) {
			enable_irq_wake(dev->irq);
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			err = flexcan_enter_stop_mode(priv);
			if (err)
				return err;
1999
		} else {
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			err = flexcan_chip_stop(dev);
			if (err)
				return err;

			err = pinctrl_pm_select_sleep_state(device);
2005 2006 2007
			if (err)
				return err;
		}
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		netif_stop_queue(dev);
		netif_device_detach(dev);
	}
	priv->can.state = CAN_STATE_SLEEPING;

2013
	return 0;
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}

2016
static int __maybe_unused flexcan_resume(struct device *device)
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{
2018
	struct net_device *dev = dev_get_drvdata(device);
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	struct flexcan_priv *priv = netdev_priv(dev);
2020
	int err;
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	priv->can.state = CAN_STATE_ERROR_ACTIVE;
	if (netif_running(dev)) {
		netif_device_attach(dev);
		netif_start_queue(dev);
2026 2027
		if (device_may_wakeup(device)) {
			disable_irq_wake(dev->irq);
2028 2029 2030
			err = flexcan_exit_stop_mode(priv);
			if (err)
				return err;
2031
		} else {
2032 2033 2034 2035 2036 2037 2038
			err = pinctrl_pm_select_default_state(device);
			if (err)
				return err;

			err = flexcan_chip_start(dev);
			if (err)
				return err;
2039
		}
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2040
	}
2041

2042
	return 0;
2043 2044 2045 2046 2047 2048 2049 2050 2051
}

static int __maybe_unused flexcan_runtime_suspend(struct device *device)
{
	struct net_device *dev = dev_get_drvdata(device);
	struct flexcan_priv *priv = netdev_priv(dev);

	flexcan_clks_disable(priv);

2052
	return 0;
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2053
}
2054

2055 2056 2057 2058 2059 2060 2061 2062
static int __maybe_unused flexcan_runtime_resume(struct device *device)
{
	struct net_device *dev = dev_get_drvdata(device);
	struct flexcan_priv *priv = netdev_priv(dev);

	return flexcan_clks_enable(priv);
}

2063 2064 2065 2066 2067
static int __maybe_unused flexcan_noirq_suspend(struct device *device)
{
	struct net_device *dev = dev_get_drvdata(device);
	struct flexcan_priv *priv = netdev_priv(dev);

2068 2069 2070 2071 2072 2073 2074 2075 2076 2077
	if (netif_running(dev)) {
		int err;

		if (device_may_wakeup(device))
			flexcan_enable_wakeup_irq(priv, true);

		err = pm_runtime_force_suspend(device);
		if (err)
			return err;
	}
2078 2079 2080 2081 2082 2083 2084 2085 2086

	return 0;
}

static int __maybe_unused flexcan_noirq_resume(struct device *device)
{
	struct net_device *dev = dev_get_drvdata(device);
	struct flexcan_priv *priv = netdev_priv(dev);

2087 2088 2089 2090 2091 2092 2093 2094 2095 2096
	if (netif_running(dev)) {
		int err;

		err = pm_runtime_force_resume(device);
		if (err)
			return err;

		if (device_may_wakeup(device))
			flexcan_enable_wakeup_irq(priv, false);
	}
2097 2098 2099 2100 2101 2102

	return 0;
}

static const struct dev_pm_ops flexcan_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2103
	SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2104 2105
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
};
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2106

2107
static struct platform_driver flexcan_driver = {
2108 2109
	.driver = {
		.name = DRV_NAME,
2110
		.pm = &flexcan_pm_ops,
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		.of_match_table = flexcan_of_match,
	},
2113
	.probe = flexcan_probe,
2114
	.remove = flexcan_remove,
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	.id_table = flexcan_id_table,
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};

2118
module_platform_driver(flexcan_driver);
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MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
	      "Marc Kleine-Budde <kernel@pengutronix.de>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("CAN port driver for flexcan based chip");