intel_tv.c 48.7 KB
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/*
 * Copyright © 2006-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

/** @file
 * Integrated TV-out support for the 915GM and 945GM.
 */

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

enum tv_margin {
	TV_MARGIN_LEFT, TV_MARGIN_TOP,
	TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
};

/** Private structure for the integrated TV support */
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struct intel_tv {
	struct intel_encoder base;

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	int type;
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	const char *tv_format;
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	int margin[4];
	u32 save_TV_H_CTL_1;
	u32 save_TV_H_CTL_2;
	u32 save_TV_H_CTL_3;
	u32 save_TV_V_CTL_1;
	u32 save_TV_V_CTL_2;
	u32 save_TV_V_CTL_3;
	u32 save_TV_V_CTL_4;
	u32 save_TV_V_CTL_5;
	u32 save_TV_V_CTL_6;
	u32 save_TV_V_CTL_7;
	u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;

	u32 save_TV_CSC_Y;
	u32 save_TV_CSC_Y2;
	u32 save_TV_CSC_U;
	u32 save_TV_CSC_U2;
	u32 save_TV_CSC_V;
	u32 save_TV_CSC_V2;
	u32 save_TV_CLR_KNOBS;
	u32 save_TV_CLR_LEVEL;
	u32 save_TV_WIN_POS;
	u32 save_TV_WIN_SIZE;
	u32 save_TV_FILTER_CTL_1;
	u32 save_TV_FILTER_CTL_2;
	u32 save_TV_FILTER_CTL_3;

	u32 save_TV_H_LUMA[60];
	u32 save_TV_H_CHROMA[60];
	u32 save_TV_V_LUMA[43];
	u32 save_TV_V_CHROMA[43];

	u32 save_TV_DAC;
	u32 save_TV_CTL;
};

struct video_levels {
	int blank, black, burst;
};

struct color_conversion {
	u16 ry, gy, by, ay;
	u16 ru, gu, bu, au;
	u16 rv, gv, bv, av;
};

static const u32 filter_table[] = {
	0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
	0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
	0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
	0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
	0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
	0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
	0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
	0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
	0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
	0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
	0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
	0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
	0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
	0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
	0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
	0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
	0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
	0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
	0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
	0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
	0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
	0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
	0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
	0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
	0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
	0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
	0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
	0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
	0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
	0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
	0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
	0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
	0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
	0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
	0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
	0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
	0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
	0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
	0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
	0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
	0x28003100, 0x28002F00, 0x00003100, 0x36403000,
	0x2D002CC0, 0x30003640, 0x2D0036C0,
	0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
	0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
	0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
	0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
	0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
	0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
	0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
	0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
	0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
	0x28003100, 0x28002F00, 0x00003100,
};

/*
 * Color conversion values have 3 separate fixed point formats:
 *
 * 10 bit fields (ay, au)
 *   1.9 fixed point (b.bbbbbbbbb)
 * 11 bit fields (ry, by, ru, gu, gv)
 *   exp.mantissa (ee.mmmmmmmmm)
 *   ee = 00 = 10^-1 (0.mmmmmmmmm)
 *   ee = 01 = 10^-2 (0.0mmmmmmmmm)
 *   ee = 10 = 10^-3 (0.00mmmmmmmmm)
 *   ee = 11 = 10^-4 (0.000mmmmmmmmm)
 * 12 bit fields (gy, rv, bu)
 *   exp.mantissa (eee.mmmmmmmmm)
 *   eee = 000 = 10^-1 (0.mmmmmmmmm)
 *   eee = 001 = 10^-2 (0.0mmmmmmmmm)
 *   eee = 010 = 10^-3 (0.00mmmmmmmmm)
 *   eee = 011 = 10^-4 (0.000mmmmmmmmm)
 *   eee = 100 = reserved
 *   eee = 101 = reserved
 *   eee = 110 = reserved
 *   eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
 *
 * Saturation and contrast are 8 bits, with their own representation:
 * 8 bit field (saturation, contrast)
 *   exp.mantissa (ee.mmmmmm)
 *   ee = 00 = 10^-1 (0.mmmmmm)
 *   ee = 01 = 10^0 (m.mmmmm)
 *   ee = 10 = 10^1 (mm.mmmm)
 *   ee = 11 = 10^2 (mmm.mmm)
 *
 * Simple conversion function:
 *
 * static u32
 * float_to_csc_11(float f)
 * {
 *     u32 exp;
 *     u32 mant;
 *     u32 ret;
 *
 *     if (f < 0)
 *         f = -f;
 *
 *     if (f >= 1) {
 *         exp = 0x7;
 * 	   mant = 1 << 8;
 *     } else {
 *         for (exp = 0; exp < 3 && f < 0.5; exp++)
 * 	       f *= 2.0;
 *         mant = (f * (1 << 9) + 0.5);
 *         if (mant >= (1 << 9))
 *             mant = (1 << 9) - 1;
 *     }
 *     ret = (exp << 9) | mant;
 *     return ret;
 * }
 */

/*
 * Behold, magic numbers!  If we plant them they might grow a big
 * s-video cable to the sky... or something.
 *
 * Pre-converted to appropriate hex value.
 */

/*
 * PAL & NTSC values for composite & s-video connections
 */
static const struct color_conversion ntsc_m_csc_composite = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
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	.ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
	.rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
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};

static const struct video_levels ntsc_m_levels_composite = {
	.blank = 225, .black = 267, .burst = 113,
};

static const struct color_conversion ntsc_m_csc_svideo = {
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	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
	.ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
	.rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
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};

static const struct video_levels ntsc_m_levels_svideo = {
	.blank = 266, .black = 316, .burst = 133,
};

static const struct color_conversion ntsc_j_csc_composite = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
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	.ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
	.rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
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};

static const struct video_levels ntsc_j_levels_composite = {
	.blank = 225, .black = 225, .burst = 113,
};

static const struct color_conversion ntsc_j_csc_svideo = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
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	.ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
	.rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
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};

static const struct video_levels ntsc_j_levels_svideo = {
	.blank = 266, .black = 266, .burst = 133,
};

static const struct color_conversion pal_csc_composite = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
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	.ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
	.rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
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};

static const struct video_levels pal_levels_composite = {
	.blank = 237, .black = 237, .burst = 118,
};

static const struct color_conversion pal_csc_svideo = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
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	.ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
	.rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
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};

static const struct video_levels pal_levels_svideo = {
	.blank = 280, .black = 280, .burst = 139,
};

static const struct color_conversion pal_m_csc_composite = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
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	.ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
	.rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
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};

static const struct video_levels pal_m_levels_composite = {
	.blank = 225, .black = 267, .burst = 113,
};

static const struct color_conversion pal_m_csc_svideo = {
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	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
	.ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
	.rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
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};

static const struct video_levels pal_m_levels_svideo = {
	.blank = 266, .black = 316, .burst = 133,
};

static const struct color_conversion pal_n_csc_composite = {
	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
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	.ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
	.rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
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};

static const struct video_levels pal_n_levels_composite = {
	.blank = 225, .black = 267, .burst = 118,
};

static const struct color_conversion pal_n_csc_svideo = {
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	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
	.ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
	.rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
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};

static const struct video_levels pal_n_levels_svideo = {
	.blank = 266, .black = 316, .burst = 139,
};

/*
 * Component connections
 */
static const struct color_conversion sdtv_csc_yprpb = {
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	.ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
	.ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
	.rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
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};

static const struct color_conversion sdtv_csc_rgb = {
	.ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
	.ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
	.rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
};

static const struct color_conversion hdtv_csc_yprpb = {
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	.ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
	.ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
	.rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
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};

static const struct color_conversion hdtv_csc_rgb = {
	.ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
	.ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
	.rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
};

static const struct video_levels component_levels = {
	.blank = 279, .black = 279, .burst = 0,
};


struct tv_mode {
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	const char *name;
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	int clock;
	int refresh; /* in millihertz (for precision) */
	u32 oversample;
	int hsync_end, hblank_start, hblank_end, htotal;
	bool progressive, trilevel_sync, component_only;
	int vsync_start_f1, vsync_start_f2, vsync_len;
	bool veq_ena;
	int veq_start_f1, veq_start_f2, veq_len;
	int vi_end_f1, vi_end_f2, nbr_end;
	bool burst_ena;
	int hburst_start, hburst_len;
	int vburst_start_f1, vburst_end_f1;
	int vburst_start_f2, vburst_end_f2;
	int vburst_start_f3, vburst_end_f3;
	int vburst_start_f4, vburst_end_f4;
	/*
	 * subcarrier programming
	 */
	int dda2_size, dda3_size, dda1_inc, dda2_inc, dda3_inc;
	u32 sc_reset;
	bool pal_burst;
	/*
	 * blank/black levels
	 */
	const struct video_levels *composite_levels, *svideo_levels;
	const struct color_conversion *composite_color, *svideo_color;
	const u32 *filter_table;
	int max_srcw;
};


/*
 * Sub carrier DDA
 *
 *  I think this works as follows:
 *
 *  subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
 *
 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
 *
 * So,
 *  dda1_ideal = subcarrier/pixel * 4096
 *  dda1_inc = floor (dda1_ideal)
 *  dda2 = dda1_ideal - dda1_inc
 *
 *  then pick a ratio for dda2 that gives the closest approximation. If
 *  you can't get close enough, you can play with dda3 as well. This
 *  seems likely to happen when dda2 is small as the jumps would be larger
 *
 * To invert this,
 *
 *  pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
 *
 * The constants below were all computed using a 107.520MHz clock
 */

/**
 * Register programming values for TV modes.
 *
 * These values account for -1s required.
 */

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static const struct tv_mode tv_modes[] = {
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	{
		.name		= "NTSC-M",
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		.clock		= 108000,
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		.refresh	= 29970,
		.oversample	= TV_OVERSAMPLE_8X,
		.component_only = 0,
		/* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */

		.hsync_end	= 64,		    .hblank_end		= 124,
		.hblank_start	= 836,		    .htotal		= 857,

		.progressive	= false,	    .trilevel_sync = false,

		.vsync_start_f1	= 6,		    .vsync_start_f2	= 7,
		.vsync_len	= 6,

		.veq_ena	= true,		    .veq_start_f1    	= 0,
		.veq_start_f2	= 1,		    .veq_len		= 18,

		.vi_end_f1	= 20,		    .vi_end_f2		= 21,
		.nbr_end	= 240,

		.burst_ena	= true,
		.hburst_start	= 72,		    .hburst_len		= 34,
		.vburst_start_f1 = 9,		    .vburst_end_f1	= 240,
		.vburst_start_f2 = 10,		    .vburst_end_f2	= 240,
		.vburst_start_f3 = 9,		    .vburst_end_f3	= 240,
		.vburst_start_f4 = 10,		    .vburst_end_f4	= 240,

		/* desired 3.5800000 actual 3.5800000 clock 107.52 */
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		.dda1_inc	=    135,
		.dda2_inc	=  20800,	    .dda2_size		=  27456,
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		.dda3_inc	=      0,	    .dda3_size		=      0,
		.sc_reset	= TV_SC_RESET_EVERY_4,
		.pal_burst	= false,

		.composite_levels = &ntsc_m_levels_composite,
		.composite_color = &ntsc_m_csc_composite,
		.svideo_levels  = &ntsc_m_levels_svideo,
		.svideo_color = &ntsc_m_csc_svideo,

		.filter_table = filter_table,
	},
	{
		.name		= "NTSC-443",
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		.clock		= 108000,
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		.refresh	= 29970,
		.oversample	= TV_OVERSAMPLE_8X,
		.component_only = 0,
		/* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
		.hsync_end	= 64,		    .hblank_end		= 124,
		.hblank_start	= 836,		    .htotal		= 857,

		.progressive	= false,	    .trilevel_sync = false,

		.vsync_start_f1 = 6,		    .vsync_start_f2	= 7,
		.vsync_len	= 6,

		.veq_ena	= true,		    .veq_start_f1    	= 0,
		.veq_start_f2	= 1,		    .veq_len		= 18,

		.vi_end_f1	= 20,		    .vi_end_f2		= 21,
		.nbr_end	= 240,

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		.burst_ena	= true,
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		.hburst_start	= 72,		    .hburst_len		= 34,
		.vburst_start_f1 = 9,		    .vburst_end_f1	= 240,
		.vburst_start_f2 = 10,		    .vburst_end_f2	= 240,
		.vburst_start_f3 = 9,		    .vburst_end_f3	= 240,
		.vburst_start_f4 = 10,		    .vburst_end_f4	= 240,

		/* desired 4.4336180 actual 4.4336180 clock 107.52 */
		.dda1_inc       =    168,
490 491 492 493
		.dda2_inc       =   4093,       .dda2_size      =  27456,
		.dda3_inc       =    310,       .dda3_size      =    525,
		.sc_reset   = TV_SC_RESET_NEVER,
		.pal_burst  = false,
494 495 496 497 498 499 500 501 502 503

		.composite_levels = &ntsc_m_levels_composite,
		.composite_color = &ntsc_m_csc_composite,
		.svideo_levels  = &ntsc_m_levels_svideo,
		.svideo_color = &ntsc_m_csc_svideo,

		.filter_table = filter_table,
	},
	{
		.name		= "NTSC-J",
504
		.clock		= 108000,
505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531
		.refresh	= 29970,
		.oversample	= TV_OVERSAMPLE_8X,
		.component_only = 0,

		/* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
		.hsync_end	= 64,		    .hblank_end		= 124,
		.hblank_start = 836,	    .htotal		= 857,

		.progressive	= false,    .trilevel_sync = false,

		.vsync_start_f1	= 6,	    .vsync_start_f2	= 7,
		.vsync_len	= 6,

		.veq_ena	= true,		    .veq_start_f1    	= 0,
		.veq_start_f2 = 1,	    .veq_len		= 18,

		.vi_end_f1	= 20,		    .vi_end_f2		= 21,
		.nbr_end	= 240,

		.burst_ena	= true,
		.hburst_start	= 72,		    .hburst_len		= 34,
		.vburst_start_f1 = 9,		    .vburst_end_f1	= 240,
		.vburst_start_f2 = 10,		    .vburst_end_f2	= 240,
		.vburst_start_f3 = 9,		    .vburst_end_f3	= 240,
		.vburst_start_f4 = 10,		    .vburst_end_f4	= 240,

		/* desired 3.5800000 actual 3.5800000 clock 107.52 */
532 533
		.dda1_inc	=    135,
		.dda2_inc	=  20800,	    .dda2_size		=  27456,
534 535 536 537 538 539 540 541 542 543 544 545 546
		.dda3_inc	=      0,	    .dda3_size		=      0,
		.sc_reset	= TV_SC_RESET_EVERY_4,
		.pal_burst	= false,

		.composite_levels = &ntsc_j_levels_composite,
		.composite_color = &ntsc_j_csc_composite,
		.svideo_levels  = &ntsc_j_levels_svideo,
		.svideo_color = &ntsc_j_csc_svideo,

		.filter_table = filter_table,
	},
	{
		.name		= "PAL-M",
547
		.clock		= 108000,
548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574
		.refresh	= 29970,
		.oversample	= TV_OVERSAMPLE_8X,
		.component_only = 0,

		/* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
		.hsync_end	= 64,		  .hblank_end		= 124,
		.hblank_start = 836,	  .htotal		= 857,

		.progressive	= false,	    .trilevel_sync = false,

		.vsync_start_f1	= 6,		    .vsync_start_f2	= 7,
		.vsync_len	= 6,

		.veq_ena	= true,		    .veq_start_f1    	= 0,
		.veq_start_f2	= 1,		    .veq_len		= 18,

		.vi_end_f1	= 20,		    .vi_end_f2		= 21,
		.nbr_end	= 240,

		.burst_ena	= true,
		.hburst_start	= 72,		    .hburst_len		= 34,
		.vburst_start_f1 = 9,		    .vburst_end_f1	= 240,
		.vburst_start_f2 = 10,		    .vburst_end_f2	= 240,
		.vburst_start_f3 = 9,		    .vburst_end_f3	= 240,
		.vburst_start_f4 = 10,		    .vburst_end_f4	= 240,

		/* desired 3.5800000 actual 3.5800000 clock 107.52 */
575 576
		.dda1_inc	=    135,
		.dda2_inc	=  16704,	    .dda2_size		=  27456,
577
		.dda3_inc	=      0,	    .dda3_size		=      0,
578 579
		.sc_reset	= TV_SC_RESET_EVERY_8,
		.pal_burst  = true,
580 581 582 583 584 585 586 587 588 589 590

		.composite_levels = &pal_m_levels_composite,
		.composite_color = &pal_m_csc_composite,
		.svideo_levels  = &pal_m_levels_svideo,
		.svideo_color = &pal_m_csc_svideo,

		.filter_table = filter_table,
	},
	{
		/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
		.name	    = "PAL-N",
591
		.clock		= 108000,
592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619
		.refresh	= 25000,
		.oversample	= TV_OVERSAMPLE_8X,
		.component_only = 0,

		.hsync_end	= 64,		    .hblank_end		= 128,
		.hblank_start = 844,	    .htotal		= 863,

		.progressive  = false,    .trilevel_sync = false,


		.vsync_start_f1	= 6,	   .vsync_start_f2	= 7,
		.vsync_len	= 6,

		.veq_ena	= true,		    .veq_start_f1    	= 0,
		.veq_start_f2	= 1,		    .veq_len		= 18,

		.vi_end_f1	= 24,		    .vi_end_f2		= 25,
		.nbr_end	= 286,

		.burst_ena	= true,
		.hburst_start = 73,	    	    .hburst_len		= 34,
		.vburst_start_f1 = 8,	    .vburst_end_f1	= 285,
		.vburst_start_f2 = 8,	    .vburst_end_f2	= 286,
		.vburst_start_f3 = 9,	    .vburst_end_f3	= 286,
		.vburst_start_f4 = 9,	    .vburst_end_f4	= 285,


		/* desired 4.4336180 actual 4.4336180 clock 107.52 */
620 621 622
		.dda1_inc       =    135,
		.dda2_inc       =  23578,       .dda2_size      =  27648,
		.dda3_inc       =    134,       .dda3_size      =    625,
623 624 625 626 627 628 629 630 631 632 633 634 635
		.sc_reset   = TV_SC_RESET_EVERY_8,
		.pal_burst  = true,

		.composite_levels = &pal_n_levels_composite,
		.composite_color = &pal_n_csc_composite,
		.svideo_levels  = &pal_n_levels_svideo,
		.svideo_color = &pal_n_csc_svideo,

		.filter_table = filter_table,
	},
	{
		/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
		.name	    = "PAL",
636
		.clock		= 108000,
637 638 639 640
		.refresh	= 25000,
		.oversample	= TV_OVERSAMPLE_8X,
		.component_only = 0,

641
		.hsync_end	= 64,		    .hblank_end		= 142,
642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663
		.hblank_start	= 844,	    .htotal		= 863,

		.progressive	= false,    .trilevel_sync = false,

		.vsync_start_f1	= 5,	    .vsync_start_f2	= 6,
		.vsync_len	= 5,

		.veq_ena	= true,		    .veq_start_f1    	= 0,
		.veq_start_f2	= 1,	    .veq_len		= 15,

		.vi_end_f1	= 24,		    .vi_end_f2		= 25,
		.nbr_end	= 286,

		.burst_ena	= true,
		.hburst_start	= 73,		    .hburst_len		= 32,
		.vburst_start_f1 = 8,		    .vburst_end_f1	= 285,
		.vburst_start_f2 = 8,		    .vburst_end_f2	= 286,
		.vburst_start_f3 = 9,		    .vburst_end_f3	= 286,
		.vburst_start_f4 = 9,		    .vburst_end_f4	= 285,

		/* desired 4.4336180 actual 4.4336180 clock 107.52 */
		.dda1_inc       =    168,
664 665
		.dda2_inc       =   4122,       .dda2_size      =  27648,
		.dda3_inc       =     67,       .dda3_size      =    625,
666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693
		.sc_reset   = TV_SC_RESET_EVERY_8,
		.pal_burst  = true,

		.composite_levels = &pal_levels_composite,
		.composite_color = &pal_csc_composite,
		.svideo_levels  = &pal_levels_svideo,
		.svideo_color = &pal_csc_svideo,

		.filter_table = filter_table,
	},
	{
		.name       = "480p@59.94Hz",
		.clock 	= 107520,
		.refresh	= 59940,
		.oversample     = TV_OVERSAMPLE_4X,
		.component_only = 1,

		.hsync_end      = 64,               .hblank_end         = 122,
		.hblank_start   = 842,              .htotal             = 857,

		.progressive    = true,.trilevel_sync = false,

		.vsync_start_f1 = 12,               .vsync_start_f2     = 12,
		.vsync_len      = 12,

		.veq_ena        = false,

		.vi_end_f1      = 44,               .vi_end_f2          = 44,
694
		.nbr_end        = 479,
695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "480p@60Hz",
		.clock 	= 107520,
		.refresh	= 60000,
		.oversample     = TV_OVERSAMPLE_4X,
		.component_only = 1,

		.hsync_end      = 64,               .hblank_end         = 122,
		.hblank_start   = 842,              .htotal             = 856,

		.progressive    = true,.trilevel_sync = false,

		.vsync_start_f1 = 12,               .vsync_start_f2     = 12,
		.vsync_len      = 12,

		.veq_ena        = false,

		.vi_end_f1      = 44,               .vi_end_f2          = 44,
718
		.nbr_end        = 479,
719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "576p",
		.clock 	= 107520,
		.refresh	= 50000,
		.oversample     = TV_OVERSAMPLE_4X,
		.component_only = 1,

		.hsync_end      = 64,               .hblank_end         = 139,
		.hblank_start   = 859,              .htotal             = 863,

		.progressive    = true,		.trilevel_sync = false,

		.vsync_start_f1 = 10,               .vsync_start_f2     = 10,
		.vsync_len      = 10,

		.veq_ena        = false,

		.vi_end_f1      = 48,               .vi_end_f2          = 48,
		.nbr_end        = 575,

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "720p@60Hz",
		.clock		= 148800,
		.refresh	= 60000,
		.oversample     = TV_OVERSAMPLE_2X,
		.component_only = 1,

		.hsync_end      = 80,               .hblank_end         = 300,
		.hblank_start   = 1580,             .htotal             = 1649,

		.progressive    = true, 	    .trilevel_sync = true,

		.vsync_start_f1 = 10,               .vsync_start_f2     = 10,
		.vsync_len      = 10,

		.veq_ena        = false,

		.vi_end_f1      = 29,               .vi_end_f2          = 29,
		.nbr_end        = 719,

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "720p@59.94Hz",
		.clock		= 148800,
		.refresh	= 59940,
		.oversample     = TV_OVERSAMPLE_2X,
		.component_only = 1,

		.hsync_end      = 80,               .hblank_end         = 300,
		.hblank_start   = 1580,             .htotal             = 1651,

		.progressive    = true, 	    .trilevel_sync = true,

		.vsync_start_f1 = 10,               .vsync_start_f2     = 10,
		.vsync_len      = 10,

		.veq_ena        = false,

		.vi_end_f1      = 29,               .vi_end_f2          = 29,
		.nbr_end        = 719,

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "720p@50Hz",
		.clock		= 148800,
		.refresh	= 50000,
		.oversample     = TV_OVERSAMPLE_2X,
		.component_only = 1,

		.hsync_end      = 80,               .hblank_end         = 300,
		.hblank_start   = 1580,             .htotal             = 1979,

		.progressive    = true, 	        .trilevel_sync = true,

		.vsync_start_f1 = 10,               .vsync_start_f2     = 10,
		.vsync_len      = 10,

		.veq_ena        = false,

		.vi_end_f1      = 29,               .vi_end_f2          = 29,
		.nbr_end        = 719,

		.burst_ena      = false,

		.filter_table = filter_table,
		.max_srcw = 800
	},
	{
		.name       = "1080i@50Hz",
		.clock		= 148800,
		.refresh	= 25000,
		.oversample     = TV_OVERSAMPLE_2X,
		.component_only = 1,

		.hsync_end      = 88,               .hblank_end         = 235,
		.hblank_start   = 2155,             .htotal             = 2639,

		.progressive    = false, 	    .trilevel_sync = true,

		.vsync_start_f1 = 4,              .vsync_start_f2     = 5,
		.vsync_len      = 10,

		.veq_ena	= true,		    .veq_start_f1    	= 4,
		.veq_start_f2   = 4,	    .veq_len		= 10,


		.vi_end_f1      = 21,           .vi_end_f2          = 22,
		.nbr_end        = 539,

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "1080i@60Hz",
		.clock		= 148800,
		.refresh	= 30000,
		.oversample     = TV_OVERSAMPLE_2X,
		.component_only = 1,

		.hsync_end      = 88,               .hblank_end         = 235,
		.hblank_start   = 2155,             .htotal             = 2199,

		.progressive    = false, 	    .trilevel_sync = true,

		.vsync_start_f1 = 4,               .vsync_start_f2     = 5,
		.vsync_len      = 10,

		.veq_ena	= true,		    .veq_start_f1    	= 4,
		.veq_start_f2	= 4,		    .veq_len		= 10,


		.vi_end_f1      = 21,               .vi_end_f2          = 22,
		.nbr_end        = 539,

		.burst_ena      = false,

		.filter_table = filter_table,
	},
	{
		.name       = "1080i@59.94Hz",
		.clock		= 148800,
		.refresh	= 29970,
		.oversample     = TV_OVERSAMPLE_2X,
		.component_only = 1,

		.hsync_end      = 88,               .hblank_end         = 235,
881
		.hblank_start   = 2155,             .htotal             = 2201,
882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900

		.progressive    = false, 	    .trilevel_sync = true,

		.vsync_start_f1 = 4,            .vsync_start_f2    = 5,
		.vsync_len      = 10,

		.veq_ena	= true,		    .veq_start_f1	= 4,
		.veq_start_f2 = 4,	    	    .veq_len = 10,


		.vi_end_f1      = 21,           .vi_end_f2         	= 22,
		.nbr_end        = 539,

		.burst_ena      = false,

		.filter_table = filter_table,
	},
};

901 902
static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
{
903
	return container_of(encoder, struct intel_tv, base.base);
904 905
}

906 907 908 909 910 911 912
static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_tv,
			    base);
}

913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931
static void
intel_tv_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	switch(mode) {
	case DRM_MODE_DPMS_ON:
		I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
		break;
	}
}

static const struct tv_mode *
932
intel_tv_mode_lookup(const char *tv_format)
933 934 935 936 937 938 939 940 941 942 943 944 945
{
	int i;

	for (i = 0; i < sizeof(tv_modes) / sizeof (tv_modes[0]); i++) {
		const struct tv_mode *tv_mode = &tv_modes[i];

		if (!strcmp(tv_format, tv_mode->name))
			return tv_mode;
	}
	return NULL;
}

static const struct tv_mode *
946
intel_tv_mode_find(struct intel_tv *intel_tv)
947
{
948
	return intel_tv_mode_lookup(intel_tv->tv_format);
949 950 951
}

static enum drm_mode_status
952 953
intel_tv_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
954
{
955
	struct intel_tv *intel_tv = intel_attached_tv(connector);
956
	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
957 958

	/* Ensure TV refresh is close to desired refresh */
959 960
	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
				< 1000)
961
		return MODE_OK;
962

963 964 965 966 967 968 969 970 971 972
	return MODE_CLOCK_RANGE;
}


static bool
intel_tv_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
		    struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_mode_config *drm_config = &dev->mode_config;
973 974
	struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998
	struct drm_encoder *other_encoder;

	if (!tv_mode)
		return false;

	/* FIXME: lock encoder list */
	list_for_each_entry(other_encoder, &drm_config->encoder_list, head) {
		if (other_encoder != encoder &&
		    other_encoder->crtc == encoder->crtc)
			return false;
	}

	adjusted_mode->clock = tv_mode->clock;
	return true;
}

static void
intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
999 1000
	struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
	u32 tv_ctl;
	u32 hctl1, hctl2, hctl3;
	u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
	u32 scctl1, scctl2, scctl3;
	int i, j;
	const struct video_levels *video_levels;
	const struct color_conversion *color_conversion;
	bool burst_ena;

	if (!tv_mode)
		return;	/* can't happen (mode_prepare prevents this) */

1013 1014
	tv_ctl = I915_READ(TV_CTL);
	tv_ctl &= TV_CTL_SAVE;
1015

1016
	switch (intel_tv->type) {
1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
	default:
	case DRM_MODE_CONNECTOR_Unknown:
	case DRM_MODE_CONNECTOR_Composite:
		tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
		video_levels = tv_mode->composite_levels;
		color_conversion = tv_mode->composite_color;
		burst_ena = tv_mode->burst_ena;
		break;
	case DRM_MODE_CONNECTOR_Component:
		tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
		video_levels = &component_levels;
		if (tv_mode->burst_ena)
			color_conversion = &sdtv_csc_yprpb;
		else
			color_conversion = &hdtv_csc_yprpb;
		burst_ena = false;
		break;
	case DRM_MODE_CONNECTOR_SVIDEO:
		tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
		video_levels = tv_mode->svideo_levels;
		color_conversion = tv_mode->svideo_color;
		burst_ena = tv_mode->burst_ena;
		break;
	}
	hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
		(tv_mode->htotal << TV_HTOTAL_SHIFT);

	hctl2 = (tv_mode->hburst_start << 16) |
		(tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);

	if (burst_ena)
		hctl2 |= TV_BURST_ENA;

	hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
		(tv_mode->hblank_end << TV_HBLANK_END_SHIFT);

	vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
		(tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
		(tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);

	vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
		(tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
		(tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);

	vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
		(tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
		(tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);

	if (tv_mode->veq_ena)
		vctl3 |= TV_EQUAL_ENA;

	vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
		(tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);

	vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
		(tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);

	vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
		(tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);

	vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
		(tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);

	if (intel_crtc->pipe == 1)
		tv_ctl |= TV_ENC_PIPEB_SELECT;
	tv_ctl |= tv_mode->oversample;

	if (tv_mode->progressive)
		tv_ctl |= TV_PROGRESSIVE;
	if (tv_mode->trilevel_sync)
		tv_ctl |= TV_TRILEVEL_SYNC;
	if (tv_mode->pal_burst)
		tv_ctl |= TV_PAL_BURST;
1090

1091
	scctl1 = 0;
1092
	if (tv_mode->dda1_inc)
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		scctl1 |= TV_SC_DDA1_EN;
	if (tv_mode->dda2_inc)
		scctl1 |= TV_SC_DDA2_EN;
	if (tv_mode->dda3_inc)
		scctl1 |= TV_SC_DDA3_EN;
	scctl1 |= tv_mode->sc_reset;
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	if (video_levels)
		scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
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	scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;

	scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
		tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;

	scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
		tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;

	/* Enable two fixes for the chips that need them. */
	if (dev->pci_device < 0x2772)
		tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;

	I915_WRITE(TV_H_CTL_1, hctl1);
	I915_WRITE(TV_H_CTL_2, hctl2);
	I915_WRITE(TV_H_CTL_3, hctl3);
	I915_WRITE(TV_V_CTL_1, vctl1);
	I915_WRITE(TV_V_CTL_2, vctl2);
	I915_WRITE(TV_V_CTL_3, vctl3);
	I915_WRITE(TV_V_CTL_4, vctl4);
	I915_WRITE(TV_V_CTL_5, vctl5);
	I915_WRITE(TV_V_CTL_6, vctl6);
	I915_WRITE(TV_V_CTL_7, vctl7);
	I915_WRITE(TV_SC_CTL_1, scctl1);
	I915_WRITE(TV_SC_CTL_2, scctl2);
	I915_WRITE(TV_SC_CTL_3, scctl3);

	if (color_conversion) {
		I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
			   color_conversion->gy);
		I915_WRITE(TV_CSC_Y2,(color_conversion->by << 16) |
			   color_conversion->ay);
		I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
			   color_conversion->gu);
		I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
			   color_conversion->au);
		I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
			   color_conversion->gv);
		I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
			   color_conversion->av);
	}

1142
	if (INTEL_INFO(dev)->gen >= 4)
1143 1144 1145 1146
		I915_WRITE(TV_CLR_KNOBS, 0x00404000);
	else
		I915_WRITE(TV_CLR_KNOBS, 0x00606000);

1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
	if (video_levels)
		I915_WRITE(TV_CLR_LEVEL,
			   ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
			    (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
	{
		int pipeconf_reg = (intel_crtc->pipe == 0) ?
			PIPEACONF : PIPEBCONF;
		int dspcntr_reg = (intel_crtc->plane == 0) ?
			DSPACNTR : DSPBCNTR;
		int pipeconf = I915_READ(pipeconf_reg);
		int dspcntr = I915_READ(dspcntr_reg);
		int dspbase_reg = (intel_crtc->plane == 0) ?
			DSPAADDR : DSPBADDR;
		int xpos = 0x0, ypos = 0x0;
		unsigned int xsize, ysize;
		/* Pipe must be off here */
		I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
		/* Flush the plane changes */
		I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));

		/* Wait for vblank for the disable to take effect */
1168
		if (IS_GEN2(dev))
1169
			intel_wait_for_vblank(dev, intel_crtc->pipe);
1170

1171
		I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
1172
		/* Wait for vblank for the disable to take effect. */
1173
		intel_wait_for_vblank_off(dev, intel_crtc->pipe);
1174 1175 1176 1177 1178 1179 1180 1181 1182

		/* Filter ctl must be set before TV_WIN_SIZE */
		I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
		xsize = tv_mode->hblank_start - tv_mode->hblank_end;
		if (tv_mode->progressive)
			ysize = tv_mode->nbr_end + 1;
		else
			ysize = 2*tv_mode->nbr_end + 1;

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		xpos += intel_tv->margin[TV_MARGIN_LEFT];
		ypos += intel_tv->margin[TV_MARGIN_TOP];
		xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
			  intel_tv->margin[TV_MARGIN_RIGHT]);
		ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
			  intel_tv->margin[TV_MARGIN_BOTTOM]);
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		I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
		I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);

		I915_WRITE(pipeconf_reg, pipeconf);
		I915_WRITE(dspcntr_reg, dspcntr);
		/* Flush the plane changes */
		I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
	}

	j = 0;
	for (i = 0; i < 60; i++)
		I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
	for (i = 0; i < 60; i++)
		I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
	for (i = 0; i < 43; i++)
		I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
	for (i = 0; i < 43; i++)
		I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1207
	I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
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	I915_WRITE(TV_CTL, tv_ctl);
}

static const struct drm_display_mode reported_modes[] = {
	{
		.name = "NTSC 480i",
		.clock = 107520,
		.hdisplay = 1280,
		.hsync_start = 1368,
		.hsync_end = 1496,
		.htotal = 1712,

		.vdisplay = 1024,
		.vsync_start = 1027,
		.vsync_end = 1034,
		.vtotal = 1104,
		.type = DRM_MODE_TYPE_DRIVER,
	},
};

/**
 * Detects TV presence by checking for load.
 *
 * Requires that the current pipe's DPLL is active.

 * \return true if TV is connected.
 * \return false if TV is disconnected.
 */
static int
1237
intel_tv_detect_type (struct intel_tv *intel_tv)
1238
{
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	struct drm_encoder *encoder = &intel_tv->base.base;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;
	u32 tv_ctl, save_tv_ctl;
	u32 tv_dac, save_tv_dac;
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	int type;
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	/* Disable TV interrupts around load detect or we'll recurse */
	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	i915_disable_pipestat(dev_priv, 0, PIPE_HOTPLUG_INTERRUPT_ENABLE |
			      PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);

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	save_tv_dac = tv_dac = I915_READ(TV_DAC);
	save_tv_ctl = tv_ctl = I915_READ(TV_CTL);

	/* Poll for TV detection */
	tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
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	tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
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	tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
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	tv_dac |= (TVDAC_STATE_CHG_EN |
		   TVDAC_A_SENSE_CTL |
		   TVDAC_B_SENSE_CTL |
		   TVDAC_C_SENSE_CTL |
		   DAC_CTL_OVERRIDE |
		   DAC_A_0_7_V |
		   DAC_B_0_7_V |
		   DAC_C_0_7_V);
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1270 1271
	I915_WRITE(TV_CTL, tv_ctl);
	I915_WRITE(TV_DAC, tv_dac);
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	POSTING_READ(TV_DAC);

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	intel_wait_for_vblank(intel_tv->base.base.dev,
			      to_intel_crtc(intel_tv->base.base.crtc)->pipe);

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	type = -1;
	if (wait_for((tv_dac = I915_READ(TV_DAC)) & TVDAC_STATE_CHG, 20) == 0) {
1279
		DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
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		/*
		 *  A B C
		 *  0 1 1 Composite
		 *  1 0 X svideo
		 *  0 0 0 Component
		 */
		if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
			DRM_DEBUG_KMS("Detected Composite TV connection\n");
			type = DRM_MODE_CONNECTOR_Composite;
		} else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
			DRM_DEBUG_KMS("Detected S-Video TV connection\n");
			type = DRM_MODE_CONNECTOR_SVIDEO;
		} else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
			DRM_DEBUG_KMS("Detected Component TV connection\n");
			type = DRM_MODE_CONNECTOR_Component;
		} else {
1296
			DRM_DEBUG_KMS("Unrecognised TV connection\n");
1297
		}
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	}

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	I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
	I915_WRITE(TV_CTL, save_tv_ctl);

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	/* Restore interrupt config */
	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	i915_enable_pipestat(dev_priv, 0, PIPE_HOTPLUG_INTERRUPT_ENABLE |
			     PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);

	return type;
}

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/*
 * Here we set accurate tv format according to connector type
 * i.e Component TV should not be assigned by NTSC or PAL
 */
static void intel_tv_find_better_format(struct drm_connector *connector)
{
1318
	struct intel_tv *intel_tv = intel_attached_tv(connector);
1319
	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
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	int i;

1322
	if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
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		tv_mode->component_only)
		return;


	for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
		tv_mode = tv_modes + i;

1330
		if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
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			tv_mode->component_only)
			break;
	}

1335
	intel_tv->tv_format = tv_mode->name;
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	drm_connector_property_set_value(connector,
		connector->dev->mode_config.tv_mode_property, i);
}

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/**
 * Detect the TV connection.
 *
 * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
 * we have a pipe programmed in order to probe the TV.
 */
static enum drm_connector_status
1347
intel_tv_detect(struct drm_connector *connector, bool force)
1348 1349
{
	struct drm_display_mode mode;
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	struct intel_tv *intel_tv = intel_attached_tv(connector);
1351
	int type;
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	mode = reported_modes[0];
	drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V);

1356
	if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) {
1357
		type = intel_tv_detect_type(intel_tv);
1358
	} else if (force) {
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		struct drm_crtc *crtc;
		int dpms_mode;

		crtc = intel_get_load_detect_pipe(&intel_tv->base, connector,
1363
						  &mode, &dpms_mode);
1364
		if (crtc) {
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			type = intel_tv_detect_type(intel_tv);
			intel_release_load_detect_pipe(&intel_tv->base, connector,
1367
						       dpms_mode);
1368
		} else
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			return connector_status_unknown;
	} else
		return connector->status;
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Zhenyu Wang committed
1372

1373 1374 1375
	if (type < 0)
		return connector_status_disconnected;

1376
	intel_tv_find_better_format(connector);
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	return connector_status_connected;
}

1380 1381
static const struct input_res {
	const char *name;
1382
	int w, h;
1383
} input_res_table[] = {
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	{"640x480", 640, 480},
	{"800x600", 800, 600},
	{"1024x768", 1024, 768},
	{"1280x1024", 1280, 1024},
	{"848x480", 848, 480},
	{"1280x720", 1280, 720},
	{"1920x1080", 1920, 1080},
};

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/*
 * Chose preferred mode  according to line number of TV format
 */
static void
intel_tv_chose_preferred_modes(struct drm_connector *connector,
			       struct drm_display_mode *mode_ptr)
{
1400
	struct intel_tv *intel_tv = intel_attached_tv(connector);
1401
	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
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	if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
		mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
	else if (tv_mode->nbr_end > 480) {
		if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
			if (mode_ptr->vdisplay == 720)
				mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
		} else if (mode_ptr->vdisplay == 1080)
				mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
	}
}

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/**
 * Stub get_modes function.
 *
 * This should probably return a set of fixed modes, unless we can figure out
 * how to probe modes off of TV connections.
 */

static int
intel_tv_get_modes(struct drm_connector *connector)
{
	struct drm_display_mode *mode_ptr;
1425
	struct intel_tv *intel_tv = intel_attached_tv(connector);
1426
	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1427 1428
	int j, count = 0;
	u64 tmp;
1429

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Kulikov Vasiliy committed
1430
	for (j = 0; j < ARRAY_SIZE(input_res_table);
1431
	     j++) {
1432
		const struct input_res *input = &input_res_table[j];
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		unsigned int hactive_s = input->w;
		unsigned int vactive_s = input->h;

		if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
			continue;

		if (input->w > 1024 && (!tv_mode->progressive
					&& !tv_mode->component_only))
			continue;

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		mode_ptr = drm_mode_create(connector->dev);
		if (!mode_ptr)
			continue;
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		strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);

		mode_ptr->hdisplay = hactive_s;
		mode_ptr->hsync_start = hactive_s + 1;
		mode_ptr->hsync_end = hactive_s + 64;
		if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
			mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
		mode_ptr->htotal = hactive_s + 96;

		mode_ptr->vdisplay = vactive_s;
		mode_ptr->vsync_start = vactive_s + 1;
		mode_ptr->vsync_end = vactive_s + 32;
		if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
			mode_ptr->vsync_end = mode_ptr->vsync_start  + 1;
		mode_ptr->vtotal = vactive_s + 33;

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		tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
		tmp *= mode_ptr->htotal;
		tmp = div_u64(tmp, 1000000);
		mode_ptr->clock = (int) tmp;
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		mode_ptr->type = DRM_MODE_TYPE_DRIVER;
1468
		intel_tv_chose_preferred_modes(connector, mode_ptr);
1469
		drm_mode_probed_add(connector, mode_ptr);
1470
		count++;
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	}

1473
	return count;
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}

static void
intel_tv_destroy (struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
1481
	kfree(connector);
1482 1483 1484 1485 1486 1487 1488 1489
}


static int
intel_tv_set_property(struct drm_connector *connector, struct drm_property *property,
		      uint64_t val)
{
	struct drm_device *dev = connector->dev;
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	struct intel_tv *intel_tv = intel_attached_tv(connector);
	struct drm_crtc *crtc = intel_tv->base.base.crtc;
1492
	int ret = 0;
1493
	bool changed = false;
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	ret = drm_connector_property_set_value(connector, property, val);
	if (ret < 0)
		goto out;

1499
	if (property == dev->mode_config.tv_left_margin_property &&
1500 1501
		intel_tv->margin[TV_MARGIN_LEFT] != val) {
		intel_tv->margin[TV_MARGIN_LEFT] = val;
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		changed = true;
	} else if (property == dev->mode_config.tv_right_margin_property &&
1504 1505
		intel_tv->margin[TV_MARGIN_RIGHT] != val) {
		intel_tv->margin[TV_MARGIN_RIGHT] = val;
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		changed = true;
	} else if (property == dev->mode_config.tv_top_margin_property &&
1508 1509
		intel_tv->margin[TV_MARGIN_TOP] != val) {
		intel_tv->margin[TV_MARGIN_TOP] = val;
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		changed = true;
	} else if (property == dev->mode_config.tv_bottom_margin_property &&
1512 1513
		intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
		intel_tv->margin[TV_MARGIN_BOTTOM] = val;
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		changed = true;
	} else if (property == dev->mode_config.tv_mode_property) {
1516
		if (val >= ARRAY_SIZE(tv_modes)) {
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			ret = -EINVAL;
			goto out;
		}
1520
		if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
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			goto out;

1523
		intel_tv->tv_format = tv_modes[val].name;
1524
		changed = true;
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	} else {
		ret = -EINVAL;
		goto out;
	}

1530 1531 1532
	if (changed && crtc)
		drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
				crtc->y, crtc->fb);
1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
out:
	return ret;
}

static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = {
	.dpms = intel_tv_dpms,
	.mode_fixup = intel_tv_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_tv_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_tv_connector_funcs = {
1546
	.dpms = drm_helper_connector_dpms,
1547 1548 1549 1550 1551 1552 1553 1554 1555
	.detect = intel_tv_detect,
	.destroy = intel_tv_destroy,
	.set_property = intel_tv_set_property,
	.fill_modes = drm_helper_probe_single_connector_modes,
};

static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
	.mode_valid = intel_tv_mode_valid,
	.get_modes = intel_tv_get_modes,
1556
	.best_encoder = intel_best_encoder,
1557 1558 1559
};

static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1560
	.destroy = intel_encoder_destroy,
1561 1562
};

1563 1564 1565 1566 1567 1568 1569
/*
 * Enumerate the child dev array parsed from VBT to check whether
 * the integrated TV is present.
 * If it is present, return 1.
 * If it is not present, return false.
 * If no child dev is parsed from VBT, it assumes that the TV is present.
 */
1570
static int tv_is_present_in_vbt(struct drm_device *dev)
1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct child_device_config *p_child;
	int i, ret;

	if (!dev_priv->child_dev_num)
		return 1;

	ret = 0;
	for (i = 0; i < dev_priv->child_dev_num; i++) {
		p_child = dev_priv->child_dev + i;
		/*
		 * If the device type is not TV, continue.
		 */
		if (p_child->device_type != DEVICE_TYPE_INT_TV &&
			p_child->device_type != DEVICE_TYPE_TV)
			continue;
		/* Only when the addin_offset is non-zero, it is regarded
		 * as present.
		 */
		if (p_child->addin_offset) {
			ret = 1;
			break;
		}
	}
	return ret;
}
1598 1599 1600 1601 1602 1603

void
intel_tv_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
1604
	struct intel_tv *intel_tv;
1605
	struct intel_encoder *intel_encoder;
1606
	struct intel_connector *intel_connector;
1607
	u32 tv_dac_on, tv_dac_off, save_tv_dac;
1608
	char *tv_format_names[ARRAY_SIZE(tv_modes)];
1609 1610 1611 1612 1613
	int i, initial_mode = 0;

	if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
		return;

1614 1615 1616 1617
	if (!tv_is_present_in_vbt(dev)) {
		DRM_DEBUG_KMS("Integrated TV is not present.\n");
		return;
	}
1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644
	/* Even if we have an encoder we may not have a connector */
	if (!dev_priv->int_tv_support)
		return;

	/*
	 * Sanity check the TV output by checking to see if the
	 * DAC register holds a value
	 */
	save_tv_dac = I915_READ(TV_DAC);

	I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
	tv_dac_on = I915_READ(TV_DAC);

	I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
	tv_dac_off = I915_READ(TV_DAC);

	I915_WRITE(TV_DAC, save_tv_dac);

	/*
	 * If the register does not hold the state change enable
	 * bit, (either as a 0 or a 1), assume it doesn't really
	 * exist
	 */
	if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
	    (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
		return;

1645 1646
	intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
	if (!intel_tv) {
1647 1648
		return;
	}
1649

1650 1651
	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
1652
		kfree(intel_tv);
1653 1654 1655
		return;
	}

1656
	intel_encoder = &intel_tv->base;
1657
	connector = &intel_connector->base;
1658 1659 1660 1661

	drm_connector_init(dev, connector, &intel_tv_connector_funcs,
			   DRM_MODE_CONNECTOR_SVIDEO);

1662
	drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1663 1664
			 DRM_MODE_ENCODER_TVDAC);

1665
	intel_connector_attach_encoder(intel_connector, intel_encoder);
1666 1667 1668
	intel_encoder->type = INTEL_OUTPUT_TVOUT;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT);
1669 1670
	intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
	intel_encoder->base.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1671
	intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1672 1673

	/* BIOS margin values */
1674 1675 1676 1677
	intel_tv->margin[TV_MARGIN_LEFT] = 54;
	intel_tv->margin[TV_MARGIN_TOP] = 36;
	intel_tv->margin[TV_MARGIN_RIGHT] = 46;
	intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
1678

1679
	intel_tv->tv_format = tv_modes[initial_mode].name;
1680

1681
	drm_encoder_helper_add(&intel_encoder->base, &intel_tv_helper_funcs);
1682 1683 1684 1685 1686
	drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
	connector->interlace_allowed = false;
	connector->doublescan_allowed = false;

	/* Create TV properties then attach current values */
1687
	for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
1688 1689 1690 1691
		tv_format_names[i] = (char *)tv_modes[i].name;
	drm_mode_create_tv_properties(dev,
				      ARRAY_SIZE(tv_modes),
				      tv_format_names);
1692 1693 1694 1695 1696

	drm_connector_attach_property(connector, dev->mode_config.tv_mode_property,
				   initial_mode);
	drm_connector_attach_property(connector,
				   dev->mode_config.tv_left_margin_property,
1697
				   intel_tv->margin[TV_MARGIN_LEFT]);
1698 1699
	drm_connector_attach_property(connector,
				   dev->mode_config.tv_top_margin_property,
1700
				   intel_tv->margin[TV_MARGIN_TOP]);
1701 1702
	drm_connector_attach_property(connector,
				   dev->mode_config.tv_right_margin_property,
1703
				   intel_tv->margin[TV_MARGIN_RIGHT]);
1704 1705
	drm_connector_attach_property(connector,
				   dev->mode_config.tv_bottom_margin_property,
1706
				   intel_tv->margin[TV_MARGIN_BOTTOM]);
1707 1708
	drm_sysfs_connector_add(connector);
}