intel_hdcp.c 60.8 KB
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/* SPDX-License-Identifier: MIT */
/*
 * Copyright (C) 2017 Google, Inc.
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 * Copyright _ 2017-2019, Intel Corporation.
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 *
 * Authors:
 * Sean Paul <seanpaul@chromium.org>
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 * Ramalingam C <ramalingam.c@intel.com>
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 */

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#include <linux/component.h>
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#include <linux/i2c.h>
#include <linux/random.h>

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#include <drm/drm_hdcp.h>
#include <drm/i915_component.h>

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#include "i915_reg.h"
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#include "intel_display_power.h"
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#include "intel_display_types.h"
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#include "intel_hdcp.h"
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#include "intel_sideband.h"
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#include "intel_connector.h"
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#define KEY_LOAD_TRIES	5
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#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS	50
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#define HDCP2_LC_RETRY_CNT			3
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static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
	int i, ones = 0;
	/* KSV has 20 1's and 20 0's */
	for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
		ones += hweight8(ksv[i]);
	if (ones != 20)
		return false;

	return true;
}

static
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int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port,
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			       const struct intel_hdcp_shim *shim, u8 *bksv)
{
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	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
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	int ret, i, tries = 2;

	/* HDCP spec states that we must retry the bksv if it is invalid */
	for (i = 0; i < tries; i++) {
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		ret = shim->read_bksv(dig_port, bksv);
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		if (ret)
			return ret;
		if (intel_hdcp_is_ksv_valid(bksv))
			break;
	}
	if (i == tries) {
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		drm_dbg_kms(&i915->drm, "Bksv is invalid\n");
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		return -ENODEV;
	}

	return 0;
}

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/* Is HDCP1.4 capable on Platform and Sink */
bool intel_hdcp_capable(struct intel_connector *connector)
{
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	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
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	const struct intel_hdcp_shim *shim = connector->hdcp.shim;
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	bool capable = false;
	u8 bksv[5];

	if (!shim)
		return capable;

	if (shim->hdcp_capable) {
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		shim->hdcp_capable(dig_port, &capable);
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	} else {
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		if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv))
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			capable = true;
	}

	return capable;
}

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/* Is HDCP2.2 capable on Platform and Sink */
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bool intel_hdcp2_capable(struct intel_connector *connector)
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{
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	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
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	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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	struct intel_hdcp *hdcp = &connector->hdcp;
	bool capable = false;

	/* I915 support for HDCP2.2 */
	if (!hdcp->hdcp2_supported)
		return false;

	/* MEI interface is solid */
	mutex_lock(&dev_priv->hdcp_comp_mutex);
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	if (!dev_priv->hdcp_comp_added ||  !dev_priv->hdcp_master) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return false;
	}
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	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	/* Sink's capability for HDCP2.2 */
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	hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
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	return capable;
}

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static bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
			      enum transcoder cpu_transcoder, enum port port)
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{
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	return intel_de_read(dev_priv,
	                     HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
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	       HDCP_STATUS_ENC;
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}

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static bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
			       enum transcoder cpu_transcoder, enum port port)
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{
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	return intel_de_read(dev_priv,
	                     HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
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	       LINK_ENCRYPTION_STATUS;
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}

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static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port,
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				    const struct intel_hdcp_shim *shim)
{
	int ret, read_ret;
	bool ksv_ready;

	/* Poll for ksv list ready (spec says max time allowed is 5s) */
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	ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port,
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							 &ksv_ready),
			 read_ret || ksv_ready, 5 * 1000 * 1000, 1000,
			 100 * 1000);
	if (ret)
		return ret;
	if (read_ret)
		return read_ret;
	if (!ksv_ready)
		return -ETIMEDOUT;

	return 0;
}

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static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
{
	enum i915_power_well_id id;
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	intel_wakeref_t wakeref;
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	bool enabled = false;

	/*
	 * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
	 * On all BXT+, SW can load the keys only when the PW#1 is turned on.
	 */
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		id = HSW_DISP_PW_GLOBAL;
	else
		id = SKL_DISP_PW_1;

	/* PG1 (power well #1) needs to be enabled */
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	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
		enabled = intel_display_power_well_is_enabled(dev_priv, id);
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	/*
	 * Another req for hdcp key loadability is enabled state of pll for
	 * cdclk. Without active crtc we wont land here. So we are assuming that
	 * cdclk is already on.
	 */

	return enabled;
}

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static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
{
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	intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
	intel_de_write(dev_priv, HDCP_KEY_STATUS,
		       HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
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}

static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
{
	int ret;
	u32 val;

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	val = intel_de_read(dev_priv, HDCP_KEY_STATUS);
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	if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS))
		return 0;

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	/*
	 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes
	 * out of reset. So if Key is not already loaded, its an error state.
	 */
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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		if (!(intel_de_read(dev_priv, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
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			return -ENXIO;

	/*
	 * Initiate loading the HDCP key from fuses.
	 *
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	 * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9
	 * platforms except BXT and GLK, differ in the key load trigger process
	 * from other platforms. So GEN9_BC uses the GT Driver Mailbox i/f.
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	 */
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	if (IS_GEN9_BC(dev_priv)) {
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		ret = sandybridge_pcode_write(dev_priv,
					      SKL_PCODE_LOAD_HDCP_KEYS, 1);
		if (ret) {
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			drm_err(&dev_priv->drm,
				"Failed to initiate HDCP key load (%d)\n",
				ret);
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			return ret;
		}
	} else {
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		intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
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	}

	/* Wait for the keys to load (500us) */
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	ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS,
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					HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
					10, 1, &val);
	if (ret)
		return ret;
	else if (!(val & HDCP_KEY_LOAD_STATUS))
		return -ENXIO;

	/* Send Aksv over to PCH display for use in authentication */
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	intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
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	return 0;
}

/* Returns updated SHA-1 index */
static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
{
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	intel_de_write(dev_priv, HDCP_SHA_TEXT, sha_text);
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	if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
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		drm_err(&dev_priv->drm, "Timed out waiting for SHA1 ready\n");
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		return -ETIMEDOUT;
	}
	return 0;
}

static
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u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
				enum transcoder cpu_transcoder, enum port port)
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{
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	if (INTEL_GEN(dev_priv) >= 12) {
		switch (cpu_transcoder) {
		case TRANSCODER_A:
			return HDCP_TRANSA_REP_PRESENT |
			       HDCP_TRANSA_SHA1_M0;
		case TRANSCODER_B:
			return HDCP_TRANSB_REP_PRESENT |
			       HDCP_TRANSB_SHA1_M0;
		case TRANSCODER_C:
			return HDCP_TRANSC_REP_PRESENT |
			       HDCP_TRANSC_SHA1_M0;
		case TRANSCODER_D:
			return HDCP_TRANSD_REP_PRESENT |
			       HDCP_TRANSD_SHA1_M0;
		default:
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			drm_err(&dev_priv->drm, "Unknown transcoder %d\n",
				cpu_transcoder);
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			return -EINVAL;
		}
	}

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	switch (port) {
	case PORT_A:
		return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
	case PORT_B:
		return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
	case PORT_C:
		return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
	case PORT_D:
		return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
	case PORT_E:
		return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
	default:
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		drm_err(&dev_priv->drm, "Unknown port %d\n", port);
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		return -EINVAL;
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	}
}

static
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int intel_hdcp_validate_v_prime(struct intel_connector *connector,
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				const struct intel_hdcp_shim *shim,
				u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
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{
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	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
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	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
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	enum port port = dig_port->base.port;
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	u32 vprime, sha_text, sha_leftovers, rep_ctl;
	int ret, i, j, sha_idx;

	/* Process V' values from the receiver */
	for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
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		ret = shim->read_v_prime_part(dig_port, i, &vprime);
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		if (ret)
			return ret;
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		intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime);
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	}

	/*
	 * We need to write the concatenation of all device KSVs, BINFO (DP) ||
	 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte
	 * stream is written via the HDCP_SHA_TEXT register in 32-bit
	 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This
	 * index will keep track of our progress through the 64 bytes as well as
	 * helping us work the 40-bit KSVs through our 32-bit register.
	 *
	 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian
	 */
	sha_idx = 0;
	sha_text = 0;
	sha_leftovers = 0;
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	rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port);
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	intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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	for (i = 0; i < num_downstream; i++) {
		unsigned int sha_empty;
		u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];

		/* Fill up the empty slots in sha_text and write it out */
		sha_empty = sizeof(sha_text) - sha_leftovers;
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		for (j = 0; j < sha_empty; j++) {
			u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8);
			sha_text |= ksv[j] << off;
		}
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		ret = intel_write_sha_text(dev_priv, sha_text);
		if (ret < 0)
			return ret;

		/* Programming guide writes this every 64 bytes */
		sha_idx += sizeof(sha_text);
		if (!(sha_idx % 64))
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			intel_de_write(dev_priv, HDCP_REP_CTL,
				       rep_ctl | HDCP_SHA1_TEXT_32);
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		/* Store the leftover bytes from the ksv in sha_text */
		sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty;
		sha_text = 0;
		for (j = 0; j < sha_leftovers; j++)
			sha_text |= ksv[sha_empty + j] <<
					((sizeof(sha_text) - j - 1) * 8);

		/*
		 * If we still have room in sha_text for more data, continue.
		 * Otherwise, write it out immediately.
		 */
		if (sizeof(sha_text) > sha_leftovers)
			continue;

		ret = intel_write_sha_text(dev_priv, sha_text);
		if (ret < 0)
			return ret;
		sha_leftovers = 0;
		sha_text = 0;
		sha_idx += sizeof(sha_text);
	}

	/*
	 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many
	 * bytes are leftover from the last ksv, we might be able to fit them
	 * all in sha_text (first 2 cases), or we might need to split them up
	 * into 2 writes (last 2 cases).
	 */
	if (sha_leftovers == 0) {
		/* Write 16 bits of text, 16 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_16);
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		ret = intel_write_sha_text(dev_priv,
					   bstatus[0] << 8 | bstatus[1]);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 32 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_0);
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		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 16 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_16);
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		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

	} else if (sha_leftovers == 1) {
		/* Write 24 bits of text, 8 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_24);
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		sha_text |= bstatus[0] << 16 | bstatus[1] << 8;
		/* Only 24-bits of data, must be in the LSB */
		sha_text = (sha_text & 0xffffff00) >> 8;
		ret = intel_write_sha_text(dev_priv, sha_text);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 32 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_0);
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		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 24 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_8);
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		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

	} else if (sha_leftovers == 2) {
		/* Write 32 bits of text */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_32);
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		sha_text |= bstatus[0] << 8 | bstatus[1];
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		ret = intel_write_sha_text(dev_priv, sha_text);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 64 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_0);
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		for (i = 0; i < 2; i++) {
			ret = intel_write_sha_text(dev_priv, 0);
			if (ret < 0)
				return ret;
			sha_idx += sizeof(sha_text);
		}
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		/*
		 * Terminate the SHA-1 stream by hand. For the other leftover
		 * cases this is appended by the hardware.
		 */
		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_32);
		sha_text = DRM_HDCP_SHA1_TERMINATOR << 24;
		ret = intel_write_sha_text(dev_priv, sha_text);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);
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	} else if (sha_leftovers == 3) {
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		/* Write 32 bits of text (filled from LSB) */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_32);
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		sha_text |= bstatus[0];
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		ret = intel_write_sha_text(dev_priv, sha_text);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

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		/* Write 8 bits of text (filled from LSB), 24 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_8);
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		ret = intel_write_sha_text(dev_priv, bstatus[1]);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 32 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_0);
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		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);

		/* Write 8 bits of M0 */
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		intel_de_write(dev_priv, HDCP_REP_CTL,
			       rep_ctl | HDCP_SHA1_TEXT_24);
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		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);
	} else {
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		drm_dbg_kms(&dev_priv->drm, "Invalid number of leftovers %d\n",
			    sha_leftovers);
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		return -EINVAL;
	}

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	intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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	/* Fill up to 64-4 bytes with zeros (leave the last write for length) */
	while ((sha_idx % 64) < (64 - sizeof(sha_text))) {
		ret = intel_write_sha_text(dev_priv, 0);
		if (ret < 0)
			return ret;
		sha_idx += sizeof(sha_text);
	}

	/*
	 * Last write gets the length of the concatenation in bits. That is:
	 *  - 5 bytes per device
	 *  - 10 bytes for BINFO/BSTATUS(2), M0(8)
	 */
	sha_text = (num_downstream * 5 + 10) * 8;
	ret = intel_write_sha_text(dev_priv, sha_text);
	if (ret < 0)
		return ret;

	/* Tell the HW we're done with the hash and wait for it to ACK */
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	intel_de_write(dev_priv, HDCP_REP_CTL,
		       rep_ctl | HDCP_SHA1_COMPLETE_HASH);
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	if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL,
				  HDCP_SHA1_COMPLETE, 1)) {
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		drm_err(&dev_priv->drm, "Timed out waiting for SHA1 complete\n");
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		return -ETIMEDOUT;
	}
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	if (!(intel_de_read(dev_priv, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
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		drm_dbg_kms(&dev_priv->drm, "SHA-1 mismatch, HDCP failed\n");
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		return -ENXIO;
	}

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	return 0;
}

/* Implements Part 2 of the HDCP authorization procedure */
static
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int intel_hdcp_auth_downstream(struct intel_connector *connector)
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{
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	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
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	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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	const struct intel_hdcp_shim *shim = connector->hdcp.shim;
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	u8 bstatus[2], num_downstream, *ksv_fifo;
	int ret, i, tries = 3;

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	ret = intel_hdcp_poll_ksv_fifo(dig_port, shim);
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	if (ret) {
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		drm_dbg_kms(&dev_priv->drm,
			    "KSV list failed to become ready (%d)\n", ret);
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		return ret;
	}

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	ret = shim->read_bstatus(dig_port, bstatus);
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	if (ret)
		return ret;

	if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
	    DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
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		drm_dbg_kms(&dev_priv->drm, "Max Topology Limit Exceeded\n");
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		return -EPERM;
	}

	/*
	 * When repeater reports 0 device count, HDCP1.4 spec allows disabling
	 * the HDCP encryption. That implies that repeater can't have its own
	 * display. As there is no consumption of encrypted content in the
	 * repeater with 0 downstream devices, we are failing the
	 * authentication.
	 */
	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
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	if (num_downstream == 0) {
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		drm_dbg_kms(&dev_priv->drm,
			    "Repeater with zero downstream devices\n");
570
		return -EINVAL;
571
	}
572

573
	ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
574
	if (!ksv_fifo) {
575
		drm_dbg_kms(&dev_priv->drm, "Out of mem: ksv_fifo\n");
576
		return -ENOMEM;
577
	}
578

579
	ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo);
580
	if (ret)
581
		goto err;
582

583
	if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, ksv_fifo,
584
					num_downstream) > 0) {
585
		drm_err(&dev_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
586 587
		ret = -EPERM;
		goto err;
588 589
	}

590 591 592 593 594
	/*
	 * When V prime mismatches, DP Spec mandates re-read of
	 * V prime atleast twice.
	 */
	for (i = 0; i < tries; i++) {
595
		ret = intel_hdcp_validate_v_prime(connector, shim,
596 597 598 599 600 601 602
						  ksv_fifo, num_downstream,
						  bstatus);
		if (!ret)
			break;
	}

	if (i == tries) {
603 604
		drm_dbg_kms(&dev_priv->drm,
			    "V Prime validation failed.(%d)\n", ret);
605
		goto err;
606 607
	}

608 609
	drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (%d downstream devices)\n",
		    num_downstream);
610 611 612 613
	ret = 0;
err:
	kfree(ksv_fifo);
	return ret;
614 615 616
}

/* Implements Part 1 of the HDCP authorization procedure */
617
static int intel_hdcp_auth(struct intel_connector *connector)
618
{
619
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
620
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
621 622
	struct intel_hdcp *hdcp = &connector->hdcp;
	const struct intel_hdcp_shim *shim = hdcp->shim;
623
	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
624
	enum port port = dig_port->base.port;
625
	unsigned long r0_prime_gen_start;
626
	int ret, i, tries = 2;
627 628 629 630 631 632 633 634 635 636 637 638
	union {
		u32 reg[2];
		u8 shim[DRM_HDCP_AN_LEN];
	} an;
	union {
		u32 reg[2];
		u8 shim[DRM_HDCP_KSV_LEN];
	} bksv;
	union {
		u32 reg;
		u8 shim[DRM_HDCP_RI_LEN];
	} ri;
639
	bool repeater_present, hdcp_capable;
640

641 642 643 644 645 646 647
	/*
	 * Detects whether the display is HDCP capable. Although we check for
	 * valid Bksv below, the HDCP over DP spec requires that we check
	 * whether the display supports HDCP before we write An. For HDMI
	 * displays, this is not necessary.
	 */
	if (shim->hdcp_capable) {
648
		ret = shim->hdcp_capable(dig_port, &hdcp_capable);
649 650 651
		if (ret)
			return ret;
		if (!hdcp_capable) {
652 653
			drm_dbg_kms(&dev_priv->drm,
				    "Panel is not HDCP capable\n");
654 655 656 657
			return -EINVAL;
		}
	}

658 659
	/* Initialize An with 2 random values and acquire it */
	for (i = 0; i < 2; i++)
660 661 662 663 664
		intel_de_write(dev_priv,
			       HDCP_ANINIT(dev_priv, cpu_transcoder, port),
			       get_random_u32());
	intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port),
		       HDCP_CONF_CAPTURE_AN);
665 666

	/* Wait for An to be acquired */
667 668
	if (intel_de_wait_for_set(dev_priv,
				  HDCP_STATUS(dev_priv, cpu_transcoder, port),
669
				  HDCP_STATUS_AN_READY, 1)) {
670
		drm_err(&dev_priv->drm, "Timed out waiting for An\n");
671 672 673
		return -ETIMEDOUT;
	}

674 675 676 677
	an.reg[0] = intel_de_read(dev_priv,
				  HDCP_ANLO(dev_priv, cpu_transcoder, port));
	an.reg[1] = intel_de_read(dev_priv,
				  HDCP_ANHI(dev_priv, cpu_transcoder, port));
678
	ret = shim->write_an_aksv(dig_port, an.shim);
679 680 681 682 683 684
	if (ret)
		return ret;

	r0_prime_gen_start = jiffies;

	memset(&bksv, 0, sizeof(bksv));
685

686
	ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim);
687 688
	if (ret < 0)
		return ret;
689

690
	if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, bksv.shim, 1) > 0) {
691
		drm_err(&dev_priv->drm, "BKSV is revoked\n");
692 693 694
		return -EPERM;
	}

695 696 697 698
	intel_de_write(dev_priv, HDCP_BKSVLO(dev_priv, cpu_transcoder, port),
		       bksv.reg[0]);
	intel_de_write(dev_priv, HDCP_BKSVHI(dev_priv, cpu_transcoder, port),
		       bksv.reg[1]);
699

700
	ret = shim->repeater_present(dig_port, &repeater_present);
701 702 703
	if (ret)
		return ret;
	if (repeater_present)
704 705
		intel_de_write(dev_priv, HDCP_REP_CTL,
			       intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port));
706

707
	ret = shim->toggle_signalling(dig_port, true);
708 709 710
	if (ret)
		return ret;

711 712
	intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port),
		       HDCP_CONF_AUTH_AND_ENC);
713 714

	/* Wait for R0 ready */
715
	if (wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
716
		     (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
717
		drm_err(&dev_priv->drm, "Timed out waiting for R0 ready\n");
718 719 720 721 722 723 724 725 726 727 728 729 730 731
		return -ETIMEDOUT;
	}

	/*
	 * Wait for R0' to become available. The spec says 100ms from Aksv, but
	 * some monitors can take longer than this. We'll set the timeout at
	 * 300ms just to be sure.
	 *
	 * On DP, there's an R0_READY bit available but no such bit
	 * exists on HDMI. Since the upper-bound is the same, we'll just do
	 * the stupid thing instead of polling on one and not the other.
	 */
	wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);

732
	tries = 3;
733

734 735 736 737 738 739
	/*
	 * DP HDCP Spec mandates the two more reattempt to read R0, incase
	 * of R0 mismatch.
	 */
	for (i = 0; i < tries; i++) {
		ri.reg = 0;
740
		ret = shim->read_ri_prime(dig_port, ri.shim);
741 742
		if (ret)
			return ret;
743 744 745
		intel_de_write(dev_priv,
			       HDCP_RPRIME(dev_priv, cpu_transcoder, port),
			       ri.reg);
746 747

		/* Wait for Ri prime match */
748 749
		if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
			      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
750 751 752 753
			break;
	}

	if (i == tries) {
754 755 756 757
		drm_dbg_kms(&dev_priv->drm,
			    "Timed out waiting for Ri prime match (%x)\n",
			    intel_de_read(dev_priv, HDCP_STATUS(dev_priv,
					  cpu_transcoder, port)));
758 759 760 761
		return -ETIMEDOUT;
	}

	/* Wait for encryption confirmation */
762 763
	if (intel_de_wait_for_set(dev_priv,
				  HDCP_STATUS(dev_priv, cpu_transcoder, port),
764 765
				  HDCP_STATUS_ENC,
				  ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
766
		drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
767 768 769 770 771 772 773 774
		return -ETIMEDOUT;
	}

	/*
	 * XXX: If we have MST-connected devices, we need to enable encryption
	 * on those as well.
	 */

775
	if (repeater_present)
776
		return intel_hdcp_auth_downstream(connector);
777

778
	drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (no repeater present)\n");
779
	return 0;
780 781 782 783
}

static int _intel_hdcp_disable(struct intel_connector *connector)
{
784
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
785 786
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct intel_hdcp *hdcp = &connector->hdcp;
787
	enum port port = dig_port->base.port;
788
	enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
789
	u32 repeater_ctl;
790 791
	int ret;

792 793
	drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
		    connector->base.name, connector->base.base.id);
794

795
	hdcp->hdcp_encrypted = false;
796
	intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
797 798 799
	if (intel_de_wait_for_clear(dev_priv,
				    HDCP_STATUS(dev_priv, cpu_transcoder, port),
				    ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
800 801
		drm_err(&dev_priv->drm,
			"Failed to disable HDCP, timeout clearing status\n");
802 803 804
		return -ETIMEDOUT;
	}

805 806 807 808 809
	repeater_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,
						   port);
	intel_de_write(dev_priv, HDCP_REP_CTL,
		       intel_de_read(dev_priv, HDCP_REP_CTL) & ~repeater_ctl);

810
	ret = hdcp->shim->toggle_signalling(dig_port, false);
811
	if (ret) {
812
		drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n");
813 814 815
		return ret;
	}

816
	drm_dbg_kms(&dev_priv->drm, "HDCP is disabled\n");
817 818 819 820 821
	return 0;
}

static int _intel_hdcp_enable(struct intel_connector *connector)
{
822
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
823
	struct intel_hdcp *hdcp = &connector->hdcp;
824
	int i, ret, tries = 3;
825

826 827
	drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being enabled...\n",
		    connector->base.name, connector->base.base.id);
828

829
	if (!hdcp_key_loadable(dev_priv)) {
830
		drm_err(&dev_priv->drm, "HDCP key Load is not possible\n");
831 832 833 834 835 836 837 838 839 840
		return -ENXIO;
	}

	for (i = 0; i < KEY_LOAD_TRIES; i++) {
		ret = intel_hdcp_load_keys(dev_priv);
		if (!ret)
			break;
		intel_hdcp_clear_keys(dev_priv);
	}
	if (ret) {
841 842
		drm_err(&dev_priv->drm, "Could not load HDCP keys, (%d)\n",
			ret);
843 844 845
		return ret;
	}

846 847
	/* Incase of authentication failures, HDCP spec expects reauth. */
	for (i = 0; i < tries; i++) {
848
		ret = intel_hdcp_auth(connector);
849 850
		if (!ret) {
			hdcp->hdcp_encrypted = true;
851
			return 0;
852
		}
853

854
		drm_dbg_kms(&dev_priv->drm, "HDCP Auth failure (%d)\n", ret);
855 856 857

		/* Ensuring HDCP encryption and signalling are stopped. */
		_intel_hdcp_disable(connector);
858 859
	}

860 861
	drm_dbg_kms(&dev_priv->drm,
		    "HDCP authentication failed (%d tries/%d)\n", tries, ret);
862
	return ret;
863 864
}

865
static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp)
866 867 868 869
{
	return container_of(hdcp, struct intel_connector, hdcp);
}

870
/* Implements Part 3 of the HDCP authorization procedure */
871
static int intel_hdcp_check_link(struct intel_connector *connector)
872
{
873
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
874 875
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct intel_hdcp *hdcp = &connector->hdcp;
876
	enum port port = dig_port->base.port;
877
	enum transcoder cpu_transcoder;
878 879 880
	int ret = 0;

	mutex_lock(&hdcp->mutex);
881
	cpu_transcoder = hdcp->cpu_transcoder;
882

883 884 885 886
	/* Check_link valid only when HDCP1.4 is enabled */
	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
	    !hdcp->hdcp_encrypted) {
		ret = -EINVAL;
887
		goto out;
888
	}
889

890 891
	if (drm_WARN_ON(&dev_priv->drm,
			!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
892 893 894
		drm_err(&dev_priv->drm,
			"%s:%d HDCP link stopped encryption,%x\n",
			connector->base.name, connector->base.base.id,
895
			intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)));
896 897 898 899 900 901
		ret = -ENXIO;
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		goto out;
	}

902
	if (hdcp->shim->check_link(dig_port)) {
903 904 905 906 907 908 909
		if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
			hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
			schedule_work(&hdcp->prop_work);
		}
		goto out;
	}

910 911 912
	drm_dbg_kms(&dev_priv->drm,
		    "[%s:%d] HDCP link failed, retrying authentication\n",
		    connector->base.name, connector->base.base.id);
913 914 915

	ret = _intel_hdcp_disable(connector);
	if (ret) {
916
		drm_err(&dev_priv->drm, "Failed to disable hdcp (%d)\n", ret);
917 918 919 920 921 922 923
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		goto out;
	}

	ret = _intel_hdcp_enable(connector);
	if (ret) {
924
		drm_err(&dev_priv->drm, "Failed to enable hdcp (%d)\n", ret);
925 926 927 928 929 930 931 932 933 934
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		goto out;
	}

out:
	mutex_unlock(&hdcp->mutex);
	return ret;
}

935 936
static void intel_hdcp_prop_work(struct work_struct *work)
{
937 938 939
	struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp,
					       prop_work);
	struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
940
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
941

942
	drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, NULL);
943
	mutex_lock(&hdcp->mutex);
944 945 946

	/*
	 * This worker is only used to flip between ENABLED/DESIRED. Either of
947
	 * those to UNDESIRED is handled by core. If value == UNDESIRED,
948 949
	 * we're running just after hdcp has been disabled, so just exit
	 */
950 951 952
	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
		drm_hdcp_update_content_protection(&connector->base,
						   hdcp->value);
953

954
	mutex_unlock(&hdcp->mutex);
955
	drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);
956 957
}

958 959
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
{
960 961
	return INTEL_INFO(dev_priv)->display.has_hdcp &&
			(INTEL_GEN(dev_priv) >= 12 || port < PORT_E);
962 963
}

964
static int
965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982
hdcp2_prepare_ake_init(struct intel_connector *connector,
		       struct hdcp2_ake_init *ake_data)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data);
	if (ret)
983 984
		drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
			    ret);
985 986 987 988 989
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

990
static int
991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
				struct hdcp2_ake_send_cert *rx_cert,
				bool *paired,
				struct hdcp2_ake_no_stored_km *ek_pub_km,
				size_t *msg_sz)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_dev, data,
							 rx_cert, paired,
							 ek_pub_km, msg_sz);
	if (ret < 0)
1014 1015
		drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n",
			    ret);
1016 1017 1018 1019 1020
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1021 1022
static int hdcp2_verify_hprime(struct intel_connector *connector,
			       struct hdcp2_ake_send_hprime *rx_hprime)
1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
	if (ret < 0)
1039
		drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
1040 1041 1042 1043 1044
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1045
static int
1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
hdcp2_store_pairing_info(struct intel_connector *connector,
			 struct hdcp2_ake_send_pairing_info *pairing_info)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->store_pairing_info(comp->mei_dev, data, pairing_info);
	if (ret < 0)
1064 1065
		drm_dbg_kms(&dev_priv->drm, "Store pairing info failed. %d\n",
			    ret);
1066 1067 1068 1069 1070
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1071
static int
1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
hdcp2_prepare_lc_init(struct intel_connector *connector,
		      struct hdcp2_lc_init *lc_init)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->initiate_locality_check(comp->mei_dev, data, lc_init);
	if (ret < 0)
1090 1091
		drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed. %d\n",
			    ret);
1092 1093 1094 1095 1096
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1097
static int
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115
hdcp2_verify_lprime(struct intel_connector *connector,
		    struct hdcp2_lc_send_lprime *rx_lprime)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->verify_lprime(comp->mei_dev, data, rx_lprime);
	if (ret < 0)
1116 1117
		drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed. %d\n",
			    ret);
1118 1119 1120 1121 1122
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1123 1124
static int hdcp2_prepare_skey(struct intel_connector *connector,
			      struct hdcp2_ske_send_eks *ske_data)
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->get_session_key(comp->mei_dev, data, ske_data);
	if (ret < 0)
1141 1142
		drm_dbg_kms(&dev_priv->drm, "Get session key failed. %d\n",
			    ret);
1143 1144 1145 1146 1147
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1148
static int
1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
				      struct hdcp2_rep_send_receiverid_list
								*rep_topology,
				      struct hdcp2_rep_send_ack *rep_send_ack)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->repeater_check_flow_prepare_ack(comp->mei_dev, data,
							 rep_topology,
							 rep_send_ack);
	if (ret < 0)
1171 1172
		drm_dbg_kms(&dev_priv->drm,
			    "Verify rep topology failed. %d\n", ret);
1173 1174 1175 1176 1177
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1178
static int
1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
hdcp2_verify_mprime(struct intel_connector *connector,
		    struct hdcp2_rep_stream_ready *stream_ready)
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready);
	if (ret < 0)
1197
		drm_dbg_kms(&dev_priv->drm, "Verify mprime failed. %d\n", ret);
1198 1199 1200 1201 1202
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1203
static int hdcp2_authenticate_port(struct intel_connector *connector)
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
{
	struct hdcp_port_data *data = &connector->hdcp.port_data;
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->enable_hdcp_authentication(comp->mei_dev, data);
	if (ret < 0)
1220 1221
		drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
			    ret);
1222 1223 1224 1225 1226
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1227
static int hdcp2_close_mei_session(struct intel_connector *connector)
1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
{
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct i915_hdcp_comp_master *comp;
	int ret;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
	comp = dev_priv->hdcp_master;

	if (!comp || !comp->ops) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return -EINVAL;
	}

	ret = comp->ops->close_hdcp_session(comp->mei_dev,
					     &connector->hdcp.port_data);
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return ret;
}

1248
static int hdcp2_deauthenticate_port(struct intel_connector *connector)
1249 1250 1251 1252
{
	return hdcp2_close_mei_session(connector);
}

1253 1254 1255
/* Authentication flow starts from here */
static int hdcp2_authentication_key_exchange(struct intel_connector *connector)
{
1256
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1257
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277
	struct intel_hdcp *hdcp = &connector->hdcp;
	union {
		struct hdcp2_ake_init ake_init;
		struct hdcp2_ake_send_cert send_cert;
		struct hdcp2_ake_no_stored_km no_stored_km;
		struct hdcp2_ake_send_hprime send_hprime;
		struct hdcp2_ake_send_pairing_info pairing_info;
	} msgs;
	const struct intel_hdcp_shim *shim = hdcp->shim;
	size_t size;
	int ret;

	/* Init for seq_num */
	hdcp->seq_num_v = 0;
	hdcp->seq_num_m = 0;

	ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init);
	if (ret < 0)
		return ret;

1278
	ret = shim->write_2_2_msg(dig_port, &msgs.ake_init,
1279 1280 1281 1282
				  sizeof(msgs.ake_init));
	if (ret < 0)
		return ret;

1283
	ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_CERT,
1284 1285 1286 1287
				 &msgs.send_cert, sizeof(msgs.send_cert));
	if (ret < 0)
		return ret;

1288
	if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) {
1289
		drm_dbg_kms(&dev_priv->drm, "cert.rx_caps dont claim HDCP2.2\n");
1290
		return -EINVAL;
1291
	}
1292 1293 1294

	hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]);

1295 1296
	if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm,
					msgs.send_cert.cert_rx.receiver_id,
1297
					1) > 0) {
1298
		drm_err(&dev_priv->drm, "Receiver ID is revoked\n");
1299 1300 1301
		return -EPERM;
	}

1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
	/*
	 * Here msgs.no_stored_km will hold msgs corresponding to the km
	 * stored also.
	 */
	ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert,
					      &hdcp->is_paired,
					      &msgs.no_stored_km, &size);
	if (ret < 0)
		return ret;

1312
	ret = shim->write_2_2_msg(dig_port, &msgs.no_stored_km, size);
1313 1314 1315
	if (ret < 0)
		return ret;

1316
	ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_HPRIME,
1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
				 &msgs.send_hprime, sizeof(msgs.send_hprime));
	if (ret < 0)
		return ret;

	ret = hdcp2_verify_hprime(connector, &msgs.send_hprime);
	if (ret < 0)
		return ret;

	if (!hdcp->is_paired) {
		/* Pairing is required */
1327
		ret = shim->read_2_2_msg(dig_port,
1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
					 HDCP_2_2_AKE_SEND_PAIRING_INFO,
					 &msgs.pairing_info,
					 sizeof(msgs.pairing_info));
		if (ret < 0)
			return ret;

		ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info);
		if (ret < 0)
			return ret;
		hdcp->is_paired = true;
	}

	return 0;
}

static int hdcp2_locality_check(struct intel_connector *connector)
{
1345
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
	struct intel_hdcp *hdcp = &connector->hdcp;
	union {
		struct hdcp2_lc_init lc_init;
		struct hdcp2_lc_send_lprime send_lprime;
	} msgs;
	const struct intel_hdcp_shim *shim = hdcp->shim;
	int tries = HDCP2_LC_RETRY_CNT, ret, i;

	for (i = 0; i < tries; i++) {
		ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init);
		if (ret < 0)
			continue;

1359
		ret = shim->write_2_2_msg(dig_port, &msgs.lc_init,
1360 1361 1362 1363
				      sizeof(msgs.lc_init));
		if (ret < 0)
			continue;

1364
		ret = shim->read_2_2_msg(dig_port,
1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
					 HDCP_2_2_LC_SEND_LPRIME,
					 &msgs.send_lprime,
					 sizeof(msgs.send_lprime));
		if (ret < 0)
			continue;

		ret = hdcp2_verify_lprime(connector, &msgs.send_lprime);
		if (!ret)
			break;
	}

	return ret;
}

static int hdcp2_session_key_exchange(struct intel_connector *connector)
{
1381
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1382 1383 1384 1385 1386 1387 1388 1389
	struct intel_hdcp *hdcp = &connector->hdcp;
	struct hdcp2_ske_send_eks send_eks;
	int ret;

	ret = hdcp2_prepare_skey(connector, &send_eks);
	if (ret < 0)
		return ret;

1390
	ret = hdcp->shim->write_2_2_msg(dig_port, &send_eks,
1391 1392 1393 1394 1395 1396 1397
					sizeof(send_eks));
	if (ret < 0)
		return ret;

	return 0;
}

1398 1399 1400
static
int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
1401
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1402
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1403 1404 1405 1406 1407 1408 1409 1410 1411 1412
	struct intel_hdcp *hdcp = &connector->hdcp;
	union {
		struct hdcp2_rep_stream_manage stream_manage;
		struct hdcp2_rep_stream_ready stream_ready;
	} msgs;
	const struct intel_hdcp_shim *shim = hdcp->shim;
	int ret;

	/* Prepare RepeaterAuth_Stream_Manage msg */
	msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
1413
	drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
1414 1415 1416 1417 1418 1419 1420 1421 1422

	/* K no of streams is fixed as 1. Stored as big-endian. */
	msgs.stream_manage.k = cpu_to_be16(1);

	/* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
	msgs.stream_manage.streams[0].stream_id = 0;
	msgs.stream_manage.streams[0].stream_type = hdcp->content_type;

	/* Send it to Repeater */
1423
	ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
1424 1425 1426 1427
				  sizeof(msgs.stream_manage));
	if (ret < 0)
		return ret;

1428
	ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY,
1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442
				 &msgs.stream_ready, sizeof(msgs.stream_ready));
	if (ret < 0)
		return ret;

	hdcp->port_data.seq_num_m = hdcp->seq_num_m;
	hdcp->port_data.streams[0].stream_type = hdcp->content_type;

	ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
	if (ret < 0)
		return ret;

	hdcp->seq_num_m++;

	if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
1443
		drm_dbg_kms(&i915->drm, "seq_num_m roll over.\n");
1444 1445 1446 1447 1448 1449 1450 1451 1452
		return -1;
	}

	return 0;
}

static
int hdcp2_authenticate_repeater_topology(struct intel_connector *connector)
{
1453
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1454
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1455 1456 1457 1458 1459 1460
	struct intel_hdcp *hdcp = &connector->hdcp;
	union {
		struct hdcp2_rep_send_receiverid_list recvid_list;
		struct hdcp2_rep_send_ack rep_ack;
	} msgs;
	const struct intel_hdcp_shim *shim = hdcp->shim;
1461
	u32 seq_num_v, device_cnt;
1462 1463 1464
	u8 *rx_info;
	int ret;

1465
	ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_SEND_RECVID_LIST,
1466 1467 1468 1469 1470 1471 1472 1473
				 &msgs.recvid_list, sizeof(msgs.recvid_list));
	if (ret < 0)
		return ret;

	rx_info = msgs.recvid_list.rx_info;

	if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) ||
	    HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) {
1474
		drm_dbg_kms(&dev_priv->drm, "Topology Max Size Exceeded\n");
1475 1476 1477 1478
		return -EINVAL;
	}

	/* Converting and Storing the seq_num_v to local variable as DWORD */
1479 1480
	seq_num_v =
		drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v);
1481

1482 1483 1484 1485 1486 1487
	if (!hdcp->hdcp2_encrypted && seq_num_v) {
		drm_dbg_kms(&dev_priv->drm,
			    "Non zero Seq_num_v at first RecvId_List msg\n");
		return -EINVAL;
	}

1488 1489
	if (seq_num_v < hdcp->seq_num_v) {
		/* Roll over of the seq_num_v from repeater. Reauthenticate. */
1490
		drm_dbg_kms(&dev_priv->drm, "Seq_num_v roll over.\n");
1491 1492 1493
		return -EINVAL;
	}

1494 1495
	device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
		      HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
1496 1497
	if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm,
					msgs.recvid_list.receiver_ids,
1498
					device_cnt) > 0) {
1499
		drm_err(&dev_priv->drm, "Revoked receiver ID(s) is in list\n");
1500 1501 1502
		return -EPERM;
	}

1503 1504 1505 1506 1507 1508 1509
	ret = hdcp2_verify_rep_topology_prepare_ack(connector,
						    &msgs.recvid_list,
						    &msgs.rep_ack);
	if (ret < 0)
		return ret;

	hdcp->seq_num_v = seq_num_v;
1510
	ret = shim->write_2_2_msg(dig_port, &msgs.rep_ack,
1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528
				  sizeof(msgs.rep_ack));
	if (ret < 0)
		return ret;

	return 0;
}

static int hdcp2_authenticate_repeater(struct intel_connector *connector)
{
	int ret;

	ret = hdcp2_authenticate_repeater_topology(connector);
	if (ret < 0)
		return ret;

	return hdcp2_propagate_stream_management_info(connector);
}

1529 1530
static int hdcp2_authenticate_sink(struct intel_connector *connector)
{
1531
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1532
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1533 1534 1535
	struct intel_hdcp *hdcp = &connector->hdcp;
	const struct intel_hdcp_shim *shim = hdcp->shim;
	int ret;
1536

1537 1538
	ret = hdcp2_authentication_key_exchange(connector);
	if (ret < 0) {
1539
		drm_dbg_kms(&i915->drm, "AKE Failed. Err : %d\n", ret);
1540 1541 1542 1543 1544
		return ret;
	}

	ret = hdcp2_locality_check(connector);
	if (ret < 0) {
1545 1546
		drm_dbg_kms(&i915->drm,
			    "Locality Check failed. Err : %d\n", ret);
1547 1548 1549 1550 1551
		return ret;
	}

	ret = hdcp2_session_key_exchange(connector);
	if (ret < 0) {
1552
		drm_dbg_kms(&i915->drm, "SKE Failed. Err : %d\n", ret);
1553 1554 1555 1556
		return ret;
	}

	if (shim->config_stream_type) {
1557
		ret = shim->config_stream_type(dig_port,
1558 1559 1560 1561 1562 1563
					       hdcp->is_repeater,
					       hdcp->content_type);
		if (ret < 0)
			return ret;
	}

1564 1565 1566
	if (hdcp->is_repeater) {
		ret = hdcp2_authenticate_repeater(connector);
		if (ret < 0) {
1567 1568
			drm_dbg_kms(&i915->drm,
				    "Repeater Auth Failed. Err: %d\n", ret);
1569 1570 1571 1572
			return ret;
		}
	}

1573 1574 1575 1576 1577 1578
	hdcp->port_data.streams[0].stream_type = hdcp->content_type;
	ret = hdcp2_authenticate_port(connector);
	if (ret < 0)
		return ret;

	return ret;
1579 1580 1581 1582
}

static int hdcp2_enable_encryption(struct intel_connector *connector)
{
1583
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1584 1585
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct intel_hdcp *hdcp = &connector->hdcp;
1586
	enum port port = dig_port->base.port;
1587
	enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
1588 1589
	int ret;

1590 1591 1592
	drm_WARN_ON(&dev_priv->drm,
		    intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
		    LINK_ENCRYPTION_STATUS);
1593
	if (hdcp->shim->toggle_signalling) {
1594
		ret = hdcp->shim->toggle_signalling(dig_port, true);
1595
		if (ret) {
1596 1597 1598
			drm_err(&dev_priv->drm,
				"Failed to enable HDCP signalling. %d\n",
				ret);
1599 1600 1601 1602
			return ret;
		}
	}

1603
	if (intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
1604
	    LINK_AUTH_STATUS) {
1605
		/* Link is Authenticated. Now set for Encryption */
1606 1607 1608
		intel_de_write(dev_priv,
			       HDCP2_CTL(dev_priv, cpu_transcoder, port),
			       intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) | CTL_LINK_ENCRYPTION_REQ);
1609 1610
	}

1611 1612 1613
	ret = intel_de_wait_for_set(dev_priv,
				    HDCP2_STATUS(dev_priv, cpu_transcoder,
						 port),
1614 1615
				    LINK_ENCRYPTION_STATUS,
				    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
1616 1617 1618 1619 1620 1621

	return ret;
}

static int hdcp2_disable_encryption(struct intel_connector *connector)
{
1622
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1623 1624
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct intel_hdcp *hdcp = &connector->hdcp;
1625
	enum port port = dig_port->base.port;
1626
	enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
1627 1628
	int ret;

1629 1630
	drm_WARN_ON(&dev_priv->drm, !(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
				      LINK_ENCRYPTION_STATUS));
1631

1632 1633
	intel_de_write(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port),
		       intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) & ~CTL_LINK_ENCRYPTION_REQ);
1634

1635 1636 1637
	ret = intel_de_wait_for_clear(dev_priv,
				      HDCP2_STATUS(dev_priv, cpu_transcoder,
						   port),
1638
				      LINK_ENCRYPTION_STATUS,
1639 1640
				      ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
	if (ret == -ETIMEDOUT)
1641
		drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
1642 1643

	if (hdcp->shim->toggle_signalling) {
1644
		ret = hdcp->shim->toggle_signalling(dig_port, false);
1645
		if (ret) {
1646 1647 1648
			drm_err(&dev_priv->drm,
				"Failed to disable HDCP signalling. %d\n",
				ret);
1649 1650 1651 1652 1653 1654 1655 1656 1657
			return ret;
		}
	}

	return ret;
}

static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
1658
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1659 1660 1661 1662 1663 1664 1665 1666
	int ret, i, tries = 3;

	for (i = 0; i < tries; i++) {
		ret = hdcp2_authenticate_sink(connector);
		if (!ret)
			break;

		/* Clearing the mei hdcp session */
1667 1668
		drm_dbg_kms(&i915->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n",
			    i + 1, tries, ret);
1669
		if (hdcp2_deauthenticate_port(connector) < 0)
1670
			drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
1671 1672 1673 1674 1675 1676 1677 1678 1679 1680
	}

	if (i != tries) {
		/*
		 * Ensuring the required 200mSec min time interval between
		 * Session Key Exchange and encryption.
		 */
		msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN);
		ret = hdcp2_enable_encryption(connector);
		if (ret < 0) {
1681 1682
			drm_dbg_kms(&i915->drm,
				    "Encryption Enable Failed.(%d)\n", ret);
1683
			if (hdcp2_deauthenticate_port(connector) < 0)
1684
				drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
1685 1686 1687 1688 1689 1690 1691 1692
		}
	}

	return ret;
}

static int _intel_hdcp2_enable(struct intel_connector *connector)
{
1693
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1694 1695 1696
	struct intel_hdcp *hdcp = &connector->hdcp;
	int ret;

1697 1698 1699
	drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being enabled. Type: %d\n",
		    connector->base.name, connector->base.base.id,
		    hdcp->content_type);
1700 1701 1702

	ret = hdcp2_authenticate_and_encrypt(connector);
	if (ret) {
1703 1704
		drm_dbg_kms(&i915->drm, "HDCP2 Type%d  Enabling Failed. (%d)\n",
			    hdcp->content_type, ret);
1705 1706 1707
		return ret;
	}

1708 1709 1710
	drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is enabled. Type %d\n",
		    connector->base.name, connector->base.base.id,
		    hdcp->content_type);
1711 1712 1713 1714 1715 1716 1717

	hdcp->hdcp2_encrypted = true;
	return 0;
}

static int _intel_hdcp2_disable(struct intel_connector *connector)
{
1718
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1719 1720
	int ret;

1721 1722
	drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
		    connector->base.name, connector->base.base.id);
1723 1724 1725 1726

	ret = hdcp2_disable_encryption(connector);

	if (hdcp2_deauthenticate_port(connector) < 0)
1727
		drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
1728 1729 1730 1731 1732 1733

	connector->hdcp.hdcp2_encrypted = false;

	return ret;
}

1734 1735 1736
/* Implements the Link Integrity Check for HDCP2.2 */
static int intel_hdcp2_check_link(struct intel_connector *connector)
{
1737
	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1738 1739
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
	struct intel_hdcp *hdcp = &connector->hdcp;
1740
	enum port port = dig_port->base.port;
1741
	enum transcoder cpu_transcoder;
1742 1743 1744
	int ret = 0;

	mutex_lock(&hdcp->mutex);
1745
	cpu_transcoder = hdcp->cpu_transcoder;
1746 1747 1748 1749 1750 1751 1752 1753

	/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
	    !hdcp->hdcp2_encrypted) {
		ret = -EINVAL;
		goto out;
	}

1754 1755
	if (drm_WARN_ON(&dev_priv->drm,
			!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
1756 1757
		drm_err(&dev_priv->drm,
			"HDCP2.2 link stopped the encryption, %x\n",
1758
			intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)));
1759 1760 1761 1762 1763 1764
		ret = -ENXIO;
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		goto out;
	}

1765
	ret = hdcp->shim->check_2_2_link(dig_port);
1766 1767 1768 1769 1770 1771 1772 1773
	if (ret == HDCP_LINK_PROTECTED) {
		if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
			hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
			schedule_work(&hdcp->prop_work);
		}
		goto out;
	}

1774 1775 1776 1777
	if (ret == HDCP_TOPOLOGY_CHANGE) {
		if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
			goto out;

1778 1779
		drm_dbg_kms(&dev_priv->drm,
			    "HDCP2.2 Downstream topology change\n");
1780 1781 1782 1783 1784 1785
		ret = hdcp2_authenticate_repeater_topology(connector);
		if (!ret) {
			hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
			schedule_work(&hdcp->prop_work);
			goto out;
		}
1786 1787 1788 1789
		drm_dbg_kms(&dev_priv->drm,
			    "[%s:%d] Repeater topology auth failed.(%d)\n",
			    connector->base.name, connector->base.base.id,
			    ret);
1790
	} else {
1791 1792 1793
		drm_dbg_kms(&dev_priv->drm,
			    "[%s:%d] HDCP2.2 link failed, retrying auth\n",
			    connector->base.name, connector->base.base.id);
1794
	}
1795 1796 1797

	ret = _intel_hdcp2_disable(connector);
	if (ret) {
1798 1799 1800
		drm_err(&dev_priv->drm,
			"[%s:%d] Failed to disable hdcp2.2 (%d)\n",
			connector->base.name, connector->base.base.id, ret);
1801 1802 1803 1804 1805 1806 1807
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		goto out;
	}

	ret = _intel_hdcp2_enable(connector);
	if (ret) {
1808 1809 1810 1811
		drm_dbg_kms(&dev_priv->drm,
			    "[%s:%d] Failed to enable hdcp2.2 (%d)\n",
			    connector->base.name, connector->base.base.id,
			    ret);
1812 1813 1814 1815 1816 1817 1818 1819 1820 1821
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		goto out;
	}

out:
	mutex_unlock(&hdcp->mutex);
	return ret;
}

1822 1823 1824 1825 1826 1827 1828
static void intel_hdcp_check_work(struct work_struct *work)
{
	struct intel_hdcp *hdcp = container_of(to_delayed_work(work),
					       struct intel_hdcp,
					       check_work);
	struct intel_connector *connector = intel_hdcp_to_connector(hdcp);

1829 1830 1831 1832
	if (!intel_hdcp2_check_link(connector))
		schedule_delayed_work(&hdcp->check_work,
				      DRM_HDCP2_CHECK_PERIOD_MS);
	else if (!intel_hdcp_check_link(connector))
1833 1834 1835 1836
		schedule_delayed_work(&hdcp->check_work,
				      DRM_HDCP_CHECK_PERIOD_MS);
}

1837 1838 1839 1840 1841
static int i915_hdcp_component_bind(struct device *i915_kdev,
				    struct device *mei_kdev, void *data)
{
	struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);

1842
	drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n");
1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855
	mutex_lock(&dev_priv->hdcp_comp_mutex);
	dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data;
	dev_priv->hdcp_master->mei_dev = mei_kdev;
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	return 0;
}

static void i915_hdcp_component_unbind(struct device *i915_kdev,
				       struct device *mei_kdev, void *data)
{
	struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);

1856
	drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n");
1857 1858 1859 1860 1861 1862 1863 1864 1865 1866
	mutex_lock(&dev_priv->hdcp_comp_mutex);
	dev_priv->hdcp_master = NULL;
	mutex_unlock(&dev_priv->hdcp_comp_mutex);
}

static const struct component_ops i915_hdcp_component_ops = {
	.bind   = i915_hdcp_component_bind,
	.unbind = i915_hdcp_component_unbind,
};

1867
static enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port)
1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878
{
	switch (port) {
	case PORT_A:
		return MEI_DDI_A;
	case PORT_B ... PORT_F:
		return (enum mei_fw_ddi)port;
	default:
		return MEI_DDI_INVALID_PORT;
	}
}

1879
static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
1880 1881 1882 1883 1884 1885 1886 1887 1888
{
	switch (cpu_transcoder) {
	case TRANSCODER_A ... TRANSCODER_D:
		return (enum mei_fw_tc)(cpu_transcoder | 0x10);
	default: /* eDP, DSI TRANSCODERS are non HDCP capable */
		return MEI_INVALID_TRANSCODER;
	}
}

1889 1890
static int initialize_hdcp_port_data(struct intel_connector *connector,
				     const struct intel_hdcp_shim *shim)
1891
{
1892
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1893 1894 1895
	struct intel_hdcp *hdcp = &connector->hdcp;
	struct hdcp_port_data *data = &hdcp->port_data;

1896 1897
	if (INTEL_GEN(dev_priv) < 12)
		data->fw_ddi =
1898
			intel_get_mei_fw_ddi_index(intel_attached_encoder(connector)->port);
1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912
	else
		/*
		 * As per ME FW API expectation, for GEN 12+, fw_ddi is filled
		 * with zero(INVALID PORT index).
		 */
		data->fw_ddi = MEI_DDI_INVALID_PORT;

	/*
	 * As associated transcoder is set and modified at modeset, here fw_tc
	 * is initialized to zero (invalid transcoder index). This will be
	 * retained for <Gen12 forever.
	 */
	data->fw_tc = MEI_INVALID_TRANSCODER;

1913
	data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
1914
	data->protocol = (u8)shim->protocol;
1915 1916 1917 1918 1919 1920 1921

	data->k = 1;
	if (!data->streams)
		data->streams = kcalloc(data->k,
					sizeof(struct hdcp2_streamid_type),
					GFP_KERNEL);
	if (!data->streams) {
1922
		drm_err(&dev_priv->drm, "Out of Memory\n");
1923 1924 1925 1926 1927 1928 1929 1930 1931
		return -ENOMEM;
	}

	data->streams[0].stream_id = 0;
	data->streams[0].stream_type = hdcp->content_type;

	return 0;
}

1932 1933 1934 1935 1936
static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
{
	if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
		return false;

1937 1938 1939 1940 1941
	return (INTEL_GEN(dev_priv) >= 10 ||
		IS_GEMINILAKE(dev_priv) ||
		IS_KABYLAKE(dev_priv) ||
		IS_COFFEELAKE(dev_priv) ||
		IS_COMETLAKE(dev_priv));
1942 1943
}

1944 1945 1946 1947 1948 1949 1950 1951
void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
{
	int ret;

	if (!is_hdcp2_supported(dev_priv))
		return;

	mutex_lock(&dev_priv->hdcp_comp_mutex);
1952
	drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added);
1953 1954 1955 1956 1957 1958

	dev_priv->hdcp_comp_added = true;
	mutex_unlock(&dev_priv->hdcp_comp_mutex);
	ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops,
				  I915_COMPONENT_HDCP);
	if (ret < 0) {
1959 1960
		drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n",
			    ret);
1961 1962 1963 1964 1965 1966 1967
		mutex_lock(&dev_priv->hdcp_comp_mutex);
		dev_priv->hdcp_comp_added = false;
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return;
	}
}

1968 1969
static void intel_hdcp2_init(struct intel_connector *connector,
			     const struct intel_hdcp_shim *shim)
1970
{
1971
	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1972
	struct intel_hdcp *hdcp = &connector->hdcp;
1973 1974
	int ret;

1975
	ret = initialize_hdcp_port_data(connector, shim);
1976
	if (ret) {
1977
		drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
1978 1979
		return;
	}
1980 1981 1982 1983

	hdcp->hdcp2_supported = true;
}

1984
int intel_hdcp_init(struct intel_connector *connector,
1985
		    const struct intel_hdcp_shim *shim)
1986
{
1987
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1988
	struct intel_hdcp *hdcp = &connector->hdcp;
1989 1990
	int ret;

1991 1992 1993
	if (!shim)
		return -EINVAL;

1994 1995 1996
	if (is_hdcp2_supported(dev_priv))
		intel_hdcp2_init(connector, shim);

1997 1998
	ret =
	drm_connector_attach_content_protection_property(&connector->base,
1999 2000 2001 2002
							 hdcp->hdcp2_supported);
	if (ret) {
		hdcp->hdcp2_supported = false;
		kfree(hdcp->port_data.streams);
2003
		return ret;
2004
	}
2005

2006 2007 2008 2009
	hdcp->shim = shim;
	mutex_init(&hdcp->mutex);
	INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work);
	INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work);
2010
	init_waitqueue_head(&hdcp->cp_irq_queue);
2011

2012 2013 2014
	return 0;
}

2015 2016
int intel_hdcp_enable(struct intel_connector *connector,
		      enum transcoder cpu_transcoder, u8 content_type)
2017
{
2018
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
2019
	struct intel_hdcp *hdcp = &connector->hdcp;
2020
	unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS;
2021
	int ret = -EINVAL;
2022

2023
	if (!hdcp->shim)
2024 2025
		return -ENOENT;

2026
	mutex_lock(&hdcp->mutex);
2027 2028
	drm_WARN_ON(&dev_priv->drm,
		    hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
2029
	hdcp->content_type = content_type;
2030

2031 2032 2033 2034 2035
	if (INTEL_GEN(dev_priv) >= 12) {
		hdcp->cpu_transcoder = cpu_transcoder;
		hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
	}

2036 2037 2038 2039
	/*
	 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
	 * is capable of HDCP2.2, it is preferred to use HDCP2.2.
	 */
2040
	if (intel_hdcp2_capable(connector)) {
2041
		ret = _intel_hdcp2_enable(connector);
2042 2043 2044
		if (!ret)
			check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS;
	}
2045

2046 2047 2048 2049 2050 2051
	/*
	 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will
	 * be attempted.
	 */
	if (ret && intel_hdcp_capable(connector) &&
	    hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) {
2052 2053 2054 2055
		ret = _intel_hdcp_enable(connector);
	}

	if (!ret) {
2056
		schedule_delayed_work(&hdcp->check_work, check_link_interval);
2057 2058 2059
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
		schedule_work(&hdcp->prop_work);
	}
2060

2061
	mutex_unlock(&hdcp->mutex);
2062 2063 2064 2065 2066
	return ret;
}

int intel_hdcp_disable(struct intel_connector *connector)
{
2067
	struct intel_hdcp *hdcp = &connector->hdcp;
2068
	int ret = 0;
2069

2070
	if (!hdcp->shim)
2071 2072
		return -ENOENT;

2073
	mutex_lock(&hdcp->mutex);
2074

2075 2076
	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2077 2078 2079
		if (hdcp->hdcp2_encrypted)
			ret = _intel_hdcp2_disable(connector);
		else if (hdcp->hdcp_encrypted)
2080
			ret = _intel_hdcp_disable(connector);
2081
	}
2082

2083 2084
	mutex_unlock(&hdcp->mutex);
	cancel_delayed_work_sync(&hdcp->check_work);
2085 2086 2087
	return ret;
}

2088 2089
void intel_hdcp_update_pipe(struct intel_atomic_state *state,
			    struct intel_encoder *encoder,
2090 2091 2092 2093 2094 2095
			    const struct intel_crtc_state *crtc_state,
			    const struct drm_connector_state *conn_state)
{
	struct intel_connector *connector =
				to_intel_connector(conn_state->connector);
	struct intel_hdcp *hdcp = &connector->hdcp;
2096 2097 2098 2099 2100 2101
	bool content_protection_type_changed, desired_and_not_enabled = false;

	if (!connector->hdcp.shim)
		return;

	content_protection_type_changed =
2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126
		(conn_state->hdcp_content_type != hdcp->content_type &&
		 conn_state->content_protection !=
		 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);

	/*
	 * During the HDCP encryption session if Type change is requested,
	 * disable the HDCP and reenable it with new TYPE value.
	 */
	if (conn_state->content_protection ==
	    DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
	    content_protection_type_changed)
		intel_hdcp_disable(connector);

	/*
	 * Mark the hdcp state as DESIRED after the hdcp disable of type
	 * change procedure.
	 */
	if (content_protection_type_changed) {
		mutex_lock(&hdcp->mutex);
		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		schedule_work(&hdcp->prop_work);
		mutex_unlock(&hdcp->mutex);
	}

	if (conn_state->content_protection ==
2127 2128 2129 2130 2131 2132 2133 2134 2135
	    DRM_MODE_CONTENT_PROTECTION_DESIRED) {
		mutex_lock(&hdcp->mutex);
		/* Avoid enabling hdcp, if it already ENABLED */
		desired_and_not_enabled =
			hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
		mutex_unlock(&hdcp->mutex);
	}

	if (desired_and_not_enabled || content_protection_type_changed)
2136 2137 2138 2139 2140
		intel_hdcp_enable(connector,
				  crtc_state->cpu_transcoder,
				  (u8)conn_state->hdcp_content_type);
}

2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv)
{
	mutex_lock(&dev_priv->hdcp_comp_mutex);
	if (!dev_priv->hdcp_comp_added) {
		mutex_unlock(&dev_priv->hdcp_comp_mutex);
		return;
	}

	dev_priv->hdcp_comp_added = false;
	mutex_unlock(&dev_priv->hdcp_comp_mutex);

	component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
}

void intel_hdcp_cleanup(struct intel_connector *connector)
{
	if (!connector->hdcp.shim)
		return;

	mutex_lock(&connector->hdcp.mutex);
	kfree(connector->hdcp.port_data.streams);
	mutex_unlock(&connector->hdcp.mutex);
}

2165 2166 2167 2168
void intel_hdcp_atomic_check(struct drm_connector *connector,
			     struct drm_connector_state *old_state,
			     struct drm_connector_state *new_state)
{
2169 2170
	u64 old_cp = old_state->content_protection;
	u64 new_cp = new_state->content_protection;
2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183
	struct drm_crtc_state *crtc_state;

	if (!new_state->crtc) {
		/*
		 * If the connector is being disabled with CP enabled, mark it
		 * desired so it's re-enabled when the connector is brought back
		 */
		if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
			new_state->content_protection =
				DRM_MODE_CONTENT_PROTECTION_DESIRED;
		return;
	}

2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196
	crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
						   new_state->crtc);
	/*
	 * Fix the HDCP uapi content protection state in case of modeset.
	 * FIXME: As per HDCP content protection property uapi doc, an uevent()
	 * need to be sent if there is transition from ENABLED->DESIRED.
	 */
	if (drm_atomic_crtc_needs_modeset(crtc_state) &&
	    (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
	    new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
		new_state->content_protection =
			DRM_MODE_CONTENT_PROTECTION_DESIRED;

2197 2198
	/*
	 * Nothing to do if the state didn't change, or HDCP was activated since
2199
	 * the last commit. And also no change in hdcp content type.
2200 2201 2202
	 */
	if (old_cp == new_cp ||
	    (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
2203 2204 2205 2206 2207
	     new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) {
		if (old_state->hdcp_content_type ==
				new_state->hdcp_content_type)
			return;
	}
2208 2209 2210

	crtc_state->mode_changed = true;
}
2211 2212 2213 2214 2215 2216 2217 2218 2219

/* Handles the CP_IRQ raised from the DP HDCP sink */
void intel_hdcp_handle_cp_irq(struct intel_connector *connector)
{
	struct intel_hdcp *hdcp = &connector->hdcp;

	if (!hdcp->shim)
		return;

2220 2221 2222
	atomic_inc(&connector->hdcp.cp_irq_count);
	wake_up_all(&connector->hdcp.cp_irq_queue);

2223 2224
	schedule_delayed_work(&hdcp->check_work, 0);
}