board_setup.c 5.51 KB
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/*
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 * Copyright 2000, 2008 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. <source@mvista.com>
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 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
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#include <linux/delay.h>
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#include <linux/init.h>
#include <linux/interrupt.h>
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#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1000.h>
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#include <prom.h>
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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	{ AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 },
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};


const char *get_system_type(void)
{
	return "Alchemy Pb1000";
}

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void board_reset(void)
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{
}

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void __init board_init_irq(void)
{
	au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
}

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void __init board_setup(void)
{
	u32 pin_func, static_cfg0;
	u32 sys_freqctrl, sys_clksrc;
	u32 prid = read_c0_prid();

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#ifdef CONFIG_SERIAL_8250_CONSOLE
	char *argptr = prom_getcmdline();
	argptr = strstr(argptr, "console=");
	if (argptr == NULL) {
		argptr = prom_getcmdline();
		strcat(argptr, " console=ttyS0,115200");
	}
#endif

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	/* Set AUX clock to 12 MHz * 8 = 96 MHz */
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	au_writel(8, SYS_AUXPLL);
	au_writel(0, SYS_PINSTATERD);
	udelay(100);

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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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	/* Zero and disable FREQ2 */
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	sys_freqctrl = au_readl(SYS_FREQCTRL0);
	sys_freqctrl &= ~0xFFF00000;
	au_writel(sys_freqctrl, SYS_FREQCTRL0);

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	/* Zero and disable USBH/USBD clocks */
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	sys_clksrc = au_readl(SYS_CLKSRC);
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	sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
		        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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	au_writel(sys_clksrc, SYS_CLKSRC);

	sys_freqctrl = au_readl(SYS_FREQCTRL0);
	sys_freqctrl &= ~0xFFF00000;

	sys_clksrc = au_readl(SYS_CLKSRC);
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	sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
		        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
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	switch (prid & 0x000000FF) {
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	case 0x00: /* DA */
	case 0x01: /* HA */
	case 0x02: /* HB */
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		/* CPU core freq to 48 MHz to slow it way down... */
		au_writel(4, SYS_CPUPLL);
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		/*
		 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
		 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
		 */
		sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
		au_writel(sys_freqctrl, SYS_FREQCTRL0);
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		/* CPU core freq to 384 MHz */
		au_writel(0x20, SYS_CPUPLL);
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		printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
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		break;

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	default: /* HC and newer */
		/* FREQ2 = aux / 2 = 48 MHz */
		sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
				 SYS_FC_FE2 | SYS_FC_FS2;
		au_writel(sys_freqctrl, SYS_FREQCTRL0);
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		break;
	}

	/*
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	 * Route 48 MHz FREQ2 into USB Host and/or Device
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	 */
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	sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
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	au_writel(sys_clksrc, SYS_CLKSRC);

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	/* Configure pins GPIO[14:9] as GPIO */
	pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
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	/* 2nd USB port is USB host */
	pin_func |= SYS_PF_USB;
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	au_writel(pin_func, SYS_PINFUNC);
	au_writel(0x2800, SYS_TRIOUTCLR);
	au_writel(0x0030, SYS_OUTPUTCLR);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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	/* Make GPIO 15 an input (for interrupt line) */
	pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
	/* We don't need I2S, so make it available for GPIO[31:29] */
	pin_func |= SYS_PF_I2S;
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	au_writel(pin_func, SYS_PINFUNC);

	au_writel(0x8000, SYS_TRIOUTCLR);

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	static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
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	au_writel(static_cfg0, MEM_STCFG0);

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	/* configure RCE2* for LCD */
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	au_writel(0x00000004, MEM_STCFG2);

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	/* MEM_STTIME2 */
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	au_writel(0x09000000, MEM_STTIME2);

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	/* Set 32-bit base address decoding for RCE2* */
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	au_writel(0x10003ff0, MEM_STADDR2);

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	/*
	 * PCI CPLD setup
	 * Expand CE0 to cover PCI
	 */
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	au_writel(0x11803e40, MEM_STADDR1);

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	/* Burst visibility on */
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	au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);

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	au_writel(0x83, MEM_STCFG1);	     /* ewait enabled, flash timing */
	au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
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	/* Setup the static bus controller */
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	au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
	au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
	au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */

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	/*
	 * Enable Au1000 BCLK switching - note: sed1356 must not use
	 * its BCLK (Au1000 LCLK) for any timings
	 */
	switch (prid & 0x000000FF) {
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	case 0x00: /* DA */
	case 0x01: /* HA */
	case 0x02: /* HB */
		break;
	default:  /* HC and newer */
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		/*
		 * Enable sys bus clock divider when IDLE state or no bus
		 * activity.
		 */
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		au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
		break;
	}
}