uhci-hcd.c 63.8 KB
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/*
 * Universal Host Controller Interface driver for USB.
 *
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 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
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 *
 * (C) Copyright 1999 Linus Torvalds
 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
 * (C) Copyright 1999 Randy Dunlap
 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
 *               support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
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 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
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 *
 * Intel documents this fairly well, and as far as I know there
 * are no royalties or anything like that, but even so there are
 * people who decided that they want to do the same thing in a
 * completely different way.
 *
 * WARNING! The USB documentation is downright evil. Most of it
 * is just crap, written by a committee. You're better off ignoring
 * most of it, the important stuff is:
 *  - the low-level protocol (fairly simple but lots of small details)
 *  - working around the horridness of the rest
 */

#include <linux/config.h>
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#ifdef CONFIG_USB_DEBUG
#define DEBUG
#else
#undef DEBUG
#endif
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#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/smp_lock.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/proc_fs.h>
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#include <linux/pm.h>
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#include <linux/dmapool.h>
#include <linux/dma-mapping.h>
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#include <linux/usb.h>

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#include <asm/bitops.h>
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#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>

#include "../core/hcd.h"
#include "uhci-hcd.h"

/*
 * Version Information
 */
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#define DRIVER_VERSION "v2.2"
#define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
Alan Stern"
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#define DRIVER_DESC "USB Universal Host Controller Interface driver"

/*
 * debug = 0, no debugging messages
 * debug = 1, dump failed URB's except for stalls
 * debug = 2, dump all failed URB's (including stalls)
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 *            show all queues in /proc/driver/uhci/[pci_addr]
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 * debug = 3, show all TD's in URB's when dumping
 */
#ifdef DEBUG
static int debug = 1;
#else
static int debug = 0;
#endif
MODULE_PARM(debug, "i");
MODULE_PARM_DESC(debug, "Debug level");
static char *errbuf;
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#define ERRBUF_LEN    (32 * 1024)
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#include "uhci-hub.c"
#include "uhci-debug.c"

static kmem_cache_t *uhci_up_cachep;	/* urb_priv */

static int uhci_get_current_frame_number(struct uhci_hcd *uhci);
static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
static void uhci_unlink_generic(struct uhci_hcd *uhci, struct urb *urb);
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static void uhci_remove_pending_urbps(struct uhci_hcd *uhci);
static void uhci_finish_completion(struct usb_hcd *hcd, struct pt_regs *regs);
static void uhci_free_pending_qhs(struct uhci_hcd *uhci);
static void uhci_free_pending_tds(struct uhci_hcd *uhci);
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static void hc_state_transitions(struct uhci_hcd *uhci);
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/* If a transfer is still active after this much time, turn off FSBR */
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#define IDLE_TIMEOUT	msecs_to_jiffies(50)
#define FSBR_DELAY	msecs_to_jiffies(50)
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/* When we timeout an idle transfer for FSBR, we'll switch it over to */
/* depth first traversal. We'll do it in groups of this number of TD's */
/* to make sure it doesn't hog all of the bandwidth */
#define DEPTH_INTERVAL 5

/*
 * Technically, updating td->status here is a race, but it's not really a
 * problem. The worst that can happen is that we set the IOC bit again
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 * generating a spurious interrupt. We could fix this by creating another
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 * QH and leaving the IOC bit always set, but then we would have to play
 * games with the FSBR code to make sure we get the correct order in all
 * the cases. I don't think it's worth the effort
 */
static inline void uhci_set_next_interrupt(struct uhci_hcd *uhci)
{
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	uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC); 
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}

static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
{
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	uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
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}

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static inline void uhci_moveto_complete(struct uhci_hcd *uhci, 
					struct urb_priv *urbp)
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{
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	list_move_tail(&urbp->urb_list, &uhci->complete_list);
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}

static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci, struct usb_device *dev)
{
	dma_addr_t dma_handle;
	struct uhci_td *td;

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	td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
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	if (!td)
		return NULL;

	td->dma_handle = dma_handle;

	td->link = UHCI_PTR_TERM;
	td->buffer = 0;

	td->frame = -1;
	td->dev = dev;

	INIT_LIST_HEAD(&td->list);
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	INIT_LIST_HEAD(&td->remove_list);
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	INIT_LIST_HEAD(&td->fl_list);

	usb_get_dev(dev);

	return td;
}

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static inline void uhci_fill_td(struct uhci_td *td, u32 status,
		u32 token, u32 buffer)
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{
	td->status = cpu_to_le32(status);
	td->token = cpu_to_le32(token);
	td->buffer = cpu_to_le32(buffer);
}

/*
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 * We insert Isochronous URB's directly into the frame list at the beginning
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 */
static void uhci_insert_td_frame_list(struct uhci_hcd *uhci, struct uhci_td *td, unsigned framenum)
{
	framenum %= UHCI_NUMFRAMES;

	td->frame = framenum;

	/* Is there a TD already mapped there? */
	if (uhci->fl->frame_cpu[framenum]) {
		struct uhci_td *ftd, *ltd;

		ftd = uhci->fl->frame_cpu[framenum];
		ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);

		list_add_tail(&td->fl_list, &ftd->fl_list);

		td->link = ltd->link;
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		wmb();
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		ltd->link = cpu_to_le32(td->dma_handle);
	} else {
		td->link = uhci->fl->frame[framenum];
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		wmb();
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		uhci->fl->frame[framenum] = cpu_to_le32(td->dma_handle);
		uhci->fl->frame_cpu[framenum] = td;
	}
}

static void uhci_remove_td(struct uhci_hcd *uhci, struct uhci_td *td)
{
	/* If it's not inserted, don't remove it */
	if (td->frame == -1 && list_empty(&td->fl_list))
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		return;
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	if (td->frame != -1 && uhci->fl->frame_cpu[td->frame] == td) {
		if (list_empty(&td->fl_list)) {
			uhci->fl->frame[td->frame] = td->link;
			uhci->fl->frame_cpu[td->frame] = NULL;
		} else {
			struct uhci_td *ntd;

			ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
			uhci->fl->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
			uhci->fl->frame_cpu[td->frame] = ntd;
		}
	} else {
		struct uhci_td *ptd;

		ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
		ptd->link = td->link;
	}

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	wmb();
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	td->link = UHCI_PTR_TERM;

	list_del_init(&td->fl_list);
	td->frame = -1;
}

/*
 * Inserts a td into qh list at the top.
 */
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static void uhci_insert_tds_in_qh(struct uhci_qh *qh, struct urb *urb, u32 breadth)
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{
	struct list_head *tmp, *head;
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	struct uhci_td *td, *ptd;

	if (list_empty(&urbp->td_list))
		return;

	head = &urbp->td_list;
	tmp = head->next;

	/* Ordering isn't important here yet since the QH hasn't been */
	/*  inserted into the schedule yet */
	td = list_entry(tmp, struct uhci_td, list);

	/* Add the first TD to the QH element pointer */
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	qh->element = cpu_to_le32(td->dma_handle) | breadth;
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	ptd = td;

	/* Then link the rest of the TD's */
	tmp = tmp->next;
	while (tmp != head) {
		td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

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		ptd->link = cpu_to_le32(td->dma_handle) | breadth;
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		ptd = td;
	}

	ptd->link = UHCI_PTR_TERM;
}

static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
{
	if (!list_empty(&td->list))
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		dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
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	if (!list_empty(&td->remove_list))
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		dev_warn(uhci_dev(uhci), "td %p still in remove_list!\n", td);
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	if (!list_empty(&td->fl_list))
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		dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
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	if (td->dev)
		usb_put_dev(td->dev);

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	dma_pool_free(uhci->td_pool, td, td->dma_handle);
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}

static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci, struct usb_device *dev)
{
	dma_addr_t dma_handle;
	struct uhci_qh *qh;

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	qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
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	if (!qh)
		return NULL;

	qh->dma_handle = dma_handle;

	qh->element = UHCI_PTR_TERM;
	qh->link = UHCI_PTR_TERM;

	qh->dev = dev;
	qh->urbp = NULL;

	INIT_LIST_HEAD(&qh->list);
	INIT_LIST_HEAD(&qh->remove_list);

	usb_get_dev(dev);

	return qh;
}

static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
{
	if (!list_empty(&qh->list))
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		dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
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	if (!list_empty(&qh->remove_list))
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		dev_warn(uhci_dev(uhci), "qh %p still in remove_list!\n", qh);
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	if (qh->dev)
		usb_put_dev(qh->dev);

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	dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
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}

/*
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 * Append this urb's qh after the last qh in skelqh->list
 *
 * Note that urb_priv.queue_list doesn't have a separate queue head;
 * it's a ring with every element "live".
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 */
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static void uhci_insert_qh(struct uhci_hcd *uhci, struct uhci_qh *skelqh, struct urb *urb)
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{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
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	struct list_head *tmp;
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	struct uhci_qh *lqh;

	/* Grab the last QH */
	lqh = list_entry(skelqh->list.prev, struct uhci_qh, list);

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	/* Point to the next skelqh */
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	urbp->qh->link = lqh->link;
	wmb();				/* Ordering is important */

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	/*
	 * Patch QHs for previous endpoint's queued URBs?  HC goes
	 * here next, not to the next skelqh it now points to.
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	 *
	 *    lqh --> td ... --> qh ... --> td --> qh ... --> td
	 *     |                 |                 |
	 *     v                 v                 v
	 *     +<----------------+-----------------+
	 *     v
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	 *    newqh --> td ... --> td
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	 *     |
	 *     v
	 *    ...
	 *
	 * The HC could see (and use!) any of these as we write them.
	 */
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	lqh->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;
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	if (lqh->urbp) {
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		list_for_each (tmp, &lqh->urbp->queue_list) {
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			struct urb_priv *turbp =
				list_entry(tmp, struct urb_priv, queue_list);

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			turbp->qh->link = lqh->link;
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		}
	}

	list_add_tail(&urbp->qh->list, &skelqh->list);
}

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/*
 * Start removal of QH from schedule; it finishes next frame.
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 * TDs should be unlinked before this is called.
 */
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static void uhci_remove_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
{
	struct uhci_qh *pqh;
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	u32 newlink;
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	unsigned int age;
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	if (!qh)
		return;

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	/*
	 * Only go through the hoops if it's actually linked in
	 */
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	if (!list_empty(&qh->list)) {

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		/* If our queue is nonempty, make the next URB the head */
		if (!list_empty(&qh->urbp->queue_list)) {
			struct urb_priv *nurbp;

			nurbp = list_entry(qh->urbp->queue_list.next,
					struct urb_priv, queue_list);
			nurbp->queued = 0;
			list_add(&nurbp->qh->list, &qh->list);
			newlink = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
		} else
			newlink = qh->link;

		/* Fix up the previous QH's queue to link to either
		 * the new head of this queue or the start of the
		 * next endpoint's queue. */
		pqh = list_entry(qh->list.prev, struct uhci_qh, list);
		pqh->link = newlink;
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		if (pqh->urbp) {
			struct list_head *head, *tmp;

			head = &pqh->urbp->queue_list;
			tmp = head->next;
			while (head != tmp) {
				struct urb_priv *turbp =
					list_entry(tmp, struct urb_priv, queue_list);

				tmp = tmp->next;

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				turbp->qh->link = newlink;
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			}
		}
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		wmb();
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		/* Leave qh->link in case the HC is on the QH now, it will */
		/* continue the rest of the schedule */
		qh->element = UHCI_PTR_TERM;
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		list_del_init(&qh->list);
	}

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	list_del_init(&qh->urbp->queue_list);
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	qh->urbp = NULL;

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	age = uhci_get_current_frame_number(uhci);
	if (age != uhci->qh_remove_age) {
		uhci_free_pending_qhs(uhci);
		uhci->qh_remove_age = age;
	}

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	/* Check to see if the remove list is empty. Set the IOC bit */
	/* to force an interrupt so we can remove the QH */
	if (list_empty(&uhci->qh_remove_list))
		uhci_set_next_interrupt(uhci);

	list_add(&qh->remove_list, &uhci->qh_remove_list);
}

static int uhci_fixup_toggle(struct urb *urb, unsigned int toggle)
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	struct list_head *head, *tmp;

	head = &urbp->td_list;
	tmp = head->next;
	while (head != tmp) {
		struct uhci_td *td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

		if (toggle)
			td->token |= cpu_to_le32(TD_TOKEN_TOGGLE);
		else
			td->token &= ~cpu_to_le32(TD_TOKEN_TOGGLE);


		toggle ^= 1;
	}

	return toggle;
}

/* This function will append one URB's QH to another URB's QH. This is for */
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/* queuing interrupt, control or bulk transfers */
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static void uhci_append_queued_urb(struct uhci_hcd *uhci, struct urb *eurb, struct urb *urb)
{
	struct urb_priv *eurbp, *urbp, *furbp, *lurbp;
	struct list_head *tmp;
	struct uhci_td *lltd;

	eurbp = eurb->hcpriv;
	urbp = urb->hcpriv;

	/* Find the first URB in the queue */
	if (eurbp->queued) {
		struct list_head *head = &eurbp->queue_list;

		tmp = head->next;
		while (tmp != head) {
			struct urb_priv *turbp =
				list_entry(tmp, struct urb_priv, queue_list);

			if (!turbp->queued)
				break;

			tmp = tmp->next;
		}
	} else
		tmp = &eurbp->queue_list;

	furbp = list_entry(tmp, struct urb_priv, queue_list);
	lurbp = list_entry(furbp->queue_list.prev, struct urb_priv, queue_list);

	lltd = list_entry(lurbp->td_list.prev, struct uhci_td, list);

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	/* Control transfers always start with toggle 0 */
	if (!usb_pipecontrol(urb->pipe))
		usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
				usb_pipeout(urb->pipe),
				uhci_fixup_toggle(urb,
					uhci_toggle(td_token(lltd)) ^ 1));
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	/* All qh's in the queue need to link to the next queue */
	urbp->qh->link = eurbp->qh->link;

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	wmb();			/* Make sure we flush everything */
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	lltd->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;

	list_add_tail(&urbp->queue_list, &furbp->queue_list);

	urbp->queued = 1;
}

static void uhci_delete_queued_urb(struct uhci_hcd *uhci, struct urb *urb)
{
	struct urb_priv *urbp, *nurbp;
	struct list_head *head, *tmp;
	struct urb_priv *purbp;
	struct uhci_td *pltd;
	unsigned int toggle;

	urbp = urb->hcpriv;

	if (list_empty(&urbp->queue_list))
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		return;
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	nurbp = list_entry(urbp->queue_list.next, struct urb_priv, queue_list);

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	/*
	 * Fix up the toggle for the following URBs in the queue.
	 * Only needed for bulk and interrupt: control and isochronous
	 * endpoints don't propagate toggles between messages.
	 */
	if (usb_pipebulk(urb->pipe) || usb_pipeint(urb->pipe)) {
		if (!urbp->queued)
			/* We just set the toggle in uhci_unlink_generic */
			toggle = usb_gettoggle(urb->dev,
					usb_pipeendpoint(urb->pipe),
					usb_pipeout(urb->pipe));
		else {
			/* If we're in the middle of the queue, grab the */
			/* toggle from the TD previous to us */
			purbp = list_entry(urbp->queue_list.prev,
					struct urb_priv, queue_list);
			pltd = list_entry(purbp->td_list.prev,
					struct uhci_td, list);
			toggle = uhci_toggle(td_token(pltd)) ^ 1;
		}
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		head = &urbp->queue_list;
		tmp = head->next;
		while (head != tmp) {
			struct urb_priv *turbp;
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			turbp = list_entry(tmp, struct urb_priv, queue_list);
			tmp = tmp->next;
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			if (!turbp->queued)
				break;
			toggle = uhci_fixup_toggle(turbp->urb, toggle);
		}
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		usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
				usb_pipeout(urb->pipe), toggle);
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	}

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	if (urbp->queued) {
		/* We're somewhere in the middle (or end).  The case where
		 * we're at the head is handled in uhci_remove_qh(). */
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		purbp = list_entry(urbp->queue_list.prev, struct urb_priv,
				queue_list);

		pltd = list_entry(purbp->td_list.prev, struct uhci_td, list);
		if (nurbp->queued)
			pltd->link = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
		else
			/* The next URB happens to be the beginning, so */
			/*  we're the last, end the chain */
			pltd->link = UHCI_PTR_TERM;
	}

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	/* urbp->queue_list is handled in uhci_remove_qh() */
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}

static struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, struct urb *urb)
{
	struct urb_priv *urbp;

	urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
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	if (!urbp)
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		return NULL;

	memset((void *)urbp, 0, sizeof(*urbp));

	urbp->inserttime = jiffies;
	urbp->fsbrtime = jiffies;
	urbp->urb = urb;
	
	INIT_LIST_HEAD(&urbp->td_list);
	INIT_LIST_HEAD(&urbp->queue_list);
	INIT_LIST_HEAD(&urbp->urb_list);

	list_add_tail(&urbp->urb_list, &uhci->urb_list);

	urb->hcpriv = urbp;

	return urbp;
}

static void uhci_add_td_to_urb(struct urb *urb, struct uhci_td *td)
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;

	td->urb = urb;

	list_add_tail(&td->list, &urbp->td_list);
}

static void uhci_remove_td_from_urb(struct uhci_td *td)
{
	if (list_empty(&td->list))
		return;

	list_del_init(&td->list);

	td->urb = NULL;
}

static void uhci_destroy_urb_priv(struct uhci_hcd *uhci, struct urb *urb)
{
	struct list_head *head, *tmp;
	struct urb_priv *urbp;
642
	unsigned int age;
643 644 645 646 647 648

	urbp = (struct urb_priv *)urb->hcpriv;
	if (!urbp)
		return;

	if (!list_empty(&urbp->urb_list))
649 650
		dev_warn(uhci_dev(uhci), "urb %p still on uhci->urb_list "
				"or uhci->remove_list!\n", urb);
651

652 653 654 655 656 657
	age = uhci_get_current_frame_number(uhci);
	if (age != uhci->td_remove_age) {
		uhci_free_pending_tds(uhci);
		uhci->td_remove_age = age;
	}

658 659 660 661 662
	/* Check to see if the remove list is empty. Set the IOC bit */
	/* to force an interrupt so we can remove the TD's*/
	if (list_empty(&uhci->td_remove_list))
		uhci_set_next_interrupt(uhci);

663 664 665 666 667 668 669 670 671
	head = &urbp->td_list;
	tmp = head->next;
	while (tmp != head) {
		struct uhci_td *td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

		uhci_remove_td_from_urb(td);
		uhci_remove_td(uhci, td);
672
		list_add(&td->remove_list, &uhci->td_remove_list);
673 674 675 676 677 678 679 680 681 682
	}

	urb->hcpriv = NULL;
	kmem_cache_free(uhci_up_cachep, urbp);
}

static void uhci_inc_fsbr(struct uhci_hcd *uhci, struct urb *urb)
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;

683
	if ((!(urb->transfer_flags & URB_NO_FSBR)) && !urbp->fsbr) {
684 685
		urbp->fsbr = 1;
		if (!uhci->fsbr++ && !uhci->fsbrtimeout)
686
			uhci->skel_term_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
687 688 689 690 691 692 693
	}
}

static void uhci_dec_fsbr(struct uhci_hcd *uhci, struct urb *urb)
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;

694
	if ((!(urb->transfer_flags & URB_NO_FSBR)) && urbp->fsbr) {
695 696 697 698 699 700 701 702 703
		urbp->fsbr = 0;
		if (!--uhci->fsbr)
			uhci->fsbrtimeout = jiffies + FSBR_DELAY;
	}
}

/*
 * Map status to standard result codes
 *
704 705
 * <status> is (td->status & 0xF60000) [a.k.a. uhci_status_bits(td->status)]
 * Note: status does not include the TD_CTRL_NAK bit.
706 707 708 709 710 711 712 713 714 715
 * <dir_out> is True for output TDs and False for input TDs.
 */
static int uhci_map_status(int status, int dir_out)
{
	if (!status)
		return 0;
	if (status & TD_CTRL_BITSTUFF)			/* Bitstuff error */
		return -EPROTO;
	if (status & TD_CTRL_CRCTIMEO) {		/* CRC/Timeout */
		if (dir_out)
716
			return -EPROTO;
717 718 719 720 721 722 723 724 725
		else
			return -EILSEQ;
	}
	if (status & TD_CTRL_BABBLE)			/* Babble */
		return -EOVERFLOW;
	if (status & TD_CTRL_DBUFERR)			/* Buffer error */
		return -ENOSR;
	if (status & TD_CTRL_STALLED)			/* Stalled */
		return -EPIPE;
726 727
	WARN_ON(status & TD_CTRL_ACTIVE);		/* Active */
	return 0;
728 729 730 731 732
}

/*
 * Control transfers
 */
733
static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
734 735 736
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	struct uhci_td *td;
737
	struct uhci_qh *qh, *skelqh;
738 739 740
	unsigned long destination, status;
	int maxsze = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
	int len = urb->transfer_buffer_length;
741
	dma_addr_t data = urb->transfer_dma;
742 743 744 745 746 747 748 749 750 751

	/* The "pipe" thing contains the destination in bits 8--18 */
	destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;

	/* 3 errors */
	status = TD_CTRL_ACTIVE | uhci_maxerr(3);
	if (urb->dev->speed == USB_SPEED_LOW)
		status |= TD_CTRL_LS;

	/*
752
	 * Build the TD for the control request setup packet
753 754 755 756 757 758 759
	 */
	td = uhci_alloc_td(uhci, urb->dev);
	if (!td)
		return -ENOMEM;

	uhci_add_td_to_urb(urb, td);
	uhci_fill_td(td, status, destination | uhci_explen(7),
760
		urb->setup_dma);
761 762

	/*
763 764 765
	 * If direction is "send", change the packet ID from SETUP (0x2D)
	 * to OUT (0xE1).  Else change it from SETUP to IN (0x69) and
	 * set Short Packet Detect (SPD) for all data packets.
766
	 */
767 768 769 770
	if (usb_pipeout(urb->pipe))
		destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
	else {
		destination ^= (USB_PID_SETUP ^ USB_PID_IN);
771
		status |= TD_CTRL_SPD;
772
	}
773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829

	/*
	 * Build the DATA TD's
	 */
	while (len > 0) {
		int pktsze = len;

		if (pktsze > maxsze)
			pktsze = maxsze;

		td = uhci_alloc_td(uhci, urb->dev);
		if (!td)
			return -ENOMEM;

		/* Alternate Data0/1 (start with Data1) */
		destination ^= TD_TOKEN_TOGGLE;
	
		uhci_add_td_to_urb(urb, td);
		uhci_fill_td(td, status, destination | uhci_explen(pktsze - 1),
			data);

		data += pktsze;
		len -= pktsze;
	}

	/*
	 * Build the final TD for control status 
	 */
	td = uhci_alloc_td(uhci, urb->dev);
	if (!td)
		return -ENOMEM;

	/*
	 * It's IN if the pipe is an output pipe or we're not expecting
	 * data back.
	 */
	destination &= ~TD_TOKEN_PID_MASK;
	if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
		destination |= USB_PID_IN;
	else
		destination |= USB_PID_OUT;

	destination |= TD_TOKEN_TOGGLE;		/* End in Data1 */

	status &= ~TD_CTRL_SPD;

	uhci_add_td_to_urb(urb, td);
	uhci_fill_td(td, status | TD_CTRL_IOC,
		destination | uhci_explen(UHCI_NULL_DATA_SIZE), 0);

	qh = uhci_alloc_qh(uhci, urb->dev);
	if (!qh)
		return -ENOMEM;

	urbp->qh = qh;
	qh->urbp = urbp;

830 831
	uhci_insert_tds_in_qh(qh, urb, UHCI_PTR_BREADTH);

832
	/* Low-speed transfers get a different queue, and won't hog the bus */
833
	if (urb->dev->speed == USB_SPEED_LOW)
834
		skelqh = uhci->skel_ls_control_qh;
835
	else {
836
		skelqh = uhci->skel_fs_control_qh;
837 838 839
		uhci_inc_fsbr(uhci, urb);
	}

840 841 842 843 844
	if (eurb)
		uhci_append_queued_urb(uhci, eurb, urb);
	else
		uhci_insert_qh(uhci, skelqh, urb);

845 846 847
	return -EINPROGRESS;
}

848
/*
849 850 851 852 853 854 855
 * If control-IN transfer was short, the status packet wasn't sent.
 * This routine changes the element pointer in the QH to point at the
 * status TD.  It's safe to do this even while the QH is live, because
 * the hardware only updates the element pointer following a successful
 * transfer.  The inactive TD for the short packet won't cause an update,
 * so the pointer won't get overwritten.  The next time the controller
 * sees this QH, it will send the status packet.
856
 */
857 858 859
static int usb_control_retrigger_status(struct uhci_hcd *uhci, struct urb *urb)
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
860
	struct uhci_td *td;
861 862 863

	urbp->short_control_packet = 1;

864 865
	td = list_entry(urbp->td_list.prev, struct uhci_td, list);
	urbp->qh->element = td->dma_handle;
866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885

	return -EINPROGRESS;
}


static int uhci_result_control(struct uhci_hcd *uhci, struct urb *urb)
{
	struct list_head *tmp, *head;
	struct urb_priv *urbp = urb->hcpriv;
	struct uhci_td *td;
	unsigned int status;
	int ret = 0;

	if (list_empty(&urbp->td_list))
		return -EINVAL;

	head = &urbp->td_list;

	if (urbp->short_control_packet) {
		tmp = head->prev;
886
		goto status_stage;
887 888 889 890 891
	}

	tmp = head->next;
	td = list_entry(tmp, struct uhci_td, list);

892
	/* The first TD is the SETUP stage, check the status, but skip */
893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920
	/*  the count */
	status = uhci_status_bits(td_status(td));
	if (status & TD_CTRL_ACTIVE)
		return -EINPROGRESS;

	if (status)
		goto td_error;

	urb->actual_length = 0;

	/* The rest of the TD's (but the last) are data */
	tmp = tmp->next;
	while (tmp != head && tmp->next != head) {
		td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

		status = uhci_status_bits(td_status(td));
		if (status & TD_CTRL_ACTIVE)
			return -EINPROGRESS;

		urb->actual_length += uhci_actual_length(td_status(td));

		if (status)
			goto td_error;

		/* Check to see if we received a short packet */
		if (uhci_actual_length(td_status(td)) < uhci_expected_length(td_token(td))) {
921
			if (urb->transfer_flags & URB_SHORT_NOT_OK) {
922 923 924 925 926 927 928 929 930 931 932
				ret = -EREMOTEIO;
				goto err;
			}

			if (uhci_packetid(td_token(td)) == USB_PID_IN)
				return usb_control_retrigger_status(uhci, urb);
			else
				return 0;
		}
	}

933
status_stage:
934 935
	td = list_entry(tmp, struct uhci_td, list);

936
	/* Control status stage */
937 938 939 940 941 942 943 944 945 946 947 948
	status = td_status(td);

#ifdef I_HAVE_BUGGY_APC_BACKUPS
	/* APC BackUPS Pro kludge */
	/* It tries to send all of the descriptor instead of the amount */
	/*  we requested */
	if (status & TD_CTRL_IOC &&	/* IOC is masked out by uhci_status_bits */
	    status & TD_CTRL_ACTIVE &&
	    status & TD_CTRL_NAK)
		return 0;
#endif

949
	status = uhci_status_bits(status);
950 951 952
	if (status & TD_CTRL_ACTIVE)
		return -EINPROGRESS;

953
	if (status)
954 955 956 957 958 959 960 961 962 963
		goto td_error;

	return 0;

td_error:
	ret = uhci_map_status(status, uhci_packetout(td_token(td)));

err:
	if ((debug == 1 && ret != -EPIPE) || debug > 1) {
		/* Some debugging code */
964 965
		dev_dbg(uhci_dev(uhci), "%s: failed with status %x\n",
				__FUNCTION__, status);
966 967 968 969 970 971 972 973 974 975 976 977 978

		if (errbuf) {
			/* Print the chain for debugging purposes */
			uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);

			lprintk(errbuf);
		}
	}

	return ret;
}

/*
979
 * Common submit for bulk and interrupt
980
 */
981
static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb, struct uhci_qh *skelqh)
982 983
{
	struct uhci_td *td;
984
	struct uhci_qh *qh;
985
	unsigned long destination, status;
986 987 988 989
	int maxsze = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
	int len = urb->transfer_buffer_length;
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	dma_addr_t data = urb->transfer_dma;
990

991
	if (len < 0)
992 993 994 995 996
		return -EINVAL;

	/* The "pipe" thing contains the destination in bits 8--18 */
	destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);

997
	status = uhci_maxerr(3) | TD_CTRL_ACTIVE;
998 999
	if (urb->dev->speed == USB_SPEED_LOW)
		status |= TD_CTRL_LS;
1000
	if (usb_pipein(urb->pipe))
1001
		status |= TD_CTRL_SPD;
1002

1003 1004 1005 1006
	/*
	 * Build the DATA TD's
	 */
	do {	/* Allow zero length packets */
1007
		int pktsze = maxsze;
1008

1009 1010 1011 1012 1013
		if (pktsze >= len) {
			pktsze = len;
			if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
				status &= ~TD_CTRL_SPD;
		}
1014

1015 1016 1017
		td = uhci_alloc_td(uhci, urb->dev);
		if (!td)
			return -ENOMEM;
1018

1019 1020 1021 1022 1023
		uhci_add_td_to_urb(urb, td);
		uhci_fill_td(td, status, destination | uhci_explen(pktsze - 1) |
			(usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
			 usb_pipeout(urb->pipe)) << TD_TOKEN_TOGGLE_SHIFT),
			data);
1024

1025 1026 1027 1028 1029 1030 1031 1032
		data += pktsze;
		len -= maxsze;

		usb_dotoggle(urb->dev, usb_pipeendpoint(urb->pipe),
			usb_pipeout(urb->pipe));
	} while (len > 0);

	/*
1033
	 * URB_ZERO_PACKET means adding a 0-length packet, if direction
1034 1035 1036 1037 1038
	 * is OUT and the transfer_length was an exact multiple of maxsze,
	 * hence (len = transfer_length - N * maxsze) == 0
	 * however, if transfer_length == 0, the zero packet was already
	 * prepared above.
	 */
1039
	if (usb_pipeout(urb->pipe) && (urb->transfer_flags & URB_ZERO_PACKET) &&
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054
	    !len && urb->transfer_buffer_length) {
		td = uhci_alloc_td(uhci, urb->dev);
		if (!td)
			return -ENOMEM;

		uhci_add_td_to_urb(urb, td);
		uhci_fill_td(td, status, destination | uhci_explen(UHCI_NULL_DATA_SIZE) |
			(usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
			 usb_pipeout(urb->pipe)) << TD_TOKEN_TOGGLE_SHIFT),
			data);

		usb_dotoggle(urb->dev, usb_pipeendpoint(urb->pipe),
			usb_pipeout(urb->pipe));
	}

1055 1056 1057 1058 1059 1060 1061
	/* Set the interrupt-on-completion flag on the last packet.
	 * A more-or-less typical 4 KB URB (= size of one memory page)
	 * will require about 3 ms to transfer; that's a little on the
	 * fast side but not enough to justify delaying an interrupt
	 * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
	 * flag setting. */
	td->status |= cpu_to_le32(TD_CTRL_IOC);
1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076

	qh = uhci_alloc_qh(uhci, urb->dev);
	if (!qh)
		return -ENOMEM;

	urbp->qh = qh;
	qh->urbp = urbp;

	/* Always breadth first */
	uhci_insert_tds_in_qh(qh, urb, UHCI_PTR_BREADTH);

	if (eurb)
		uhci_append_queued_urb(uhci, eurb, urb);
	else
		uhci_insert_qh(uhci, skelqh, urb);
1077 1078 1079 1080

	return -EINPROGRESS;
}

1081 1082 1083 1084
/*
 * Common result for bulk and interrupt
 */
static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
1085 1086 1087 1088
{
	struct list_head *tmp, *head;
	struct urb_priv *urbp = urb->hcpriv;
	struct uhci_td *td;
1089
	unsigned int status = 0;
1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110
	int ret = 0;

	urb->actual_length = 0;

	head = &urbp->td_list;
	tmp = head->next;
	while (tmp != head) {
		td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

		status = uhci_status_bits(td_status(td));
		if (status & TD_CTRL_ACTIVE)
			return -EINPROGRESS;

		urb->actual_length += uhci_actual_length(td_status(td));

		if (status)
			goto td_error;

		if (uhci_actual_length(td_status(td)) < uhci_expected_length(td_token(td))) {
1111
			if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128
				ret = -EREMOTEIO;
				goto err;
			} else
				return 0;
		}
	}

	return 0;

td_error:
	ret = uhci_map_status(status, uhci_packetout(td_token(td)));
	if (ret == -EPIPE)
		/* endpoint has stalled - mark it halted */
		usb_endpoint_halt(urb->dev, uhci_endpoint(td_token(td)),
	    			uhci_packetout(td_token(td)));

err:
1129 1130 1131 1132 1133 1134 1135
	/* 
	 * Enable this chunk of code if you want to see some more debugging.
	 * But be careful, it has the tendancy to starve out khubd and prevent
	 * disconnects from happening successfully if you have a slow debug
	 * log interface (like a serial console.
	 */
#if 0
1136 1137
	if ((debug == 1 && ret != -EPIPE) || debug > 1) {
		/* Some debugging code */
1138 1139
		dev_dbg(uhci_dev(uhci), "%s: failed with status %x\n",
				__FUNCTION__, status);
1140 1141 1142

		if (errbuf) {
			/* Print the chain for debugging purposes */
1143
			uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
1144 1145 1146 1147

			lprintk(errbuf);
		}
	}
1148
#endif
1149 1150 1151
	return ret;
}

1152
static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
1153
{
1154
	int ret;
1155

1156
	/* Can't have low-speed bulk transfers */
1157 1158 1159
	if (urb->dev->speed == USB_SPEED_LOW)
		return -EINVAL;

1160 1161 1162
	ret = uhci_submit_common(uhci, urb, eurb, uhci->skel_bulk_qh);
	if (ret == -EINPROGRESS)
		uhci_inc_fsbr(uhci, urb);
1163

1164 1165
	return ret;
}
1166

1167 1168
static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
{
1169 1170 1171 1172 1173
	/* USB 1.1 interrupt transfers only involve one packet per interval;
	 * that's the uhci_submit_common() "breadth first" policy.  Drivers
	 * can submit urbs of any length, but longer ones might need many
	 * intervals to complete.
	 */
1174
	return uhci_submit_common(uhci, urb, eurb, uhci->skelqh[__interval_to_skel(urb->interval)]);
1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
}

/*
 * Isochronous transfers
 */
static int isochronous_find_limits(struct uhci_hcd *uhci, struct urb *urb, unsigned int *start, unsigned int *end)
{
	struct urb *last_urb = NULL;
	struct list_head *tmp, *head;
	int ret = 0;

	head = &uhci->urb_list;
	tmp = head->next;
	while (tmp != head) {
		struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
		struct urb *u = up->urb;

		tmp = tmp->next;

		/* look for pending URB's with identical pipe handle */
		if ((urb->pipe == u->pipe) && (urb->dev == u->dev) &&
		    (u->status == -EINPROGRESS) && (u != urb)) {
			if (!last_urb)
				*start = u->start_frame;
			last_urb = u;
		}
	}

	if (last_urb) {
1204 1205
		*end = (last_urb->start_frame + last_urb->number_of_packets *
				last_urb->interval) & (UHCI_NUMFRAMES-1);
1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
		ret = 0;
	} else
		ret = -1;	/* no previous urb found */

	return ret;
}

static int isochronous_find_start(struct uhci_hcd *uhci, struct urb *urb)
{
	int limits;
	unsigned int start = 0, end = 0;

	if (urb->number_of_packets > 900)	/* 900? Why? */
		return -EFBIG;

	limits = isochronous_find_limits(uhci, urb, &start, &end);

1223
	if (urb->transfer_flags & URB_ISO_ASAP) {
1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
		if (limits) {
			int curframe;

			curframe = uhci_get_current_frame_number(uhci) % UHCI_NUMFRAMES;
			urb->start_frame = (curframe + 10) % UHCI_NUMFRAMES;
		} else
			urb->start_frame = end;
	} else {
		urb->start_frame %= UHCI_NUMFRAMES;
		/* FIXME: Sanity check */
	}

	return 0;
}

/*
 * Isochronous transfers
 */
static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb)
{
	struct uhci_td *td;
	int i, ret, frame;
	int status, destination;

	status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
	destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);

	ret = isochronous_find_start(uhci, urb);
	if (ret)
		return ret;

	frame = urb->start_frame;
	for (i = 0; i < urb->number_of_packets; i++, frame += urb->interval) {
		if (!urb->iso_frame_desc[i].length)
			continue;

		td = uhci_alloc_td(uhci, urb->dev);
		if (!td)
			return -ENOMEM;

		uhci_add_td_to_urb(urb, td);
		uhci_fill_td(td, status, destination | uhci_explen(urb->iso_frame_desc[i].length - 1),
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			urb->transfer_dma + urb->iso_frame_desc[i].offset);
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		if (i + 1 >= urb->number_of_packets)
			td->status |= cpu_to_le32(TD_CTRL_IOC);

		uhci_insert_td_frame_list(uhci, td, frame);
	}

	return -EINPROGRESS;
}

static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
{
	struct list_head *tmp, *head;
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	int status;
	int i, ret = 0;

	urb->actual_length = 0;

	i = 0;
	head = &urbp->td_list;
	tmp = head->next;
	while (tmp != head) {
		struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
		int actlength;

		tmp = tmp->next;

		if (td_status(td) & TD_CTRL_ACTIVE)
			return -EINPROGRESS;

		actlength = uhci_actual_length(td_status(td));
		urb->iso_frame_desc[i].actual_length = actlength;
		urb->actual_length += actlength;

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		status = uhci_map_status(uhci_status_bits(td_status(td)),
				usb_pipeout(urb->pipe));
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		urb->iso_frame_desc[i].status = status;
		if (status) {
			urb->error_count++;
			ret = status;
		}

		i++;
	}

	return ret;
}

static struct urb *uhci_find_urb_ep(struct uhci_hcd *uhci, struct urb *urb)
{
	struct list_head *tmp, *head;

	/* We don't match Isoc transfers since they are special */
	if (usb_pipeisoc(urb->pipe))
		return NULL;

	head = &uhci->urb_list;
	tmp = head->next;
	while (tmp != head) {
		struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
		struct urb *u = up->urb;

		tmp = tmp->next;

		if (u->dev == urb->dev && u->status == -EINPROGRESS) {
			/* For control, ignore the direction */
			if (usb_pipecontrol(urb->pipe) &&
			    (u->pipe & ~USB_DIR_IN) == (urb->pipe & ~USB_DIR_IN))
				return u;
			else if (u->pipe == urb->pipe)
				return u;
		}
	}

	return NULL;
}

static int uhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, int mem_flags)
{
	int ret = -EINVAL;
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	unsigned long flags;
	struct urb *eurb;
	int bustime;

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	spin_lock_irqsave(&uhci->schedule_lock, flags);
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	if (urb->status != -EINPROGRESS)	/* URB already unlinked! */
		goto out;

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	eurb = uhci_find_urb_ep(uhci, urb);

	if (!uhci_alloc_urb_priv(uhci, urb)) {
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		ret = -ENOMEM;
		goto out;
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	}

	switch (usb_pipetype(urb->pipe)) {
	case PIPE_CONTROL:
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		ret = uhci_submit_control(uhci, urb, eurb);
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		break;
	case PIPE_INTERRUPT:
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		if (!eurb) {
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			bustime = usb_check_bandwidth(urb->dev, urb);
			if (bustime < 0)
				ret = bustime;
			else {
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				ret = uhci_submit_interrupt(uhci, urb, eurb);
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				if (ret == -EINPROGRESS)
					usb_claim_bandwidth(urb->dev, urb, bustime, 0);
			}
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		} else {	/* inherit from parent */
			urb->bandwidth = eurb->bandwidth;
			ret = uhci_submit_interrupt(uhci, urb, eurb);
		}
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		break;
	case PIPE_BULK:
		ret = uhci_submit_bulk(uhci, urb, eurb);
		break;
	case PIPE_ISOCHRONOUS:
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		bustime = usb_check_bandwidth(urb->dev, urb);
		if (bustime < 0) {
			ret = bustime;
			break;
		}
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		ret = uhci_submit_isochronous(uhci, urb);
		if (ret == -EINPROGRESS)
			usb_claim_bandwidth(urb->dev, urb, bustime, 1);
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		break;
	}

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	if (ret != -EINPROGRESS) {
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		/* Submit failed, so delete it from the urb_list */
		struct urb_priv *urbp = urb->hcpriv;

		list_del_init(&urbp->urb_list);
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		uhci_destroy_urb_priv(uhci, urb);
	} else
		ret = 0;
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out:
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	spin_unlock_irqrestore(&uhci->schedule_lock, flags);
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	return ret;
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}

/*
 * Return the result of a transfer
 */
static void uhci_transfer_result(struct uhci_hcd *uhci, struct urb *urb)
{
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	int ret = -EINPROGRESS;
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	struct urb_priv *urbp;

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	spin_lock(&urb->lock);
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	urbp = (struct urb_priv *)urb->hcpriv;

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	if (urb->status != -EINPROGRESS)	/* URB already dequeued */
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		goto out;

	switch (usb_pipetype(urb->pipe)) {
	case PIPE_CONTROL:
		ret = uhci_result_control(uhci, urb);
		break;
	case PIPE_BULK:
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	case PIPE_INTERRUPT:
		ret = uhci_result_common(uhci, urb);
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		break;
	case PIPE_ISOCHRONOUS:
		ret = uhci_result_isochronous(uhci, urb);
		break;
	}

	if (ret == -EINPROGRESS)
		goto out;
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	urb->status = ret;
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	switch (usb_pipetype(urb->pipe)) {
	case PIPE_CONTROL:
	case PIPE_BULK:
	case PIPE_ISOCHRONOUS:
		/* Release bandwidth for Interrupt or Isoc. transfers */
		if (urb->bandwidth)
			usb_release_bandwidth(urb->dev, urb, 1);
		uhci_unlink_generic(uhci, urb);
		break;
	case PIPE_INTERRUPT:
		/* Release bandwidth for Interrupt or Isoc. transfers */
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		/* Make sure we don't release if we have a queued URB */
		if (list_empty(&urbp->queue_list) && urb->bandwidth)
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			usb_release_bandwidth(urb->dev, urb, 0);
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		else
			/* bandwidth was passed on to queued URB, */
			/* so don't let usb_unlink_urb() release it */
			urb->bandwidth = 0;
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		uhci_unlink_generic(uhci, urb);
		break;
	default:
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		dev_info(uhci_dev(uhci), "%s: unknown pipe type %d "
				"for urb %p\n",
				__FUNCTION__, usb_pipetype(urb->pipe), urb);
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	}

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	/* Move it from uhci->urb_list to uhci->complete_list */
	uhci_moveto_complete(uhci, urbp);
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out:
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	spin_unlock(&urb->lock);
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}

static void uhci_unlink_generic(struct uhci_hcd *uhci, struct urb *urb)
{
	struct list_head *head, *tmp;
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	int prevactive = 1;

	uhci_dec_fsbr(uhci, urb);	/* Safe since it checks */

	/*
	 * Now we need to find out what the last successful toggle was
	 * so we can update the local data toggle for the next transfer
	 *
	 * There's 3 way's the last successful completed TD is found:
	 *
	 * 1) The TD is NOT active and the actual length < expected length
	 * 2) The TD is NOT active and it's the last TD in the chain
	 * 3) The TD is active and the previous TD is NOT active
	 *
	 * Control and Isochronous ignore the toggle, so this is safe
	 * for all types
	 */
	head = &urbp->td_list;
	tmp = head->next;
	while (tmp != head) {
		struct uhci_td *td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

		if (!(td_status(td) & TD_CTRL_ACTIVE) &&
		    (uhci_actual_length(td_status(td)) < uhci_expected_length(td_token(td)) ||
		    tmp == head))
			usb_settoggle(urb->dev, uhci_endpoint(td_token(td)),
				uhci_packetout(td_token(td)),
				uhci_toggle(td_token(td)) ^ 1);
		else if ((td_status(td) & TD_CTRL_ACTIVE) && !prevactive)
			usb_settoggle(urb->dev, uhci_endpoint(td_token(td)),
				uhci_packetout(td_token(td)),
				uhci_toggle(td_token(td)));

		prevactive = td_status(td) & TD_CTRL_ACTIVE;
	}

	uhci_delete_queued_urb(uhci, urb);

	/* The interrupt loop will reclaim the QH's */
	uhci_remove_qh(uhci, urbp->qh);
	urbp->qh = NULL;
}

static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	unsigned long flags;
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	struct urb_priv *urbp;
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	unsigned int age;
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	spin_lock_irqsave(&uhci->schedule_lock, flags);
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	urbp = urb->hcpriv;
	if (!urbp)			/* URB was never linked! */
		goto done;
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	list_del_init(&urbp->urb_list);

	uhci_unlink_generic(uhci, urb);

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	age = uhci_get_current_frame_number(uhci);
	if (age != uhci->urb_remove_age) {
		uhci_remove_pending_urbps(uhci);
		uhci->urb_remove_age = age;
	}

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	/* If we're the first, set the next interrupt bit */
	if (list_empty(&uhci->urb_remove_list))
		uhci_set_next_interrupt(uhci);
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	list_add_tail(&urbp->urb_list, &uhci->urb_remove_list);
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done:
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	spin_unlock_irqrestore(&uhci->schedule_lock, flags);
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	return 0;
}

static int uhci_fsbr_timeout(struct uhci_hcd *uhci, struct urb *urb)
{
	struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
	struct list_head *head, *tmp;
	int count = 0;

	uhci_dec_fsbr(uhci, urb);

	urbp->fsbr_timeout = 1;

	/*
	 * Ideally we would want to fix qh->element as well, but it's
	 * read/write by the HC, so that can introduce a race. It's not
	 * really worth the hassle
	 */

	head = &urbp->td_list;
	tmp = head->next;
	while (tmp != head) {
		struct uhci_td *td = list_entry(tmp, struct uhci_td, list);

		tmp = tmp->next;

		/*
		 * Make sure we don't do the last one (since it'll have the
		 * TERM bit set) as well as we skip every so many TD's to
		 * make sure it doesn't hog the bandwidth
		 */
		if (tmp != head && (count % DEPTH_INTERVAL) == (DEPTH_INTERVAL - 1))
			td->link |= UHCI_PTR_DEPTH;

		count++;
	}

	return 0;
}

/*
 * uhci_get_current_frame_number()
 *
 * returns the current frame number for a USB bus/controller.
 */
static int uhci_get_current_frame_number(struct uhci_hcd *uhci)
{
	return inw(uhci->io_addr + USBFRNUM);
}

static int init_stall_timer(struct usb_hcd *hcd);

static void stall_callback(unsigned long ptr)
{
	struct usb_hcd *hcd = (struct usb_hcd *)ptr;
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	struct list_head list, *tmp, *head;
	unsigned long flags;
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	int called_uhci_finish_completion = 0;
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	INIT_LIST_HEAD(&list);

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	spin_lock_irqsave(&uhci->schedule_lock, flags);
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	if (!list_empty(&uhci->urb_remove_list) &&
	    uhci_get_current_frame_number(uhci) != uhci->urb_remove_age) {
		uhci_remove_pending_urbps(uhci);
		uhci_finish_completion(hcd, NULL);
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		called_uhci_finish_completion = 1;
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	}

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	head = &uhci->urb_list;
	tmp = head->next;
	while (tmp != head) {
		struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
		struct urb *u = up->urb;

		tmp = tmp->next;

		spin_lock(&u->lock);

		/* Check if the FSBR timed out */
		if (up->fsbr && !up->fsbr_timeout && time_after_eq(jiffies, up->fsbrtime + IDLE_TIMEOUT))
			uhci_fsbr_timeout(uhci, u);

		/* Check if the URB timed out */
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		if (u->timeout && u->status == -EINPROGRESS &&
			time_after_eq(jiffies, up->inserttime + u->timeout)) {
			u->status = -ETIMEDOUT;
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			list_move_tail(&up->urb_list, &list);
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		}
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		spin_unlock(&u->lock);
	}
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	spin_unlock_irqrestore(&uhci->schedule_lock, flags);
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	/* Wake up anyone waiting for an URB to complete */
	if (called_uhci_finish_completion)
		wake_up_all(&uhci->waitqh);

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	head = &list;
	tmp = head->next;
	while (tmp != head) {
		struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
		struct urb *u = up->urb;

		tmp = tmp->next;

		uhci_urb_dequeue(hcd, u);
	}

	/* Really disable FSBR */
	if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) {
		uhci->fsbrtimeout = 0;
		uhci->skel_term_qh->link = UHCI_PTR_TERM;
	}

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	/* Poll for and perform state transitions */
	hc_state_transitions(uhci);
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	init_stall_timer(hcd);
}

static int init_stall_timer(struct usb_hcd *hcd)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

	init_timer(&uhci->stall_timer);
	uhci->stall_timer.function = stall_callback;
	uhci->stall_timer.data = (unsigned long)hcd;
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	uhci->stall_timer.expires = jiffies + msecs_to_jiffies(100);
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	add_timer(&uhci->stall_timer);

	return 0;
}

static void uhci_free_pending_qhs(struct uhci_hcd *uhci)
{
	struct list_head *tmp, *head;

	head = &uhci->qh_remove_list;
	tmp = head->next;
	while (tmp != head) {
		struct uhci_qh *qh = list_entry(tmp, struct uhci_qh, remove_list);

		tmp = tmp->next;

		list_del_init(&qh->remove_list);

		uhci_free_qh(uhci, qh);
	}
}

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static void uhci_free_pending_tds(struct uhci_hcd *uhci)
{
	struct list_head *tmp, *head;

	head = &uhci->td_remove_list;
	tmp = head->next;
	while (tmp != head) {
		struct uhci_td *td = list_entry(tmp, struct uhci_td, remove_list);

		tmp = tmp->next;

		list_del_init(&td->remove_list);

		uhci_free_td(uhci, td);
	}
}

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static void uhci_finish_urb(struct usb_hcd *hcd, struct urb *urb, struct pt_regs *regs)
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{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

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	uhci_destroy_urb_priv(uhci, urb);
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	spin_unlock(&uhci->schedule_lock);
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	usb_hcd_giveback_urb(hcd, urb, regs);
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	spin_lock(&uhci->schedule_lock);
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}

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static void uhci_finish_completion(struct usb_hcd *hcd, struct pt_regs *regs)
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{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	struct list_head *tmp, *head;

	head = &uhci->complete_list;
	tmp = head->next;
	while (tmp != head) {
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		struct urb_priv *urbp = list_entry(tmp, struct urb_priv, urb_list);
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		struct urb *urb = urbp->urb;

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		list_del_init(&urbp->urb_list);
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		uhci_finish_urb(hcd, urb, regs);
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		head = &uhci->complete_list;
		tmp = head->next;
	}
}

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static void uhci_remove_pending_urbps(struct uhci_hcd *uhci)
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{

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	/* Splice the urb_remove_list onto the end of the complete_list */
	list_splice_init(&uhci->urb_remove_list, uhci->complete_list.prev);
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}

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static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
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{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
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	unsigned long io_addr = uhci->io_addr;
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	unsigned short status;
	struct list_head *tmp, *head;
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	unsigned int age;
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	/*
	 * Read the interrupt status, and write it back to clear the
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	 * interrupt cause.  Contrary to the UHCI specification, the
	 * "HC Halted" status bit is persistent: it is RO, not R/WC.
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	 */
	status = inw(io_addr + USBSTS);
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	if (!(status & ~USBSTS_HCH))	/* shared interrupt, not mine */
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		return IRQ_NONE;
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	outw(status, io_addr + USBSTS);		/* Clear it */

	if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
		if (status & USBSTS_HSE)
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			dev_err(uhci_dev(uhci), "host system error, "
					"PCI problems?\n");
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		if (status & USBSTS_HCPE)
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			dev_err(uhci_dev(uhci), "host controller process "
					"error, something bad happened!\n");
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		if ((status & USBSTS_HCH) && uhci->state > 0) {
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			dev_err(uhci_dev(uhci), "host controller halted, "
					"very bad!\n");
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			/* FIXME: Reset the controller, fix the offending TD */
		}
	}

	if (status & USBSTS_RD)
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		uhci->resume_detect = 1;
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	spin_lock(&uhci->schedule_lock);
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	age = uhci_get_current_frame_number(uhci);
	if (age != uhci->qh_remove_age)
		uhci_free_pending_qhs(uhci);
	if (age != uhci->td_remove_age)
		uhci_free_pending_tds(uhci);
	if (age != uhci->urb_remove_age)
		uhci_remove_pending_urbps(uhci);

	if (list_empty(&uhci->urb_remove_list) &&
	    list_empty(&uhci->td_remove_list) &&
	    list_empty(&uhci->qh_remove_list))
		uhci_clear_next_interrupt(uhci);
	else
		uhci_set_next_interrupt(uhci);
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	/* Walk the list of pending URB's to see which ones completed */
	head = &uhci->urb_list;
	tmp = head->next;
	while (tmp != head) {
		struct urb_priv *urbp = list_entry(tmp, struct urb_priv, urb_list);
		struct urb *urb = urbp->urb;

		tmp = tmp->next;

		/* Checks the status and does all of the magic necessary */
		uhci_transfer_result(uhci, urb);
	}
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	uhci_finish_completion(hcd, regs);
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	spin_unlock(&uhci->schedule_lock);

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	/* Wake up anyone waiting for an URB to complete */
	wake_up_all(&uhci->waitqh);

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	return IRQ_HANDLED;
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}

static void reset_hc(struct uhci_hcd *uhci)
{
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	unsigned long io_addr = uhci->io_addr;
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1840 1841 1842 1843 1844 1845
	/* Turn off PIRQ, SMI, and all interrupts.  This also turns off
	 * the BIOS's USB Legacy Support.
	 */
	pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
	outw(0, uhci->io_addr + USBINTR);

1846
	/* Global reset for 50ms */
1847
	uhci->state = UHCI_RESET;
1848
	outw(USBCMD_GRESET, io_addr + USBCMD);
1849
	msleep(50);
1850
	outw(0, io_addr + USBCMD);
1851 1852

	/* Another 10ms delay */
1853
	msleep(10);
1854
	uhci->resume_detect = 0;
1855 1856 1857 1858
}

static void suspend_hc(struct uhci_hcd *uhci)
{
1859
	unsigned long io_addr = uhci->io_addr;
1860

1861
	dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
1862 1863
	uhci->state = UHCI_SUSPENDED;
	uhci->resume_detect = 0;
1864
	outw(USBCMD_EGSM, io_addr + USBCMD);
1865 1866 1867 1868
}

static void wakeup_hc(struct uhci_hcd *uhci)
{
1869
	unsigned long io_addr = uhci->io_addr;
1870

1871 1872
	switch (uhci->state) {
		case UHCI_SUSPENDED:		/* Start the resume */
1873
			dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
1874

1875 1876 1877
			/* Global resume for >= 20ms */
			outw(USBCMD_FGR | USBCMD_EGSM, io_addr + USBCMD);
			uhci->state = UHCI_RESUMING_1;
1878
			uhci->state_end = jiffies + msecs_to_jiffies(20);
1879
			break;
1880

1881 1882 1883 1884
		case UHCI_RESUMING_1:		/* End global resume */
			uhci->state = UHCI_RESUMING_2;
			outw(0, io_addr + USBCMD);
			/* Falls through */
1885

1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904
		case UHCI_RESUMING_2:		/* Wait for EOP to be sent */
			if (inw(io_addr + USBCMD) & USBCMD_FGR)
				break;

			/* Run for at least 1 second, and
			 * mark it configured with a 64-byte max packet */
			uhci->state = UHCI_RUNNING_GRACE;
			uhci->state_end = jiffies + HZ;
			outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP,
					io_addr + USBCMD);
			break;

		case UHCI_RUNNING_GRACE:	/* Now allowed to suspend */
			uhci->state = UHCI_RUNNING;
			break;

		default:
			break;
	}
1905 1906 1907 1908
}

static int ports_active(struct uhci_hcd *uhci)
{
1909
	unsigned long io_addr = uhci->io_addr;
1910 1911 1912 1913
	int connection = 0;
	int i;

	for (i = 0; i < uhci->rh_numports; i++)
1914
		connection |= (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_CCS);
1915 1916 1917 1918

	return connection;
}

1919 1920
static int suspend_allowed(struct uhci_hcd *uhci)
{
1921
	unsigned long io_addr = uhci->io_addr;
1922 1923
	int i;

1924
	if (to_pci_dev(uhci_dev(uhci))->vendor != PCI_VENDOR_ID_INTEL)
1925 1926
		return 1;

1927 1928 1929 1930
	/* Some of Intel's USB controllers have a bug that causes false
	 * resume indications if any port has an over current condition.
	 * To prevent problems, we will not allow a global suspend if
	 * any ports are OC.
1931
	 *
1932 1933 1934
	 * Some motherboards using Intel's chipsets (but not using all
	 * the USB ports) appear to hardwire the over current inputs active
	 * to disable the USB ports.
1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
	 */

	/* check for over current condition on any port */
	for (i = 0; i < uhci->rh_numports; i++) {
		if (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_OC)
			return 0;
	}

	return 1;
}

static void hc_state_transitions(struct uhci_hcd *uhci)
{
	switch (uhci->state) {
		case UHCI_RUNNING:

			/* global suspend if nothing connected for 1 second */
			if (!ports_active(uhci) && suspend_allowed(uhci)) {
				uhci->state = UHCI_SUSPENDING_GRACE;
				uhci->state_end = jiffies + HZ;
			}
			break;

		case UHCI_SUSPENDING_GRACE:
			if (ports_active(uhci))
				uhci->state = UHCI_RUNNING;
			else if (time_after_eq(jiffies, uhci->state_end))
				suspend_hc(uhci);
			break;

		case UHCI_SUSPENDED:

			/* wakeup if requested by a device */
			if (uhci->resume_detect)
				wakeup_hc(uhci);
			break;

		case UHCI_RESUMING_1:
		case UHCI_RESUMING_2:
		case UHCI_RUNNING_GRACE:
			if (time_after_eq(jiffies, uhci->state_end))
				wakeup_hc(uhci);
			break;

		default:
			break;
	}
}

1984 1985
static void start_hc(struct uhci_hcd *uhci)
{
1986
	unsigned long io_addr = uhci->io_addr;
1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997
	int timeout = 1000;

	/*
	 * Reset the HC - this will force us to get a
	 * new notification of any already connected
	 * ports due to the virtual disconnect that it
	 * implies.
	 */
	outw(USBCMD_HCRESET, io_addr + USBCMD);
	while (inw(io_addr + USBCMD) & USBCMD_HCRESET) {
		if (!--timeout) {
1998
			dev_err(uhci_dev(uhci), "USBCMD_HCRESET timed out!\n");
1999 2000 2001 2002
			break;
		}
	}

2003 2004 2005
	/* Turn on PIRQ and all interrupts */
	pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
			USBLEGSUP_DEFAULT);
2006 2007 2008 2009 2010 2011 2012 2013
	outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
		io_addr + USBINTR);

	/* Start at frame 0 */
	outw(0, io_addr + USBFRNUM);
	outl(uhci->fl->dma_handle, io_addr + USBFLBASEADD);

	/* Run and mark it configured with a 64-byte max packet */
2014 2015
	uhci->state = UHCI_RUNNING_GRACE;
	uhci->state_end = jiffies + HZ;
2016
	outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, io_addr + USBCMD);
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2017

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David Brownell committed
2018
        uhci->hcd.state = USB_STATE_RUNNING;
2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033
}

/*
 * De-allocate all resources..
 */
static void release_uhci(struct uhci_hcd *uhci)
{
	int i;

	for (i = 0; i < UHCI_NUM_SKELQH; i++)
		if (uhci->skelqh[i]) {
			uhci_free_qh(uhci, uhci->skelqh[i]);
			uhci->skelqh[i] = NULL;
		}

2034 2035 2036 2037
	if (uhci->term_td) {
		uhci_free_td(uhci, uhci->term_td);
		uhci->term_td = NULL;
	}
2038 2039

	if (uhci->qh_pool) {
2040
		dma_pool_destroy(uhci->qh_pool);
2041 2042 2043 2044
		uhci->qh_pool = NULL;
	}

	if (uhci->td_pool) {
2045
		dma_pool_destroy(uhci->td_pool);
2046 2047 2048 2049
		uhci->td_pool = NULL;
	}

	if (uhci->fl) {
2050 2051
		dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl),
				uhci->fl, uhci->fl->dma_handle);
2052 2053 2054 2055 2056
		uhci->fl = NULL;
	}

#ifdef CONFIG_PROC_FS
	if (uhci->proc_entry) {
2057
		remove_proc_entry(uhci->hcd.self.bus_name, uhci_proc_root);
2058 2059 2060 2061 2062
		uhci->proc_entry = NULL;
	}
#endif
}

2063 2064 2065 2066 2067 2068
static int uhci_reset(struct usb_hcd *hcd)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

	uhci->io_addr = (unsigned long) hcd->regs;

2069
	/* Kick BIOS off this hardware and reset, so we won't get
2070 2071 2072 2073 2074 2075
	 * interrupts from any previous setup.
	 */
	reset_hc(uhci);
	return 0;
}

2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086
/*
 * Allocate a frame list, and then setup the skeleton
 *
 * The hardware doesn't really know any difference
 * in the queues, but the order does matter for the
 * protocols higher up. The order is:
 *
 *  - any isochronous events handled before any
 *    of the queues. We don't do that here, because
 *    we'll create the actual TD entries on demand.
 *  - The first queue is the interrupt queue.
2087
 *  - The second queue is the control queue, split into low- and full-speed
2088 2089
 *  - The third queue is bulk queue.
 *  - The fourth queue is the bandwidth reclamation queue, which loops back
2090
 *    to the full-speed control queue.
2091
 */
2092
static int uhci_start(struct usb_hcd *hcd)
2093 2094 2095 2096
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	int retval = -EBUSY;
	int i, port;
2097
	unsigned io_size;
2098
	dma_addr_t dma_handle;
2099
	struct usb_device *udev;
2100 2101 2102 2103
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *ent;
#endif

2104
	io_size = pci_resource_len(to_pci_dev(uhci_dev(uhci)), hcd->region);
2105 2106

#ifdef CONFIG_PROC_FS
2107
	ent = create_proc_entry(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, uhci_proc_root);
2108
	if (!ent) {
2109
		dev_err(uhci_dev(uhci), "couldn't create uhci proc entry\n");
2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122
		retval = -ENOMEM;
		goto err_create_proc_entry;
	}

	ent->data = uhci;
	ent->proc_fops = &uhci_proc_operations;
	ent->size = 0;
	uhci->proc_entry = ent;
#endif

	uhci->fsbr = 0;
	uhci->fsbrtimeout = 0;

2123
	spin_lock_init(&uhci->schedule_lock);
2124 2125
	INIT_LIST_HEAD(&uhci->qh_remove_list);

2126 2127
	INIT_LIST_HEAD(&uhci->td_remove_list);

2128 2129 2130 2131 2132 2133
	INIT_LIST_HEAD(&uhci->urb_remove_list);

	INIT_LIST_HEAD(&uhci->urb_list);

	INIT_LIST_HEAD(&uhci->complete_list);

2134 2135
	init_waitqueue_head(&uhci->waitqh);

2136 2137
	uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl),
			&dma_handle, 0);
2138
	if (!uhci->fl) {
2139 2140
		dev_err(uhci_dev(uhci), "unable to allocate "
				"consistent memory for frame list\n");
2141 2142 2143 2144 2145 2146 2147
		goto err_alloc_fl;
	}

	memset((void *)uhci->fl, 0, sizeof(*uhci->fl));

	uhci->fl->dma_handle = dma_handle;

2148 2149
	uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
			sizeof(struct uhci_td), 16, 0);
2150
	if (!uhci->td_pool) {
2151
		dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
2152 2153 2154
		goto err_create_td_pool;
	}

2155 2156
	uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
			sizeof(struct uhci_qh), 16, 0);
2157
	if (!uhci->qh_pool) {
2158
		dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
2159 2160 2161 2162 2163 2164 2165 2166 2167
		goto err_create_qh_pool;
	}

	/* Initialize the root hub */

	/* UHCI specs says devices must have 2 ports, but goes on to say */
	/*  they may have more but give no way to determine how many they */
	/*  have. However, according to the UHCI spec, Bit 7 is always set */
	/*  to 1. So we try to use this to our advantage */
2168
	for (port = 0; port < (io_size - 0x10) / 2; port++) {
2169 2170 2171 2172 2173 2174 2175
		unsigned int portstatus;

		portstatus = inw(uhci->io_addr + 0x10 + (port * 2));
		if (!(portstatus & 0x0080))
			break;
	}
	if (debug)
2176
		dev_info(uhci_dev(uhci), "detected %d ports\n", port);
2177 2178 2179

	/* This is experimental so anything less than 2 or greater than 8 is */
	/*  something weird and we'll ignore it */
2180
	if (port < 2 || port > UHCI_RH_MAXCHILD) {
2181 2182
		dev_info(uhci_dev(uhci), "port count misdetected? "
				"forcing to 2 ports\n");
2183 2184 2185 2186 2187
		port = 2;
	}

	uhci->rh_numports = port;

2188
	udev = usb_alloc_dev(NULL, &hcd->self, 0);
2189
	if (!udev) {
2190
		dev_err(uhci_dev(uhci), "unable to allocate root hub\n");
2191 2192 2193
		goto err_alloc_root_hub;
	}

2194 2195
	uhci->term_td = uhci_alloc_td(uhci, udev);
	if (!uhci->term_td) {
2196
		dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
2197
		goto err_alloc_term_td;
2198 2199 2200
	}

	for (i = 0; i < UHCI_NUM_SKELQH; i++) {
2201
		uhci->skelqh[i] = uhci_alloc_qh(uhci, udev);
2202
		if (!uhci->skelqh[i]) {
2203
			dev_err(uhci_dev(uhci), "unable to allocate QH\n");
2204 2205 2206 2207
			goto err_alloc_skelqh;
		}
	}

2208
	/*
2209
	 * 8 Interrupt queues; link all higher int queues to int1,
2210 2211
	 * then link int1 to control and control to bulk
	 */
2212 2213 2214 2215 2216 2217 2218 2219
	uhci->skel_int128_qh->link =
			uhci->skel_int64_qh->link =
			uhci->skel_int32_qh->link =
			uhci->skel_int16_qh->link =
			uhci->skel_int8_qh->link =
			uhci->skel_int4_qh->link =
			uhci->skel_int2_qh->link =
			cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH;
2220
	uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH;
2221

2222 2223
	uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
	uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH;
2224 2225 2226
	uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH;

	/* This dummy TD is to work around a bug in Intel PIIX controllers */
2227
	uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) |
2228
		(0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
2229
	uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
2230 2231

	uhci->skel_term_qh->link = UHCI_PTR_TERM;
2232
	uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
2233 2234

	/*
2235 2236
	 * Fill the frame list: make all entries point to the proper
	 * interrupt queue.
2237
	 *
2238 2239 2240 2241 2242 2243
	 * The interrupt queues will be interleaved as evenly as possible.
	 * There's not much to be done about period-1 interrupts; they have
	 * to occur in every frame.  But we can schedule period-2 interrupts
	 * in odd-numbered frames, period-4 interrupts in frames congruent
	 * to 2 (mod 4), and so on.  This way each frame only has two
	 * interrupt QHs, which will help spread out bandwidth utilization.
2244 2245
	 */
	for (i = 0; i < UHCI_NUMFRAMES; i++) {
2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258
		int irq;

		/*
		 * ffs (Find First bit Set) does exactly what we need:
		 * 1,3,5,...  => ffs = 0 => use skel_int2_qh = skelqh[6],
		 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc.
		 * ffs > 6 => not on any high-period queue, so use
		 *	skel_int1_qh = skelqh[7].
		 * Add UHCI_NUMFRAMES to insure at least one bit is set.
		 */
		irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES);
		if (irq < 0)
			irq = 7;
2259 2260

		/* Only place we don't use the frame list routines */
2261
		uhci->fl->frame[i] = cpu_to_le32(uhci->skelqh[irq]->dma_handle);
2262 2263
	}

2264 2265 2266 2267 2268
	/*
	 * Some architectures require a full mb() to enforce completion of
	 * the memory writes above before the I/O transfers in start_hc().
	 */
	mb();
2269 2270 2271 2272
	start_hc(uhci);

	init_stall_timer(hcd);

2273
	udev->speed = USB_SPEED_FULL;
2274

2275
	if (hcd_register_root(udev, &uhci->hcd) != 0) {
2276
		dev_err(uhci_dev(uhci), "unable to start root hub\n");
2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288
		retval = -ENOMEM;
		goto err_start_root_hub;
	}

	return 0;

/*
 * error exits:
 */
err_start_root_hub:
	reset_hc(uhci);

2289
	del_timer_sync(&uhci->stall_timer);
2290

2291
err_alloc_skelqh:
2292 2293 2294 2295 2296 2297
	for (i = 0; i < UHCI_NUM_SKELQH; i++)
		if (uhci->skelqh[i]) {
			uhci_free_qh(uhci, uhci->skelqh[i]);
			uhci->skelqh[i] = NULL;
		}

2298 2299
	uhci_free_td(uhci, uhci->term_td);
	uhci->term_td = NULL;
2300

2301
err_alloc_term_td:
2302
	usb_put_dev(udev);
2303 2304

err_alloc_root_hub:
2305
	dma_pool_destroy(uhci->qh_pool);
2306 2307 2308
	uhci->qh_pool = NULL;

err_create_qh_pool:
2309
	dma_pool_destroy(uhci->td_pool);
2310 2311 2312
	uhci->td_pool = NULL;

err_create_td_pool:
2313 2314
	dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl),
			uhci->fl, uhci->fl->dma_handle);
2315 2316 2317 2318
	uhci->fl = NULL;

err_alloc_fl:
#ifdef CONFIG_PROC_FS
2319
	remove_proc_entry(hcd->self.bus_name, uhci_proc_root);
2320 2321 2322 2323 2324 2325 2326 2327
	uhci->proc_entry = NULL;

err_create_proc_entry:
#endif

	return retval;
}

2328
static void uhci_stop(struct usb_hcd *hcd)
2329 2330 2331
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

2332
	del_timer_sync(&uhci->stall_timer);
2333 2334 2335 2336 2337

	/*
	 * At this point, we're guaranteed that no new connects can be made
	 * to this bus since there are no more parents
	 */
2338 2339 2340

	reset_hc(uhci);

2341
	spin_lock_irq(&uhci->schedule_lock);
2342
	uhci_free_pending_qhs(uhci);
2343
	uhci_free_pending_tds(uhci);
2344
	uhci_remove_pending_urbps(uhci);
2345
	uhci_finish_completion(hcd, NULL);
2346 2347

	uhci_free_pending_qhs(uhci);
2348
	uhci_free_pending_tds(uhci);
2349
	spin_unlock_irq(&uhci->schedule_lock);
2350 2351 2352

	/* Wake up anyone waiting for an URB to complete */
	wake_up_all(&uhci->waitqh);
2353
	
2354 2355 2356 2357 2358 2359 2360 2361
	release_uhci(uhci);
}

#ifdef CONFIG_PM
static int uhci_suspend(struct usb_hcd *hcd, u32 state)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

2362
	/* Don't try to suspend broken motherboards, reset instead */
2363
	if (suspend_allowed(uhci)) {
2364
		suspend_hc(uhci);
2365 2366 2367
		uhci->saved_framenumber =
				inw(uhci->io_addr + USBFRNUM) & 0x3ff;
	} else
2368
		reset_hc(uhci);
2369 2370 2371 2372 2373 2374 2375
	return 0;
}

static int uhci_resume(struct usb_hcd *hcd)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

2376
	pci_set_master(to_pci_dev(uhci_dev(uhci)));
2377

2378 2379 2380
	if (uhci->state == UHCI_SUSPENDED) {

		/*
2381 2382
		 * Some systems don't maintain the UHCI register values
		 * during a PM suspend/resume cycle, so reinitialize
2383 2384
		 * the Frame Number, Framelist Base Address, Interrupt
		 * Enable, and Legacy Support registers.
2385
		 */
2386 2387
		pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
				0);
2388 2389
		outw(uhci->saved_framenumber, uhci->io_addr + USBFRNUM);
		outl(uhci->fl->dma_handle, uhci->io_addr + USBFLBASEADD);
2390 2391
		outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC |
				USBINTR_SP, uhci->io_addr + USBINTR);
2392
		uhci->resume_detect = 1;
2393 2394
		pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
				USBLEGSUP_DEFAULT);
2395
	} else {
2396 2397 2398
		reset_hc(uhci);
		start_hc(uhci);
	}
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David Brownell committed
2399
	uhci->hcd.state = USB_STATE_RUNNING;
2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412
	return 0;
}
#endif

static struct usb_hcd *uhci_hcd_alloc(void)
{
	struct uhci_hcd *uhci;

	uhci = (struct uhci_hcd *)kmalloc(sizeof(*uhci), GFP_KERNEL);
	if (!uhci)
		return NULL;

	memset(uhci, 0, sizeof(*uhci));
2413
	uhci->hcd.product_desc = "UHCI Host Controller";
2414 2415 2416 2417 2418 2419 2420 2421
	return &uhci->hcd;
}

static void uhci_hcd_free(struct usb_hcd *hcd)
{
	kfree(hcd_to_uhci(hcd));
}

2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461
/* Are there any URBs for a particular device/endpoint on a given list? */
static int urbs_for_ep_list(struct list_head *head,
		struct hcd_dev *hdev, int ep)
{
	struct urb_priv *urbp;

	list_for_each_entry(urbp, head, urb_list) {
		struct urb *urb = urbp->urb;

		if (hdev == urb->dev->hcpriv && ep ==
				(usb_pipeendpoint(urb->pipe) |
				 usb_pipein(urb->pipe)))
			return 1;
	}
	return 0;
}

/* Are there any URBs for a particular device/endpoint? */
static int urbs_for_ep(struct uhci_hcd *uhci, struct hcd_dev *hdev, int ep)
{
	int rc;

	spin_lock_irq(&uhci->schedule_lock);
	rc = (urbs_for_ep_list(&uhci->urb_list, hdev, ep) ||
			urbs_for_ep_list(&uhci->complete_list, hdev, ep) ||
			urbs_for_ep_list(&uhci->urb_remove_list, hdev, ep));
	spin_unlock_irq(&uhci->schedule_lock);
	return rc;
}

/* Wait until all the URBs for a particular device/endpoint are gone */
static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
		struct hcd_dev *hdev, int endpoint)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);

	wait_event_interruptible(uhci->waitqh,
			!urbs_for_ep(uhci, hdev, endpoint));
}

2462 2463 2464 2465 2466
static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
{
	return uhci_get_current_frame_number(hcd_to_uhci(hcd));
}

2467
static const char hcd_name[] = "uhci_hcd";
2468 2469

static const struct hc_driver uhci_driver = {
2470
	.description =		hcd_name,
2471 2472

	/* Generic hardware linkage */
2473 2474
	.irq =			uhci_irq,
	.flags =		HCD_USB11,
2475 2476

	/* Basic lifecycle operations */
2477
	.reset =		uhci_reset,
2478
	.start =		uhci_start,
2479
#ifdef CONFIG_PM
2480 2481
	.suspend =		uhci_suspend,
	.resume =		uhci_resume,
2482
#endif
2483
	.stop =			uhci_stop,
2484

2485 2486
	.hcd_alloc =		uhci_hcd_alloc,
	.hcd_free =		uhci_hcd_free,
2487

2488 2489
	.urb_enqueue =		uhci_urb_enqueue,
	.urb_dequeue =		uhci_urb_dequeue,
2490

2491
	.endpoint_disable =	uhci_hcd_endpoint_disable,
2492
	.get_frame_number =	uhci_hcd_get_frame_number,
2493

2494 2495
	.hub_status_data =	uhci_hub_status_data,
	.hub_control =		uhci_hub_control,
2496 2497
};

2498
static const struct pci_device_id uhci_pci_ids[] = { {
2499
	/* handle any USB UHCI controller */
2500
	PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0),
2501
	.driver_data =	(unsigned long) &uhci_driver,
2502 2503 2504 2505 2506 2507
	}, { /* end: all zeroes */ }
};

MODULE_DEVICE_TABLE(pci, uhci_pci_ids);

static struct pci_driver uhci_pci_driver = {
2508 2509
	.name =		(char *)hcd_name,
	.id_table =	uhci_pci_ids,
2510

2511 2512
	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,
2513 2514

#ifdef	CONFIG_PM
2515 2516
	.suspend =	usb_hcd_pci_suspend,
	.resume =	usb_hcd_pci_resume,
2517 2518 2519 2520 2521 2522 2523
#endif	/* PM */
};
 
static int __init uhci_hcd_init(void)
{
	int retval = -ENOMEM;

2524
	printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n");
2525

2526 2527 2528
	if (usb_disabled())
		return -ENODEV;

2529 2530 2531 2532 2533 2534 2535
	if (debug) {
		errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
		if (!errbuf)
			goto errbuf_failed;
	}

#ifdef CONFIG_PROC_FS
2536
	uhci_proc_root = create_proc_entry("driver/uhci", S_IFDIR, NULL);
2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553
	if (!uhci_proc_root)
		goto proc_failed;
#endif

	uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
		sizeof(struct urb_priv), 0, 0, NULL, NULL);
	if (!uhci_up_cachep)
		goto up_failed;

	retval = pci_module_init(&uhci_pci_driver);
	if (retval)
		goto init_failed;

	return 0;

init_failed:
	if (kmem_cache_destroy(uhci_up_cachep))
2554
		warn("not all urb_priv's were freed!");
2555 2556 2557 2558

up_failed:

#ifdef CONFIG_PROC_FS
2559
	remove_proc_entry("driver/uhci", NULL);
2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575

proc_failed:
#endif
	if (errbuf)
		kfree(errbuf);

errbuf_failed:

	return retval;
}

static void __exit uhci_hcd_cleanup(void) 
{
	pci_unregister_driver(&uhci_pci_driver);
	
	if (kmem_cache_destroy(uhci_up_cachep))
2576
		warn("not all urb_priv's were freed!");
2577 2578

#ifdef CONFIG_PROC_FS
2579
	remove_proc_entry("driver/uhci", NULL);
2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591
#endif

	if (errbuf)
		kfree(errbuf);
}

module_init(uhci_hcd_init);
module_exit(uhci_hcd_cleanup);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");