amd_iommu.c 83.3 KB
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/*
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 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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 * Author: Joerg Roedel <joerg.roedel@amd.com>
 *         Leo Duran <leo.duran@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

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#include <linux/ratelimit.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include <linux/bitmap.h>
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#include <linux/slab.h>
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#include <linux/debugfs.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/iommu-helper.h>
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#include <linux/iommu.h>
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#include <linux/delay.h>
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#include <linux/amd-iommu.h>
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#include <linux/notifier.h>
#include <linux/export.h>
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#include <asm/msidef.h>
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#include <asm/proto.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/dma.h>
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#include "amd_iommu_proto.h"
#include "amd_iommu_types.h"
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#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))

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#define LOOP_TIMEOUT	100000
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/*
 * This bitmap is used to advertise the page sizes our hardware support
 * to the IOMMU core, which will then use this information to split
 * physically contiguous memory regions it is mapping into page sizes
 * that we support.
 *
 * Traditionally the IOMMU core just handed us the mappings directly,
 * after making sure the size is an order of a 4KiB page and that the
 * mapping has natural alignment.
 *
 * To retain this behavior, we currently advertise that we support
 * all page sizes that are an order of 4KiB.
 *
 * If at some point we'd like to utilize the IOMMU core's new behavior,
 * we could change this to advertise the real page sizes we support.
 */
#define AMD_IOMMU_PGSIZES	(~0xFFFUL)

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static DEFINE_RWLOCK(amd_iommu_devtable_lock);

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/* A list of preallocated protection domains */
static LIST_HEAD(iommu_pd_list);
static DEFINE_SPINLOCK(iommu_pd_list_lock);

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/* List of all available dev_data structures */
static LIST_HEAD(dev_data_list);
static DEFINE_SPINLOCK(dev_data_list_lock);

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/*
 * Domain for untranslated devices - only allocated
 * if iommu=pt passed on kernel cmd line.
 */
static struct protection_domain *pt_domain;

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static struct iommu_ops amd_iommu_ops;

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static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
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int amd_iommu_max_glx_val = -1;
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static struct dma_map_ops amd_iommu_dma_ops;

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/*
 * general struct to manage commands send to an IOMMU
 */
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struct iommu_cmd {
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	u32 data[4];
};

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static void update_domain(struct protection_domain *domain);
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static int __init alloc_passthrough_domain(void);
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/****************************************************************************
 *
 * Helper functions
 *
 ****************************************************************************/

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static struct iommu_dev_data *alloc_dev_data(u16 devid)
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{
	struct iommu_dev_data *dev_data;
	unsigned long flags;

	dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
	if (!dev_data)
		return NULL;

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	dev_data->devid = devid;
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	atomic_set(&dev_data->bind, 0);

	spin_lock_irqsave(&dev_data_list_lock, flags);
	list_add_tail(&dev_data->dev_data_list, &dev_data_list);
	spin_unlock_irqrestore(&dev_data_list_lock, flags);

	return dev_data;
}

static void free_dev_data(struct iommu_dev_data *dev_data)
{
	unsigned long flags;

	spin_lock_irqsave(&dev_data_list_lock, flags);
	list_del(&dev_data->dev_data_list);
	spin_unlock_irqrestore(&dev_data_list_lock, flags);

	kfree(dev_data);
}

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static struct iommu_dev_data *search_dev_data(u16 devid)
{
	struct iommu_dev_data *dev_data;
	unsigned long flags;

	spin_lock_irqsave(&dev_data_list_lock, flags);
	list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
		if (dev_data->devid == devid)
			goto out_unlock;
	}

	dev_data = NULL;

out_unlock:
	spin_unlock_irqrestore(&dev_data_list_lock, flags);

	return dev_data;
}

static struct iommu_dev_data *find_dev_data(u16 devid)
{
	struct iommu_dev_data *dev_data;

	dev_data = search_dev_data(devid);

	if (dev_data == NULL)
		dev_data = alloc_dev_data(devid);

	return dev_data;
}

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static inline u16 get_device_id(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);

	return calc_devid(pdev->bus->number, pdev->devfn);
}

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static struct iommu_dev_data *get_dev_data(struct device *dev)
{
	return dev->archdata.iommu;
}

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static bool pci_iommuv2_capable(struct pci_dev *pdev)
{
	static const int caps[] = {
		PCI_EXT_CAP_ID_ATS,
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		PCI_EXT_CAP_ID_PRI,
		PCI_EXT_CAP_ID_PASID,
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	};
	int i, pos;

	for (i = 0; i < 3; ++i) {
		pos = pci_find_ext_capability(pdev, caps[i]);
		if (pos == 0)
			return false;
	}

	return true;
}

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static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
{
	struct iommu_dev_data *dev_data;

	dev_data = get_dev_data(&pdev->dev);

	return dev_data->errata & (1 << erratum) ? true : false;
}

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/*
 * In this function the list of preallocated protection domains is traversed to
 * find the domain for a specific device
 */
static struct dma_ops_domain *find_protection_domain(u16 devid)
{
	struct dma_ops_domain *entry, *ret = NULL;
	unsigned long flags;
	u16 alias = amd_iommu_alias_table[devid];

	if (list_empty(&iommu_pd_list))
		return NULL;

	spin_lock_irqsave(&iommu_pd_list_lock, flags);

	list_for_each_entry(entry, &iommu_pd_list, list) {
		if (entry->target_dev == devid ||
		    entry->target_dev == alias) {
			ret = entry;
			break;
		}
	}

	spin_unlock_irqrestore(&iommu_pd_list_lock, flags);

	return ret;
}

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/*
 * This function checks if the driver got a valid device from the caller to
 * avoid dereferencing invalid pointers.
 */
static bool check_device(struct device *dev)
{
	u16 devid;

	if (!dev || !dev->dma_mask)
		return false;

	/* No device or no PCI device */
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	if (dev->bus != &pci_bus_type)
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		return false;

	devid = get_device_id(dev);

	/* Out of our scope? */
	if (devid > amd_iommu_last_bdf)
		return false;

	if (amd_iommu_rlookup_table[devid] == NULL)
		return false;

	return true;
}

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static int iommu_init_device(struct device *dev)
{
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	struct pci_dev *pdev = to_pci_dev(dev);
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	struct iommu_dev_data *dev_data;
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	u16 alias;
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	if (dev->archdata.iommu)
		return 0;

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	dev_data = find_dev_data(get_device_id(dev));
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	if (!dev_data)
		return -ENOMEM;

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	alias = amd_iommu_alias_table[dev_data->devid];
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	if (alias != dev_data->devid) {
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		struct iommu_dev_data *alias_data;
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		alias_data = find_dev_data(alias);
		if (alias_data == NULL) {
			pr_err("AMD-Vi: Warning: Unhandled device %s\n",
					dev_name(dev));
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			free_dev_data(dev_data);
			return -ENOTSUPP;
		}
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		dev_data->alias_data = alias_data;
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	}
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	if (pci_iommuv2_capable(pdev)) {
		struct amd_iommu *iommu;

		iommu              = amd_iommu_rlookup_table[dev_data->devid];
		dev_data->iommu_v2 = iommu->is_iommu_v2;
	}

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	dev->archdata.iommu = dev_data;

	return 0;
}

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static void iommu_ignore_device(struct device *dev)
{
	u16 devid, alias;

	devid = get_device_id(dev);
	alias = amd_iommu_alias_table[devid];

	memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
	memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));

	amd_iommu_rlookup_table[devid] = NULL;
	amd_iommu_rlookup_table[alias] = NULL;
}

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static void iommu_uninit_device(struct device *dev)
{
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	/*
	 * Nothing to do here - we keep dev_data around for unplugged devices
	 * and reuse it when the device is re-plugged - not doing so would
	 * introduce a ton of races.
	 */
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}
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void __init amd_iommu_uninit_devices(void)
{
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	struct iommu_dev_data *dev_data, *n;
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	struct pci_dev *pdev = NULL;

	for_each_pci_dev(pdev) {

		if (!check_device(&pdev->dev))
			continue;

		iommu_uninit_device(&pdev->dev);
	}
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	/* Free all of our dev_data structures */
	list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
		free_dev_data(dev_data);
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}

int __init amd_iommu_init_devices(void)
{
	struct pci_dev *pdev = NULL;
	int ret = 0;

	for_each_pci_dev(pdev) {

		if (!check_device(&pdev->dev))
			continue;

		ret = iommu_init_device(&pdev->dev);
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		if (ret == -ENOTSUPP)
			iommu_ignore_device(&pdev->dev);
		else if (ret)
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			goto out_free;
	}

	return 0;

out_free:

	amd_iommu_uninit_devices();

	return ret;
}
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#ifdef CONFIG_AMD_IOMMU_STATS

/*
 * Initialization code for statistics collection
 */

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DECLARE_STATS_COUNTER(compl_wait);
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DECLARE_STATS_COUNTER(cnt_map_single);
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DECLARE_STATS_COUNTER(cnt_unmap_single);
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DECLARE_STATS_COUNTER(cnt_map_sg);
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DECLARE_STATS_COUNTER(cnt_unmap_sg);
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DECLARE_STATS_COUNTER(cnt_alloc_coherent);
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DECLARE_STATS_COUNTER(cnt_free_coherent);
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DECLARE_STATS_COUNTER(cross_page);
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DECLARE_STATS_COUNTER(domain_flush_single);
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DECLARE_STATS_COUNTER(domain_flush_all);
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DECLARE_STATS_COUNTER(alloced_io_mem);
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DECLARE_STATS_COUNTER(total_map_requests);
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DECLARE_STATS_COUNTER(complete_ppr);
DECLARE_STATS_COUNTER(invalidate_iotlb);
DECLARE_STATS_COUNTER(invalidate_iotlb_all);
DECLARE_STATS_COUNTER(pri_requests);

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static struct dentry *stats_dir;
static struct dentry *de_fflush;

static void amd_iommu_stats_add(struct __iommu_counter *cnt)
{
	if (stats_dir == NULL)
		return;

	cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
				       &cnt->value);
}

static void amd_iommu_stats_init(void)
{
	stats_dir = debugfs_create_dir("amd-iommu", NULL);
	if (stats_dir == NULL)
		return;

	de_fflush  = debugfs_create_bool("fullflush", 0444, stats_dir,
					 (u32 *)&amd_iommu_unmap_flush);
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	amd_iommu_stats_add(&compl_wait);
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	amd_iommu_stats_add(&cnt_map_single);
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	amd_iommu_stats_add(&cnt_unmap_single);
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	amd_iommu_stats_add(&cnt_map_sg);
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	amd_iommu_stats_add(&cnt_unmap_sg);
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	amd_iommu_stats_add(&cnt_alloc_coherent);
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	amd_iommu_stats_add(&cnt_free_coherent);
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	amd_iommu_stats_add(&cross_page);
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	amd_iommu_stats_add(&domain_flush_single);
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	amd_iommu_stats_add(&domain_flush_all);
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	amd_iommu_stats_add(&alloced_io_mem);
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	amd_iommu_stats_add(&total_map_requests);
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	amd_iommu_stats_add(&complete_ppr);
	amd_iommu_stats_add(&invalidate_iotlb);
	amd_iommu_stats_add(&invalidate_iotlb_all);
	amd_iommu_stats_add(&pri_requests);
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}

#endif

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/****************************************************************************
 *
 * Interrupt handling functions
 *
 ****************************************************************************/

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static void dump_dte_entry(u16 devid)
{
	int i;

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	for (i = 0; i < 4; ++i)
		pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
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			amd_iommu_dev_table[devid].data[i]);
}

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static void dump_command(unsigned long phys_addr)
{
	struct iommu_cmd *cmd = phys_to_virt(phys_addr);
	int i;

	for (i = 0; i < 4; ++i)
		pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
}

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static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
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{
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	int type, devid, domid, flags;
	volatile u32 *event = __evt;
	int count = 0;
	u64 address;

retry:
	type    = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
	devid   = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
	domid   = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
	flags   = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
	address = (u64)(((u64)event[3]) << 32) | event[2];

	if (type == 0) {
		/* Did we hit the erratum? */
		if (++count == LOOP_TIMEOUT) {
			pr_err("AMD-Vi: No event written to event log\n");
			return;
		}
		udelay(1);
		goto retry;
	}
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	printk(KERN_ERR "AMD-Vi: Event logged [");
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	switch (type) {
	case EVENT_TYPE_ILL_DEV:
		printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
		       "address=0x%016llx flags=0x%04x]\n",
		       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
		       address, flags);
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		dump_dte_entry(devid);
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		break;
	case EVENT_TYPE_IO_FAULT:
		printk("IO_PAGE_FAULT device=%02x:%02x.%x "
		       "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
		       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
		       domid, address, flags);
		break;
	case EVENT_TYPE_DEV_TAB_ERR:
		printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
		       "address=0x%016llx flags=0x%04x]\n",
		       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
		       address, flags);
		break;
	case EVENT_TYPE_PAGE_TAB_ERR:
		printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
		       "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
		       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
		       domid, address, flags);
		break;
	case EVENT_TYPE_ILL_CMD:
		printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
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		dump_command(address);
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		break;
	case EVENT_TYPE_CMD_HARD_ERR:
		printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
		       "flags=0x%04x]\n", address, flags);
		break;
	case EVENT_TYPE_IOTLB_INV_TO:
		printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
		       "address=0x%016llx]\n",
		       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
		       address);
		break;
	case EVENT_TYPE_INV_DEV_REQ:
		printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
		       "address=0x%016llx flags=0x%04x]\n",
		       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
		       address, flags);
		break;
	default:
		printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
	}
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	memset(__evt, 0, 4 * sizeof(u32));
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}

static void iommu_poll_events(struct amd_iommu *iommu)
{
	u32 head, tail;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);

	head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
	tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);

	while (head != tail) {
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		iommu_print_event(iommu, iommu->evt_buf + head);
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		head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
	}

	writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);

	spin_unlock_irqrestore(&iommu->lock, flags);
}

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static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
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{
	struct amd_iommu_fault fault;

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	INC_STATS_COUNTER(pri_requests);

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	if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
		pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
		return;
	}

	fault.address   = raw[1];
	fault.pasid     = PPR_PASID(raw[0]);
	fault.device_id = PPR_DEVID(raw[0]);
	fault.tag       = PPR_TAG(raw[0]);
	fault.flags     = PPR_FLAGS(raw[0]);

	atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
}

static void iommu_poll_ppr_log(struct amd_iommu *iommu)
{
	unsigned long flags;
	u32 head, tail;

	if (iommu->ppr_log == NULL)
		return;

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	/* enable ppr interrupts again */
	writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);

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	spin_lock_irqsave(&iommu->lock, flags);

	head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
	tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);

	while (head != tail) {
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		volatile u64 *raw;
		u64 entry[2];
		int i;

		raw = (u64 *)(iommu->ppr_log + head);

		/*
		 * Hardware bug: Interrupt may arrive before the entry is
		 * written to memory. If this happens we need to wait for the
		 * entry to arrive.
		 */
		for (i = 0; i < LOOP_TIMEOUT; ++i) {
			if (PPR_REQ_TYPE(raw[0]) != 0)
				break;
			udelay(1);
		}
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		/* Avoid memcpy function-call overhead */
		entry[0] = raw[0];
		entry[1] = raw[1];
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		/*
		 * To detect the hardware bug we need to clear the entry
		 * back to zero.
		 */
		raw[0] = raw[1] = 0UL;

		/* Update head pointer of hardware ring-buffer */
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		head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
		writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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		/*
		 * Release iommu->lock because ppr-handling might need to
		 * re-aquire it
		 */
		spin_unlock_irqrestore(&iommu->lock, flags);

		/* Handle PPR entry */
		iommu_handle_ppr_entry(iommu, entry);

		spin_lock_irqsave(&iommu->lock, flags);

		/* Refresh ring-buffer information */
		head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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		tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
	}

	spin_unlock_irqrestore(&iommu->lock, flags);
}

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irqreturn_t amd_iommu_int_thread(int irq, void *data)
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{
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	struct amd_iommu *iommu;

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	for_each_iommu(iommu) {
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		iommu_poll_events(iommu);
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		iommu_poll_ppr_log(iommu);
	}
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	return IRQ_HANDLED;
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}

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irqreturn_t amd_iommu_int_handler(int irq, void *data)
{
	return IRQ_WAKE_THREAD;
}

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/****************************************************************************
 *
 * IOMMU command queuing functions
 *
 ****************************************************************************/

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static int wait_on_sem(volatile u64 *sem)
{
	int i = 0;

	while (*sem == 0 && i < LOOP_TIMEOUT) {
		udelay(1);
		i += 1;
	}

	if (i == LOOP_TIMEOUT) {
		pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
		return -EIO;
	}

	return 0;
}

static void copy_cmd_to_buffer(struct amd_iommu *iommu,
			       struct iommu_cmd *cmd,
			       u32 tail)
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{
	u8 *target;

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	target = iommu->cmd_buf + tail;
686 687 688 689 690 691
	tail   = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;

	/* Copy command to buffer */
	memcpy(target, cmd, sizeof(*cmd));

	/* Tell the IOMMU about it */
692
	writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
693
}
694

695
static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
696
{
697 698
	WARN_ON(address & 0x7ULL);

699
	memset(cmd, 0, sizeof(*cmd));
700 701 702
	cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
	cmd->data[1] = upper_32_bits(__pa(address));
	cmd->data[2] = 1;
703 704 705
	CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
}

706 707 708 709 710 711 712
static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
{
	memset(cmd, 0, sizeof(*cmd));
	cmd->data[0] = devid;
	CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
}

713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743
static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
				  size_t size, u16 domid, int pde)
{
	u64 pages;
	int s;

	pages = iommu_num_pages(address, size, PAGE_SIZE);
	s     = 0;

	if (pages > 1) {
		/*
		 * If we have to flush more than one page, flush all
		 * TLB entries for this domain
		 */
		address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
		s = 1;
	}

	address &= PAGE_MASK;

	memset(cmd, 0, sizeof(*cmd));
	cmd->data[1] |= domid;
	cmd->data[2]  = lower_32_bits(address);
	cmd->data[3]  = upper_32_bits(address);
	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
	if (s) /* size bit - we flush more than one 4kb page */
		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
	if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
		cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
}

744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
				  u64 address, size_t size)
{
	u64 pages;
	int s;

	pages = iommu_num_pages(address, size, PAGE_SIZE);
	s     = 0;

	if (pages > 1) {
		/*
		 * If we have to flush more than one page, flush all
		 * TLB entries for this domain
		 */
		address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
		s = 1;
	}

	address &= PAGE_MASK;

	memset(cmd, 0, sizeof(*cmd));
	cmd->data[0]  = devid;
	cmd->data[0] |= (qdep & 0xff) << 24;
	cmd->data[1]  = devid;
	cmd->data[2]  = lower_32_bits(address);
	cmd->data[3]  = upper_32_bits(address);
	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
	if (s)
		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
}

775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812
static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
				  u64 address, bool size)
{
	memset(cmd, 0, sizeof(*cmd));

	address &= ~(0xfffULL);

	cmd->data[0]  = pasid & PASID_MASK;
	cmd->data[1]  = domid;
	cmd->data[2]  = lower_32_bits(address);
	cmd->data[3]  = upper_32_bits(address);
	cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
	cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
	if (size)
		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
}

static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
				  int qdep, u64 address, bool size)
{
	memset(cmd, 0, sizeof(*cmd));

	address &= ~(0xfffULL);

	cmd->data[0]  = devid;
	cmd->data[0] |= (pasid & 0xff) << 16;
	cmd->data[0] |= (qdep  & 0xff) << 24;
	cmd->data[1]  = devid;
	cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
	cmd->data[2]  = lower_32_bits(address);
	cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
	cmd->data[3]  = upper_32_bits(address);
	if (size)
		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
}

813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828
static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
			       int status, int tag, bool gn)
{
	memset(cmd, 0, sizeof(*cmd));

	cmd->data[0]  = devid;
	if (gn) {
		cmd->data[1]  = pasid & PASID_MASK;
		cmd->data[2]  = CMD_INV_IOMMU_PAGES_GN_MASK;
	}
	cmd->data[3]  = tag & 0x1ff;
	cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;

	CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
}

829 830 831 832
static void build_inv_all(struct iommu_cmd *cmd)
{
	memset(cmd, 0, sizeof(*cmd));
	CMD_SET_TYPE(cmd, CMD_INV_ALL);
833 834
}

835 836
/*
 * Writes the command to the IOMMUs command buffer and informs the
837
 * hardware about the new command.
838
 */
839 840 841
static int iommu_queue_command_sync(struct amd_iommu *iommu,
				    struct iommu_cmd *cmd,
				    bool sync)
842
{
843
	u32 left, tail, head, next_tail;
844 845
	unsigned long flags;

846
	WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
847 848

again:
849 850
	spin_lock_irqsave(&iommu->lock, flags);

851 852 853 854
	head      = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
	tail      = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
	next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
	left      = (head - next_tail) % iommu->cmd_buf_size;
855

856 857 858 859
	if (left <= 2) {
		struct iommu_cmd sync_cmd;
		volatile u64 sem = 0;
		int ret;
860

861 862
		build_completion_wait(&sync_cmd, (u64)&sem);
		copy_cmd_to_buffer(iommu, &sync_cmd, tail);
863

864 865 866 867 868 869
		spin_unlock_irqrestore(&iommu->lock, flags);

		if ((ret = wait_on_sem(&sem)) != 0)
			return ret;

		goto again;
870 871
	}

872 873 874
	copy_cmd_to_buffer(iommu, cmd, tail);

	/* We need to sync now to make sure all commands are processed */
875
	iommu->need_sync = sync;
876

877
	spin_unlock_irqrestore(&iommu->lock, flags);
878

879
	return 0;
880 881
}

882 883 884 885 886
static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
{
	return iommu_queue_command_sync(iommu, cmd, true);
}

887 888 889 890
/*
 * This function queues a completion wait command into the command
 * buffer of an IOMMU
 */
891
static int iommu_completion_wait(struct amd_iommu *iommu)
892 893
{
	struct iommu_cmd cmd;
894
	volatile u64 sem = 0;
895
	int ret;
896

897
	if (!iommu->need_sync)
898
		return 0;
899

900
	build_completion_wait(&cmd, (u64)&sem);
901

902
	ret = iommu_queue_command_sync(iommu, &cmd, false);
903
	if (ret)
904
		return ret;
905

906
	return wait_on_sem(&sem);
907 908
}

909
static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
910
{
911
	struct iommu_cmd cmd;
912

913
	build_inv_dte(&cmd, devid);
914

915 916
	return iommu_queue_command(iommu, &cmd);
}
917

918 919 920
static void iommu_flush_dte_all(struct amd_iommu *iommu)
{
	u32 devid;
921

922 923
	for (devid = 0; devid <= 0xffff; ++devid)
		iommu_flush_dte(iommu, devid);
924

925 926
	iommu_completion_wait(iommu);
}
927

928 929 930 931 932 933 934
/*
 * This function uses heavy locking and may disable irqs for some time. But
 * this is no issue because it is only called during resume.
 */
static void iommu_flush_tlb_all(struct amd_iommu *iommu)
{
	u32 dom_id;
935

936 937 938 939 940 941
	for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
		struct iommu_cmd cmd;
		build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
				      dom_id, 1);
		iommu_queue_command(iommu, &cmd);
	}
942

943
	iommu_completion_wait(iommu);
944 945
}

946
static void iommu_flush_all(struct amd_iommu *iommu)
947
{
948
	struct iommu_cmd cmd;
949

950
	build_inv_all(&cmd);
951

952 953 954 955
	iommu_queue_command(iommu, &cmd);
	iommu_completion_wait(iommu);
}

956 957
void iommu_flush_all_caches(struct amd_iommu *iommu)
{
958 959 960 961 962
	if (iommu_feature(iommu, FEATURE_IA)) {
		iommu_flush_all(iommu);
	} else {
		iommu_flush_dte_all(iommu);
		iommu_flush_tlb_all(iommu);
963 964 965
	}
}

966
/*
967
 * Command send function for flushing on-device TLB
968
 */
969 970
static int device_flush_iotlb(struct iommu_dev_data *dev_data,
			      u64 address, size_t size)
971 972
{
	struct amd_iommu *iommu;
973
	struct iommu_cmd cmd;
974
	int qdep;
975

976 977
	qdep     = dev_data->ats.qdep;
	iommu    = amd_iommu_rlookup_table[dev_data->devid];
978

979
	build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
980 981

	return iommu_queue_command(iommu, &cmd);
982 983
}

984 985 986
/*
 * Command send function for invalidating a device table entry
 */
987
static int device_flush_dte(struct iommu_dev_data *dev_data)
988
{
989
	struct amd_iommu *iommu;
990
	int ret;
991

992
	iommu = amd_iommu_rlookup_table[dev_data->devid];
993

994
	ret = iommu_flush_dte(iommu, dev_data->devid);
995 996 997
	if (ret)
		return ret;

998
	if (dev_data->ats.enabled)
999
		ret = device_flush_iotlb(dev_data, 0, ~0UL);
1000 1001

	return ret;
1002 1003
}

1004 1005 1006 1007 1008
/*
 * TLB invalidation function which is called from the mapping functions.
 * It invalidates a single PTE if the range to flush is within a single
 * page. Otherwise it flushes the whole TLB of the IOMMU.
 */
1009 1010
static void __domain_flush_pages(struct protection_domain *domain,
				 u64 address, size_t size, int pde)
1011
{
1012
	struct iommu_dev_data *dev_data;
1013 1014
	struct iommu_cmd cmd;
	int ret = 0, i;
1015

1016
	build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1017

1018 1019 1020 1021 1022 1023 1024 1025
	for (i = 0; i < amd_iommus_present; ++i) {
		if (!domain->dev_iommu[i])
			continue;

		/*
		 * Devices of this domain are behind this IOMMU
		 * We need a TLB flush
		 */
1026
		ret |= iommu_queue_command(amd_iommus[i], &cmd);
1027 1028
	}

1029 1030
	list_for_each_entry(dev_data, &domain->dev_list, list) {

1031
		if (!dev_data->ats.enabled)
1032 1033
			continue;

1034
		ret |= device_flush_iotlb(dev_data, address, size);
1035 1036
	}

1037
	WARN_ON(ret);
1038 1039
}

1040 1041
static void domain_flush_pages(struct protection_domain *domain,
			       u64 address, size_t size)
1042
{
1043
	__domain_flush_pages(domain, address, size, 0);
1044
}
1045

1046
/* Flush the whole IO/TLB for a given protection domain */
1047
static void domain_flush_tlb(struct protection_domain *domain)
1048
{
1049
	__domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1050 1051
}

1052
/* Flush the whole IO/TLB for a given protection domain - including PDE */
1053
static void domain_flush_tlb_pde(struct protection_domain *domain)
1054
{
1055
	__domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1056 1057
}

1058
static void domain_flush_complete(struct protection_domain *domain)
1059
{
1060
	int i;
1061

1062 1063 1064
	for (i = 0; i < amd_iommus_present; ++i) {
		if (!domain->dev_iommu[i])
			continue;
1065

1066 1067 1068 1069 1070
		/*
		 * Devices of this domain are behind this IOMMU
		 * We need to wait for completion of all commands.
		 */
		iommu_completion_wait(amd_iommus[i]);
1071
	}
1072 1073
}

1074

1075
/*
1076
 * This function flushes the DTEs for all devices in domain
1077
 */
1078
static void domain_flush_devices(struct protection_domain *domain)
1079
{
1080
	struct iommu_dev_data *dev_data;
1081

1082
	list_for_each_entry(dev_data, &domain->dev_list, list)
1083
		device_flush_dte(dev_data);
1084 1085
}

1086 1087 1088 1089 1090 1091 1092
/****************************************************************************
 *
 * The functions below are used the create the page table mappings for
 * unity mapped regions.
 *
 ****************************************************************************/

1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
/*
 * This function is used to add another level to an IO page table. Adding
 * another level increases the size of the address space by 9 bits to a size up
 * to 64 bits.
 */
static bool increase_address_space(struct protection_domain *domain,
				   gfp_t gfp)
{
	u64 *pte;

	if (domain->mode == PAGE_MODE_6_LEVEL)
		/* address space already 64 bit large */
		return false;

	pte = (void *)get_zeroed_page(gfp);
	if (!pte)
		return false;

	*pte             = PM_LEVEL_PDE(domain->mode,
					virt_to_phys(domain->pt_root));
	domain->pt_root  = pte;
	domain->mode    += 1;
	domain->updated  = true;

	return true;
}

static u64 *alloc_pte(struct protection_domain *domain,
		      unsigned long address,
1122
		      unsigned long page_size,
1123 1124 1125
		      u64 **pte_page,
		      gfp_t gfp)
{
1126
	int level, end_lvl;
1127
	u64 *pte, *page;
1128 1129

	BUG_ON(!is_power_of_2(page_size));
1130 1131 1132 1133

	while (address > PM_LEVEL_SIZE(domain->mode))
		increase_address_space(domain, gfp);

1134 1135 1136 1137
	level   = domain->mode - 1;
	pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
	address = PAGE_SIZE_ALIGN(address, page_size);
	end_lvl = PAGE_SIZE_LEVEL(page_size);
1138 1139 1140 1141 1142 1143 1144 1145 1146

	while (level > end_lvl) {
		if (!IOMMU_PTE_PRESENT(*pte)) {
			page = (u64 *)get_zeroed_page(gfp);
			if (!page)
				return NULL;
			*pte = PM_LEVEL_PDE(level, virt_to_phys(page));
		}

1147 1148 1149 1150
		/* No level skipping support yet */
		if (PM_PTE_LEVEL(*pte) != level)
			return NULL;

1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
		level -= 1;

		pte = IOMMU_PTE_PAGE(*pte);

		if (pte_page && level == end_lvl)
			*pte_page = pte;

		pte = &pte[PM_LEVEL_INDEX(level, address)];
	}

	return pte;
}

/*
 * This function checks if there is a PTE for a given dma address. If
 * there is one, it returns the pointer to it.
 */
1168
static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1169 1170 1171 1172
{
	int level;
	u64 *pte;

1173 1174 1175 1176 1177
	if (address > PM_LEVEL_SIZE(domain->mode))
		return NULL;

	level   =  domain->mode - 1;
	pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1178

1179 1180 1181
	while (level > 0) {

		/* Not Present */
1182 1183 1184
		if (!IOMMU_PTE_PRESENT(*pte))
			return NULL;

1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
		/* Large PTE */
		if (PM_PTE_LEVEL(*pte) == 0x07) {
			unsigned long pte_mask, __pte;

			/*
			 * If we have a series of large PTEs, make
			 * sure to return a pointer to the first one.
			 */
			pte_mask = PTE_PAGE_SIZE(*pte);
			pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
			__pte    = ((unsigned long)pte) & pte_mask;

			return (u64 *)__pte;
		}

		/* No level skipping support yet */
		if (PM_PTE_LEVEL(*pte) != level)
			return NULL;

1204 1205
		level -= 1;

1206
		/* Walk to the next level */
1207 1208 1209 1210 1211 1212 1213
		pte = IOMMU_PTE_PAGE(*pte);
		pte = &pte[PM_LEVEL_INDEX(level, address)];
	}

	return pte;
}

1214 1215 1216 1217 1218 1219 1220
/*
 * Generic mapping functions. It maps a physical address into a DMA
 * address space. It allocates the page table pages if necessary.
 * In the future it can be extended to a generic mapping function
 * supporting all features of AMD IOMMU page tables like level skipping
 * and full 64 bit address spaces.
 */
1221 1222 1223
static int iommu_map_page(struct protection_domain *dom,
			  unsigned long bus_addr,
			  unsigned long phys_addr,
1224
			  int prot,
1225
			  unsigned long page_size)
1226
{
1227
	u64 __pte, *pte;
1228
	int i, count;
1229

1230
	if (!(prot & IOMMU_PROT_MASK))
1231 1232
		return -EINVAL;

1233 1234 1235 1236 1237 1238 1239 1240
	bus_addr  = PAGE_ALIGN(bus_addr);
	phys_addr = PAGE_ALIGN(phys_addr);
	count     = PAGE_SIZE_PTE_COUNT(page_size);
	pte       = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);

	for (i = 0; i < count; ++i)
		if (IOMMU_PTE_PRESENT(pte[i]))
			return -EBUSY;
1241

1242 1243 1244 1245 1246
	if (page_size > PAGE_SIZE) {
		__pte = PAGE_SIZE_PTE(phys_addr, page_size);
		__pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
	} else
		__pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1247 1248 1249 1250 1251 1252

	if (prot & IOMMU_PROT_IR)
		__pte |= IOMMU_PTE_IR;
	if (prot & IOMMU_PROT_IW)
		__pte |= IOMMU_PTE_IW;

1253 1254
	for (i = 0; i < count; ++i)
		pte[i] = __pte;
1255

1256 1257
	update_domain(dom);

1258 1259 1260
	return 0;
}

1261 1262 1263
static unsigned long iommu_unmap_page(struct protection_domain *dom,
				      unsigned long bus_addr,
				      unsigned long page_size)
1264
{
1265 1266 1267 1268 1269 1270
	unsigned long long unmap_size, unmapped;
	u64 *pte;

	BUG_ON(!is_power_of_2(page_size));

	unmapped = 0;
1271

1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
	while (unmapped < page_size) {

		pte = fetch_pte(dom, bus_addr);

		if (!pte) {
			/*
			 * No PTE for this address
			 * move forward in 4kb steps
			 */
			unmap_size = PAGE_SIZE;
		} else if (PM_PTE_LEVEL(*pte) == 0) {
			/* 4kb PTE found for this address */
			unmap_size = PAGE_SIZE;
			*pte       = 0ULL;
		} else {
			int count, i;

			/* Large PTE found which maps this address */
			unmap_size = PTE_PAGE_SIZE(*pte);
			count      = PAGE_SIZE_PTE_COUNT(unmap_size);
			for (i = 0; i < count; i++)
				pte[i] = 0ULL;
		}

		bus_addr  = (bus_addr & ~(unmap_size - 1)) + unmap_size;
		unmapped += unmap_size;
	}

	BUG_ON(!is_power_of_2(unmapped));
1301

1302
	return unmapped;
1303 1304
}

1305 1306 1307 1308
/*
 * This function checks if a specific unity mapping entry is needed for
 * this specific IOMMU.
 */
1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
static int iommu_for_unity_map(struct amd_iommu *iommu,
			       struct unity_map_entry *entry)
{
	u16 bdf, i;

	for (i = entry->devid_start; i <= entry->devid_end; ++i) {
		bdf = amd_iommu_alias_table[i];
		if (amd_iommu_rlookup_table[bdf] == iommu)
			return 1;
	}

	return 0;
}

1323 1324 1325 1326
/*
 * This function actually applies the mapping to the page table of the
 * dma_ops domain.
 */
1327 1328 1329 1330 1331 1332 1333 1334
static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
			     struct unity_map_entry *e)
{
	u64 addr;
	int ret;

	for (addr = e->address_start; addr < e->address_end;
	     addr += PAGE_SIZE) {
1335
		ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1336
				     PAGE_SIZE);
1337 1338 1339 1340 1341 1342 1343
		if (ret)
			return ret;
		/*
		 * if unity mapping is in aperture range mark the page
		 * as allocated in the aperture
		 */
		if (addr < dma_dom->aperture_size)
1344
			__set_bit(addr >> PAGE_SHIFT,
1345
				  dma_dom->aperture[0]->bitmap);
1346 1347 1348 1349 1350
	}

	return 0;
}

1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
/*
 * Init the unity mappings for a specific IOMMU in the system
 *
 * Basically iterates over all unity mapping entries and applies them to
 * the default domain DMA of that IOMMU if necessary.
 */
static int iommu_init_unity_mappings(struct amd_iommu *iommu)
{
	struct unity_map_entry *entry;
	int ret;

	list_for_each_entry(entry, &amd_iommu_unity_map, list) {
		if (!iommu_for_unity_map(iommu, entry))
			continue;
		ret = dma_ops_unity_map(iommu->default_dom, entry);
		if (ret)
			return ret;
	}

	return 0;
}

1373 1374 1375
/*
 * Inits the unity mappings required for a specific device
 */
1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
					  u16 devid)
{
	struct unity_map_entry *e;
	int ret;

	list_for_each_entry(e, &amd_iommu_unity_map, list) {
		if (!(devid >= e->devid_start && devid <= e->devid_end))
			continue;
		ret = dma_ops_unity_map(dma_dom, e);
		if (ret)
			return ret;
	}

	return 0;
}

1393 1394 1395 1396 1397 1398 1399 1400 1401
/****************************************************************************
 *
 * The next functions belong to the address allocator for the dma_ops
 * interface functions. They work like the allocators in the other IOMMU
 * drivers. Its basically a bitmap which marks the allocated pages in
 * the aperture. Maybe it could be enhanced in the future to a more
 * efficient allocator.
 *
 ****************************************************************************/
1402

1403
/*
1404
 * The address allocator core functions.
1405 1406 1407
 *
 * called with domain->lock held
 */
1408

1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
/*
 * Used to reserve address ranges in the aperture (e.g. for exclusion
 * ranges.
 */
static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
				      unsigned long start_page,
				      unsigned int pages)
{
	unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;

	if (start_page + pages > last_page)
		pages = last_page - start_page;

	for (i = start_page; i < start_page + pages; ++i) {
		int index = i / APERTURE_RANGE_PAGES;
		int page  = i % APERTURE_RANGE_PAGES;
		__set_bit(page, dom->aperture[index]->bitmap);
	}
}

1429 1430 1431 1432 1433
/*
 * This function is used to add a new aperture range to an existing
 * aperture in case of dma_ops domain allocation or address allocation
 * failure.
 */
1434
static int alloc_new_range(struct dma_ops_domain *dma_dom,
1435 1436 1437
			   bool populate, gfp_t gfp)
{
	int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1438
	struct amd_iommu *iommu;
1439
	unsigned long i, old_size;
1440

1441 1442 1443 1444
#ifdef CONFIG_IOMMU_STRESS
	populate = false;
#endif

1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
	if (index >= APERTURE_MAX_RANGES)
		return -ENOMEM;

	dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
	if (!dma_dom->aperture[index])
		return -ENOMEM;

	dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
	if (!dma_dom->aperture[index]->bitmap)
		goto out_free;

	dma_dom->aperture[index]->offset = dma_dom->aperture_size;

	if (populate) {
		unsigned long address = dma_dom->aperture_size;
		int i, num_ptes = APERTURE_RANGE_PAGES / 512;
		u64 *pte, *pte_page;

		for (i = 0; i < num_ptes; ++i) {
1464
			pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1465 1466 1467 1468 1469 1470 1471 1472 1473 1474
					&pte_page, gfp);
			if (!pte)
				goto out_free;

			dma_dom->aperture[index]->pte_pages[i] = pte_page;

			address += APERTURE_RANGE_SIZE / 64;
		}
	}

1475
	old_size                = dma_dom->aperture_size;
1476 1477
	dma_dom->aperture_size += APERTURE_RANGE_SIZE;

1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489
	/* Reserve address range used for MSI messages */
	if (old_size < MSI_ADDR_BASE_LO &&
	    dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
		unsigned long spage;
		int pages;

		pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
		spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;

		dma_ops_reserve_addresses(dma_dom, spage, pages);
	}

1490
	/* Initialize the exclusion range if necessary */
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
	for_each_iommu(iommu) {
		if (iommu->exclusion_start &&
		    iommu->exclusion_start >= dma_dom->aperture[index]->offset
		    && iommu->exclusion_start < dma_dom->aperture_size) {
			unsigned long startpage;
			int pages = iommu_num_pages(iommu->exclusion_start,
						    iommu->exclusion_length,
						    PAGE_SIZE);
			startpage = iommu->exclusion_start >> PAGE_SHIFT;
			dma_ops_reserve_addresses(dma_dom, startpage, pages);
		}
1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
	}

	/*
	 * Check for areas already mapped as present in the new aperture
	 * range and mark those pages as reserved in the allocator. Such
	 * mappings may already exist as a result of requested unity
	 * mappings for devices.
	 */
	for (i = dma_dom->aperture[index]->offset;
	     i < dma_dom->aperture_size;
	     i += PAGE_SIZE) {
1513
		u64 *pte = fetch_pte(&dma_dom->domain, i);
1514 1515 1516
		if (!pte || !IOMMU_PTE_PRESENT(*pte))
			continue;

1517
		dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1518 1519
	}

1520 1521
	update_domain(&dma_dom->domain);

1522 1523 1524
	return 0;

out_free:
1525 1526
	update_domain(&dma_dom->domain);

1527 1528 1529 1530 1531 1532 1533 1534
	free_page((unsigned long)dma_dom->aperture[index]->bitmap);

	kfree(dma_dom->aperture[index]);
	dma_dom->aperture[index] = NULL;

	return -ENOMEM;
}

1535 1536 1537 1538 1539 1540 1541
static unsigned long dma_ops_area_alloc(struct device *dev,
					struct dma_ops_domain *dom,
					unsigned int pages,
					unsigned long align_mask,
					u64 dma_mask,
					unsigned long start)
{
1542
	unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1543 1544 1545 1546 1547 1548
	int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
	int i = start >> APERTURE_RANGE_SHIFT;
	unsigned long boundary_size;
	unsigned long address = -1;
	unsigned long limit;

1549 1550
	next_bit >>= PAGE_SHIFT;

1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568
	boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
			PAGE_SIZE) >> PAGE_SHIFT;

	for (;i < max_index; ++i) {
		unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;

		if (dom->aperture[i]->offset >= dma_mask)
			break;

		limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
					       dma_mask >> PAGE_SHIFT);

		address = iommu_area_alloc(dom->aperture[i]->bitmap,
					   limit, next_bit, pages, 0,
					    boundary_size, align_mask);
		if (address != -1) {
			address = dom->aperture[i]->offset +
				  (address << PAGE_SHIFT);
1569
			dom->next_address = address + (pages << PAGE_SHIFT);
1570 1571 1572 1573 1574 1575 1576 1577 1578
			break;
		}

		next_bit = 0;
	}

	return address;
}

1579 1580
static unsigned long dma_ops_alloc_addresses(struct device *dev,
					     struct dma_ops_domain *dom,
1581
					     unsigned int pages,
1582 1583
					     unsigned long align_mask,
					     u64 dma_mask)
1584 1585 1586
{
	unsigned long address;

1587 1588 1589 1590
#ifdef CONFIG_IOMMU_STRESS
	dom->next_address = 0;
	dom->need_flush = true;
#endif
1591

1592
	address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1593
				     dma_mask, dom->next_address);
1594

1595
	if (address == -1) {
1596
		dom->next_address = 0;
1597 1598
		address = dma_ops_area_alloc(dev, dom, pages, align_mask,
					     dma_mask, 0);
1599 1600
		dom->need_flush = true;
	}
1601

1602
	if (unlikely(address == -1))
1603
		address = DMA_ERROR_CODE;
1604 1605 1606 1607 1608 1609

	WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);

	return address;
}

1610 1611 1612 1613 1614
/*
 * The address free function.
 *
 * called with domain->lock held
 */
1615 1616 1617 1618
static void dma_ops_free_addresses(struct dma_ops_domain *dom,
				   unsigned long address,
				   unsigned int pages)
{
1619 1620
	unsigned i = address >> APERTURE_RANGE_SHIFT;
	struct aperture_range *range = dom->aperture[i];
1621

1622 1623
	BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);

1624 1625 1626 1627
#ifdef CONFIG_IOMMU_STRESS
	if (i < 4)
		return;
#endif
1628

1629
	if (address >= dom->next_address)
1630
		dom->need_flush = true;
1631 1632

	address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1633

1634
	bitmap_clear(range->bitmap, address, pages);
1635

1636 1637
}

1638 1639 1640 1641 1642 1643 1644 1645 1646 1647
/****************************************************************************
 *
 * The next functions belong to the domain allocation. A domain is
 * allocated for every IOMMU as the default domain. If device isolation
 * is enabled, every device get its own domain. The most important thing
 * about domains is the page table mapping the DMA address space they
 * contain.
 *
 ****************************************************************************/

1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672
/*
 * This function adds a protection domain to the global protection domain list
 */
static void add_domain_to_list(struct protection_domain *domain)
{
	unsigned long flags;

	spin_lock_irqsave(&amd_iommu_pd_lock, flags);
	list_add(&domain->list, &amd_iommu_pd_list);
	spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
}

/*
 * This function removes a protection domain to the global
 * protection domain list
 */
static void del_domain_from_list(struct protection_domain *domain)
{
	unsigned long flags;

	spin_lock_irqsave(&amd_iommu_pd_lock, flags);
	list_del(&domain->list);
	spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
}

1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689
static u16 domain_id_alloc(void)
{
	unsigned long flags;
	int id;

	write_lock_irqsave(&amd_iommu_devtable_lock, flags);
	id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
	BUG_ON(id == 0);
	if (id > 0 && id < MAX_DOMAIN_ID)
		__set_bit(id, amd_iommu_pd_alloc_bitmap);
	else
		id = 0;
	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);

	return id;
}

1690 1691 1692 1693 1694 1695 1696 1697 1698 1699
static void domain_id_free(int id)
{
	unsigned long flags;

	write_lock_irqsave(&amd_iommu_devtable_lock, flags);
	if (id > 0 && id < MAX_DOMAIN_ID)
		__clear_bit(id, amd_iommu_pd_alloc_bitmap);
	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
}

1700
static void free_pagetable(struct protection_domain *domain)
1701 1702 1703 1704
{
	int i, j;
	u64 *p1, *p2, *p3;

1705
	p1 = domain->pt_root;
1706 1707 1708 1709 1710 1711 1712 1713 1714

	if (!p1)
		return;

	for (i = 0; i < 512; ++i) {
		if (!IOMMU_PTE_PRESENT(p1[i]))
			continue;

		p2 = IOMMU_PTE_PAGE(p1[i]);
1715
		for (j = 0; j < 512; ++j) {
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
			if (!IOMMU_PTE_PRESENT(p2[j]))
				continue;
			p3 = IOMMU_PTE_PAGE(p2[j]);
			free_page((unsigned long)p3);
		}

		free_page((unsigned long)p2);
	}

	free_page((unsigned long)p1);
1726 1727

	domain->pt_root = NULL;
1728 1729
}

1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
static void free_gcr3_tbl_level1(u64 *tbl)
{
	u64 *ptr;
	int i;

	for (i = 0; i < 512; ++i) {
		if (!(tbl[i] & GCR3_VALID))
			continue;

		ptr = __va(tbl[i] & PAGE_MASK);

		free_page((unsigned long)ptr);
	}
}

static void free_gcr3_tbl_level2(u64 *tbl)
{
	u64 *ptr;
	int i;

	for (i = 0; i < 512; ++i) {
		if (!(tbl[i] & GCR3_VALID))
			continue;

		ptr = __va(tbl[i] & PAGE_MASK);

		free_gcr3_tbl_level1(ptr);
	}
}

1760 1761
static void free_gcr3_table(struct protection_domain *domain)
{
1762 1763 1764 1765 1766 1767 1768
	if (domain->glx == 2)
		free_gcr3_tbl_level2(domain->gcr3_tbl);
	else if (domain->glx == 1)
		free_gcr3_tbl_level1(domain->gcr3_tbl);
	else if (domain->glx != 0)
		BUG();

1769 1770 1771
	free_page((unsigned long)domain->gcr3_tbl);
}

1772 1773 1774 1775
/*
 * Free a domain, only used if something went wrong in the
 * allocation path and we need to free an already allocated page table
 */
1776 1777
static void dma_ops_domain_free(struct dma_ops_domain *dom)
{
1778 1779
	int i;

1780 1781 1782
	if (!dom)
		return;

1783 1784
	del_domain_from_list(&dom->domain);

1785
	free_pagetable(&dom->domain);
1786

1787 1788 1789 1790 1791 1792
	for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
		if (!dom->aperture[i])
			continue;
		free_page((unsigned long)dom->aperture[i]->bitmap);
		kfree(dom->aperture[i]);
	}
1793 1794 1795 1796

	kfree(dom);
}

1797 1798
/*
 * Allocates a new protection domain usable for the dma_ops functions.
1799
 * It also initializes the page table and the address allocator data
1800 1801
 * structures required for the dma_ops interface
 */
1802
static struct dma_ops_domain *dma_ops_domain_alloc(void)
1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814
{
	struct dma_ops_domain *dma_dom;

	dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
	if (!dma_dom)
		return NULL;

	spin_lock_init(&dma_dom->domain.lock);

	dma_dom->domain.id = domain_id_alloc();
	if (dma_dom->domain.id == 0)
		goto free_dma_dom;
1815
	INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1816
	dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1817
	dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1818
	dma_dom->domain.flags = PD_DMA_OPS_MASK;
1819 1820 1821 1822
	dma_dom->domain.priv = dma_dom;
	if (!dma_dom->domain.pt_root)
		goto free_dma_dom;

1823
	dma_dom->need_flush = false;
1824
	dma_dom->target_dev = 0xffff;
1825

1826 1827
	add_domain_to_list(&dma_dom->domain);

1828
	if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1829 1830
		goto free_dma_dom;

1831
	/*
1832 1833
	 * mark the first page as allocated so we never return 0 as
	 * a valid dma-address. So we can use 0 as error value
1834
	 */
1835
	dma_dom->aperture[0]->bitmap[0] = 1;
1836
	dma_dom->next_address = 0;
1837 1838 1839 1840 1841 1842 1843 1844 1845 1846


	return dma_dom;

free_dma_dom:
	dma_ops_domain_free(dma_dom);

	return NULL;
}

1847 1848 1849 1850 1851 1852 1853 1854 1855
/*
 * little helper function to check whether a given protection domain is a
 * dma_ops domain
 */
static bool dma_ops_domain(struct protection_domain *domain)
{
	return domain->flags & PD_DMA_OPS_MASK;
}

1856
static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1857
{
1858
	u64 pte_root = 0;
1859
	u64 flags = 0;
1860

1861 1862 1863
	if (domain->mode != PAGE_MODE_NONE)
		pte_root = virt_to_phys(domain->pt_root);

1864 1865 1866
	pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
		    << DEV_ENTRY_MODE_SHIFT;
	pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1867

1868 1869
	flags = amd_iommu_dev_table[devid].data[1];

1870 1871 1872
	if (ats)
		flags |= DTE_FLAG_IOTLB;

1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898
	if (domain->flags & PD_IOMMUV2_MASK) {
		u64 gcr3 = __pa(domain->gcr3_tbl);
		u64 glx  = domain->glx;
		u64 tmp;

		pte_root |= DTE_FLAG_GV;
		pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;

		/* First mask out possible old values for GCR3 table */
		tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
		flags    &= ~tmp;

		tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
		flags    &= ~tmp;

		/* Encode GCR3 table into DTE */
		tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
		pte_root |= tmp;

		tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
		flags    |= tmp;

		tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
		flags    |= tmp;
	}

1899 1900 1901 1902 1903
	flags &= ~(0xffffUL);
	flags |= domain->id;

	amd_iommu_dev_table[devid].data[1]  = flags;
	amd_iommu_dev_table[devid].data[0]  = pte_root;
1904 1905 1906 1907 1908 1909 1910 1911 1912
}

static void clear_dte_entry(u16 devid)
{
	/* remove entry from the device table seen by the hardware */
	amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
	amd_iommu_dev_table[devid].data[1] = 0;

	amd_iommu_apply_erratum_63(devid);
1913 1914
}

1915 1916
static void do_attach(struct iommu_dev_data *dev_data,
		      struct protection_domain *domain)
1917 1918
{
	struct amd_iommu *iommu;
1919
	bool ats;
1920

1921 1922
	iommu = amd_iommu_rlookup_table[dev_data->devid];
	ats   = dev_data->ats.enabled;
1923 1924 1925 1926

	/* Update data structures */
	dev_data->domain = domain;
	list_add(&dev_data->list, &domain->dev_list);
1927
	set_dte_entry(dev_data->devid, domain, ats);
1928 1929 1930 1931 1932 1933

	/* Do reference counting */
	domain->dev_iommu[iommu->index] += 1;
	domain->dev_cnt                 += 1;

	/* Flush the DTE entry */
1934
	device_flush_dte(dev_data);
1935 1936
}

1937
static void do_detach(struct iommu_dev_data *dev_data)
1938 1939 1940
{
	struct amd_iommu *iommu;

1941
	iommu = amd_iommu_rlookup_table[dev_data->devid];
1942 1943

	/* decrease reference counters */
1944 1945 1946 1947 1948 1949
	dev_data->domain->dev_iommu[iommu->index] -= 1;
	dev_data->domain->dev_cnt                 -= 1;

	/* Update data structures */
	dev_data->domain = NULL;
	list_del(&dev_data->list);
1950
	clear_dte_entry(dev_data->devid);
1951

1952
	/* Flush the DTE entry */
1953
	device_flush_dte(dev_data);
1954 1955 1956 1957 1958 1959
}

/*
 * If a device is not yet associated with a domain, this function does
 * assigns it visible for the hardware
 */
1960
static int __attach_device(struct iommu_dev_data *dev_data,
1961
			   struct protection_domain *domain)
1962
{
1963
	int ret;
1964

1965 1966 1967
	/* lock domain */
	spin_lock(&domain->lock);

1968 1969
	if (dev_data->alias_data != NULL) {
		struct iommu_dev_data *alias_data = dev_data->alias_data;
1970

1971 1972 1973 1974 1975
		/* Some sanity checks */
		ret = -EBUSY;
		if (alias_data->domain != NULL &&
				alias_data->domain != domain)
			goto out_unlock;
1976

1977 1978 1979
		if (dev_data->domain != NULL &&
				dev_data->domain != domain)
			goto out_unlock;
1980

1981
		/* Do real assignment */
1982
		if (alias_data->domain == NULL)
1983
			do_attach(alias_data, domain);
1984 1985

		atomic_inc(&alias_data->bind);
1986
	}
1987

1988
	if (dev_data->domain == NULL)
1989
		do_attach(dev_data, domain);
1990

1991 1992
	atomic_inc(&dev_data->bind);

1993 1994 1995 1996
	ret = 0;

out_unlock:

1997 1998
	/* ready */
	spin_unlock(&domain->lock);
1999

2000
	return ret;
2001
}
2002

2003 2004 2005 2006 2007 2008 2009 2010

static void pdev_iommuv2_disable(struct pci_dev *pdev)
{
	pci_disable_ats(pdev);
	pci_disable_pri(pdev);
	pci_disable_pasid(pdev);
}

2011 2012 2013 2014 2015 2016
/* FIXME: Change generic reset-function to do the same */
static int pri_reset_while_enabled(struct pci_dev *pdev)
{
	u16 control;
	int pos;

2017
	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2018 2019 2020
	if (!pos)
		return -EINVAL;

2021 2022 2023
	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	control |= PCI_PRI_CTRL_RESET;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2024 2025 2026 2027

	return 0;
}

2028 2029
static int pdev_iommuv2_enable(struct pci_dev *pdev)
{
2030 2031 2032 2033 2034 2035 2036 2037
	bool reset_enable;
	int reqs, ret;

	/* FIXME: Hardcode number of outstanding requests for now */
	reqs = 32;
	if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
		reqs = 1;
	reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048

	/* Only allow access to user-accessible pages */
	ret = pci_enable_pasid(pdev, 0);
	if (ret)
		goto out_err;

	/* First reset the PRI state of the device */
	ret = pci_reset_pri(pdev);
	if (ret)
		goto out_err;

2049 2050
	/* Enable PRI */
	ret = pci_enable_pri(pdev, reqs);
2051 2052 2053
	if (ret)
		goto out_err;

2054 2055 2056 2057 2058 2059
	if (reset_enable) {
		ret = pri_reset_while_enabled(pdev);
		if (ret)
			goto out_err;
	}

2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072
	ret = pci_enable_ats(pdev, PAGE_SHIFT);
	if (ret)
		goto out_err;

	return 0;

out_err:
	pci_disable_pri(pdev);
	pci_disable_pasid(pdev);

	return ret;
}

2073
/* FIXME: Move this to PCI code */
2074
#define PCI_PRI_TLP_OFF		(1 << 15)
2075 2076 2077

bool pci_pri_tlp_required(struct pci_dev *pdev)
{
2078
	u16 status;
2079 2080
	int pos;

2081
	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2082 2083 2084
	if (!pos)
		return false;

2085
	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2086

2087
	return (status & PCI_PRI_TLP_OFF) ? true : false;
2088 2089
}

2090 2091 2092 2093
/*
 * If a device is not yet associated with a domain, this function does
 * assigns it visible for the hardware
 */
2094 2095
static int attach_device(struct device *dev,
			 struct protection_domain *domain)
2096
{
2097
	struct pci_dev *pdev = to_pci_dev(dev);
2098
	struct iommu_dev_data *dev_data;
2099
	unsigned long flags;
2100
	int ret;
2101

2102 2103
	dev_data = get_dev_data(dev);

2104 2105 2106 2107 2108 2109 2110 2111 2112
	if (domain->flags & PD_IOMMUV2_MASK) {
		if (!dev_data->iommu_v2 || !dev_data->passthrough)
			return -EINVAL;

		if (pdev_iommuv2_enable(pdev) != 0)
			return -EINVAL;

		dev_data->ats.enabled = true;
		dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
2113
		dev_data->pri_tlp     = pci_pri_tlp_required(pdev);
2114 2115
	} else if (amd_iommu_iotlb_sup &&
		   pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2116 2117 2118
		dev_data->ats.enabled = true;
		dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
	}
2119

2120
	write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2121
	ret = __attach_device(dev_data, domain);
2122 2123
	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);

2124 2125 2126 2127 2128
	/*
	 * We might boot into a crash-kernel here. The crashed kernel
	 * left the caches in the IOMMU dirty. So we have to flush
	 * here to evict all dirty stuff.
	 */
2129
	domain_flush_tlb_pde(domain);
2130 2131

	return ret;
2132 2133
}

2134 2135 2136
/*
 * Removes a device from a protection domain (unlocked)
 */
2137
static void __detach_device(struct iommu_dev_data *dev_data)
2138
{
2139
	struct protection_domain *domain;
2140
	unsigned long flags;
2141

2142
	BUG_ON(!dev_data->domain);
2143

2144 2145 2146
	domain = dev_data->domain;

	spin_lock_irqsave(&domain->lock, flags);
2147

2148 2149 2150
	if (dev_data->alias_data != NULL) {
		struct iommu_dev_data *alias_data = dev_data->alias_data;

2151
		if (atomic_dec_and_test(&alias_data->bind))
2152
			do_detach(alias_data);
2153 2154
	}

2155
	if (atomic_dec_and_test(&dev_data->bind))
2156
		do_detach(dev_data);
2157

2158
	spin_unlock_irqrestore(&domain->lock, flags);
2159 2160 2161

	/*
	 * If we run in passthrough mode the device must be assigned to the
2162 2163
	 * passthrough domain if it is detached from any other domain.
	 * Make sure we can deassign from the pt_domain itself.
2164
	 */
2165
	if (dev_data->passthrough &&
2166
	    (dev_data->domain == NULL && domain != pt_domain))
2167
		__attach_device(dev_data, pt_domain);
2168 2169 2170 2171 2172
}

/*
 * Removes a device from a protection domain (with devtable_lock held)
 */
2173
static void detach_device(struct device *dev)
2174
{
2175
	struct protection_domain *domain;
2176
	struct iommu_dev_data *dev_data;
2177 2178
	unsigned long flags;

2179
	dev_data = get_dev_data(dev);
2180
	domain   = dev_data->domain;
2181

2182 2183
	/* lock device table */
	write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2184
	__detach_device(dev_data);
2185
	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2186

2187 2188 2189
	if (domain->flags & PD_IOMMUV2_MASK)
		pdev_iommuv2_disable(to_pci_dev(dev));
	else if (dev_data->ats.enabled)
2190
		pci_disable_ats(to_pci_dev(dev));
2191 2192

	dev_data->ats.enabled = false;
2193
}
2194

2195 2196 2197 2198 2199 2200
/*
 * Find out the protection domain structure for a given PCI device. This
 * will give us the pointer to the page table root for example.
 */
static struct protection_domain *domain_for_device(struct device *dev)
{
2201
	struct iommu_dev_data *dev_data;
2202
	struct protection_domain *dom = NULL;
2203 2204
	unsigned long flags;

2205
	dev_data   = get_dev_data(dev);
2206

2207 2208
	if (dev_data->domain)
		return dev_data->domain;
2209

2210 2211
	if (dev_data->alias_data != NULL) {
		struct iommu_dev_data *alias_data = dev_data->alias_data;
2212 2213 2214 2215 2216 2217 2218 2219

		read_lock_irqsave(&amd_iommu_devtable_lock, flags);
		if (alias_data->domain != NULL) {
			__attach_device(dev_data, alias_data->domain);
			dom = alias_data->domain;
		}
		read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
	}
2220 2221 2222 2223

	return dom;
}

2224 2225 2226 2227
static int device_change_notifier(struct notifier_block *nb,
				  unsigned long action, void *data)
{
	struct dma_ops_domain *dma_domain;
2228 2229 2230
	struct protection_domain *domain;
	struct iommu_dev_data *dev_data;
	struct device *dev = data;
2231
	struct amd_iommu *iommu;
2232
	unsigned long flags;
2233
	u16 devid;
2234

2235 2236
	if (!check_device(dev))
		return 0;
2237

2238 2239 2240
	devid    = get_device_id(dev);
	iommu    = amd_iommu_rlookup_table[devid];
	dev_data = get_dev_data(dev);
2241 2242

	switch (action) {
2243
	case BUS_NOTIFY_UNBOUND_DRIVER:
2244 2245 2246

		domain = domain_for_device(dev);

2247 2248
		if (!domain)
			goto out;
2249
		if (dev_data->passthrough)
2250
			break;
2251
		detach_device(dev);
2252 2253
		break;
	case BUS_NOTIFY_ADD_DEVICE:
2254 2255 2256 2257 2258

		iommu_init_device(dev);

		domain = domain_for_device(dev);

2259 2260 2261 2262
		/* allocate a protection domain if a device is added */
		dma_domain = find_protection_domain(devid);
		if (dma_domain)
			goto out;
2263
		dma_domain = dma_ops_domain_alloc();
2264 2265 2266 2267 2268 2269 2270 2271
		if (!dma_domain)
			goto out;
		dma_domain->target_dev = devid;

		spin_lock_irqsave(&iommu_pd_list_lock, flags);
		list_add_tail(&dma_domain->list, &iommu_pd_list);
		spin_unlock_irqrestore(&iommu_pd_list_lock, flags);

2272 2273 2274 2275 2276 2277 2278
		dev_data = get_dev_data(dev);

		if (!dev_data->passthrough)
			dev->archdata.dma_ops = &amd_iommu_dma_ops;
		else
			dev->archdata.dma_ops = &nommu_dma_ops;

2279
		break;
2280 2281 2282 2283
	case BUS_NOTIFY_DEL_DEVICE:

		iommu_uninit_device(dev);

2284 2285 2286 2287 2288 2289 2290 2291 2292 2293
	default:
		goto out;
	}

	iommu_completion_wait(iommu);

out:
	return 0;
}

2294
static struct notifier_block device_nb = {
2295 2296
	.notifier_call = device_change_notifier,
};
2297

2298 2299 2300 2301 2302
void amd_iommu_init_notifier(void)
{
	bus_register_notifier(&pci_bus_type, &device_nb);
}

2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315
/*****************************************************************************
 *
 * The next functions belong to the dma_ops mapping/unmapping code.
 *
 *****************************************************************************/

/*
 * In the dma_ops path we only have the struct device. This function
 * finds the corresponding IOMMU, the protection domain and the
 * requestor id for a given device.
 * If the device is not yet associated with a domain this is also done
 * in this function.
 */
2316
static struct protection_domain *get_domain(struct device *dev)
2317
{
2318
	struct protection_domain *domain;
2319
	struct dma_ops_domain *dma_dom;
2320
	u16 devid = get_device_id(dev);
2321

2322
	if (!check_device(dev))
2323
		return ERR_PTR(-EINVAL);
2324

2325 2326 2327
	domain = domain_for_device(dev);
	if (domain != NULL && !dma_ops_domain(domain))
		return ERR_PTR(-EBUSY);
2328

2329 2330
	if (domain != NULL)
		return domain;
2331

2332
	/* Device not bount yet - bind it */
2333
	dma_dom = find_protection_domain(devid);
2334
	if (!dma_dom)
2335 2336
		dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
	attach_device(dev, &dma_dom->domain);
2337
	DUMP_printk("Using protection domain %d for device %s\n",
2338
		    dma_dom->domain.id, dev_name(dev));
2339

2340
	return &dma_dom->domain;
2341 2342
}

2343 2344
static void update_device_table(struct protection_domain *domain)
{
2345
	struct iommu_dev_data *dev_data;
2346

2347 2348
	list_for_each_entry(dev_data, &domain->dev_list, list)
		set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2349 2350 2351 2352 2353 2354 2355 2356
}

static void update_domain(struct protection_domain *domain)
{
	if (!domain->updated)
		return;

	update_device_table(domain);
2357 2358 2359

	domain_flush_devices(domain);
	domain_flush_tlb_pde(domain);
2360 2361 2362 2363

	domain->updated = false;
}

2364 2365 2366 2367 2368 2369
/*
 * This function fetches the PTE for a given address in the aperture
 */
static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
			    unsigned long address)
{
2370
	struct aperture_range *aperture;
2371 2372
	u64 *pte, *pte_page;

2373 2374 2375 2376 2377
	aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
	if (!aperture)
		return NULL;

	pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2378
	if (!pte) {
2379
		pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2380
				GFP_ATOMIC);
2381 2382
		aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
	} else
2383
		pte += PM_LEVEL_INDEX(0, address);
2384

2385
	update_domain(&dom->domain);
2386 2387 2388 2389

	return pte;
}

2390 2391 2392 2393
/*
 * This is the generic map function. It maps one 4kb page at paddr to
 * the given address in the DMA address space for the domain.
 */
2394
static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2395 2396 2397 2398 2399 2400 2401 2402 2403 2404
				     unsigned long address,
				     phys_addr_t paddr,
				     int direction)
{
	u64 *pte, __pte;

	WARN_ON(address > dom->aperture_size);

	paddr &= PAGE_MASK;

2405
	pte  = dma_ops_get_pte(dom, address);
2406
	if (!pte)
2407
		return DMA_ERROR_CODE;
2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424

	__pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;

	if (direction == DMA_TO_DEVICE)
		__pte |= IOMMU_PTE_IR;
	else if (direction == DMA_FROM_DEVICE)
		__pte |= IOMMU_PTE_IW;
	else if (direction == DMA_BIDIRECTIONAL)
		__pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;

	WARN_ON(*pte);

	*pte = __pte;

	return (dma_addr_t)address;
}

2425 2426 2427
/*
 * The generic unmapping function for on page in the DMA address space.
 */
2428
static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2429 2430
				 unsigned long address)
{
2431
	struct aperture_range *aperture;
2432 2433 2434 2435 2436
	u64 *pte;

	if (address >= dom->aperture_size)
		return;

2437 2438 2439 2440 2441 2442 2443
	aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
	if (!aperture)
		return;

	pte  = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
	if (!pte)
		return;
2444

2445
	pte += PM_LEVEL_INDEX(0, address);
2446 2447 2448 2449 2450 2451

	WARN_ON(!*pte);

	*pte = 0ULL;
}

2452 2453
/*
 * This function contains common code for mapping of a physically
2454 2455
 * contiguous memory region into DMA address space. It is used by all
 * mapping functions provided with this IOMMU driver.
2456 2457
 * Must be called with the domain lock held.
 */
2458 2459 2460 2461
static dma_addr_t __map_single(struct device *dev,
			       struct dma_ops_domain *dma_dom,
			       phys_addr_t paddr,
			       size_t size,
2462
			       int dir,
2463 2464
			       bool align,
			       u64 dma_mask)
2465 2466
{
	dma_addr_t offset = paddr & ~PAGE_MASK;
2467
	dma_addr_t address, start, ret;
2468
	unsigned int pages;
2469
	unsigned long align_mask = 0;
2470 2471
	int i;

2472
	pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2473 2474
	paddr &= PAGE_MASK;

2475 2476
	INC_STATS_COUNTER(total_map_requests);

2477 2478 2479
	if (pages > 1)
		INC_STATS_COUNTER(cross_page);

2480 2481 2482
	if (align)
		align_mask = (1UL << get_order(size)) - 1;

2483
retry:
2484 2485
	address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
					  dma_mask);
2486
	if (unlikely(address == DMA_ERROR_CODE)) {
2487 2488 2489 2490 2491 2492 2493
		/*
		 * setting next_address here will let the address
		 * allocator only scan the new allocated range in the
		 * first run. This is a small optimization.
		 */
		dma_dom->next_address = dma_dom->aperture_size;

2494
		if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2495 2496 2497
			goto out;

		/*
2498
		 * aperture was successfully enlarged by 128 MB, try
2499 2500 2501 2502
		 * allocation again
		 */
		goto retry;
	}
2503 2504 2505

	start = address;
	for (i = 0; i < pages; ++i) {
2506
		ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2507
		if (ret == DMA_ERROR_CODE)
2508 2509
			goto out_unmap;

2510 2511 2512 2513 2514
		paddr += PAGE_SIZE;
		start += PAGE_SIZE;
	}
	address += offset;

2515 2516
	ADD_STATS_COUNTER(alloced_io_mem, size);

2517
	if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2518
		domain_flush_tlb(&dma_dom->domain);
2519
		dma_dom->need_flush = false;
2520
	} else if (unlikely(amd_iommu_np_cache))
2521
		domain_flush_pages(&dma_dom->domain, address, size);
2522

2523 2524
out:
	return address;
2525 2526 2527 2528 2529

out_unmap:

	for (--i; i >= 0; --i) {
		start -= PAGE_SIZE;
2530
		dma_ops_domain_unmap(dma_dom, start);
2531 2532 2533 2534
	}

	dma_ops_free_addresses(dma_dom, address, pages);

2535
	return DMA_ERROR_CODE;
2536 2537
}

2538 2539 2540 2541
/*
 * Does the reverse of the __map_single function. Must be called with
 * the domain lock held too
 */
2542
static void __unmap_single(struct dma_ops_domain *dma_dom,
2543 2544 2545 2546
			   dma_addr_t dma_addr,
			   size_t size,
			   int dir)
{
2547
	dma_addr_t flush_addr;
2548 2549 2550
	dma_addr_t i, start;
	unsigned int pages;

2551
	if ((dma_addr == DMA_ERROR_CODE) ||
2552
	    (dma_addr + size > dma_dom->aperture_size))
2553 2554
		return;

2555
	flush_addr = dma_addr;
2556
	pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2557 2558 2559 2560
	dma_addr &= PAGE_MASK;
	start = dma_addr;

	for (i = 0; i < pages; ++i) {
2561
		dma_ops_domain_unmap(dma_dom, start);
2562 2563 2564
		start += PAGE_SIZE;
	}

2565 2566
	SUB_STATS_COUNTER(alloced_io_mem, size);

2567
	dma_ops_free_addresses(dma_dom, dma_addr, pages);
2568

2569
	if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2570
		domain_flush_pages(&dma_dom->domain, flush_addr, size);
2571 2572
		dma_dom->need_flush = false;
	}
2573 2574
}

2575 2576 2577
/*
 * The exported map_single function for dma_ops.
 */
2578 2579 2580 2581
static dma_addr_t map_page(struct device *dev, struct page *page,
			   unsigned long offset, size_t size,
			   enum dma_data_direction dir,
			   struct dma_attrs *attrs)
2582 2583 2584 2585
{
	unsigned long flags;
	struct protection_domain *domain;
	dma_addr_t addr;
2586
	u64 dma_mask;
2587
	phys_addr_t paddr = page_to_phys(page) + offset;
2588

2589 2590
	INC_STATS_COUNTER(cnt_map_single);

2591 2592
	domain = get_domain(dev);
	if (PTR_ERR(domain) == -EINVAL)
2593
		return (dma_addr_t)paddr;
2594 2595
	else if (IS_ERR(domain))
		return DMA_ERROR_CODE;
2596

2597 2598
	dma_mask = *dev->dma_mask;

2599
	spin_lock_irqsave(&domain->lock, flags);
2600

2601
	addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2602
			    dma_mask);
2603
	if (addr == DMA_ERROR_CODE)
2604 2605
		goto out;

2606
	domain_flush_complete(domain);
2607 2608 2609 2610 2611 2612 2613

out:
	spin_unlock_irqrestore(&domain->lock, flags);

	return addr;
}

2614 2615 2616
/*
 * The exported unmap_single function for dma_ops.
 */
2617 2618
static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
		       enum dma_data_direction dir, struct dma_attrs *attrs)
2619 2620 2621 2622
{
	unsigned long flags;
	struct protection_domain *domain;

2623 2624
	INC_STATS_COUNTER(cnt_unmap_single);

2625 2626
	domain = get_domain(dev);
	if (IS_ERR(domain))
2627 2628
		return;

2629 2630
	spin_lock_irqsave(&domain->lock, flags);

2631
	__unmap_single(domain->priv, dma_addr, size, dir);
2632

2633
	domain_flush_complete(domain);
2634 2635 2636 2637

	spin_unlock_irqrestore(&domain->lock, flags);
}

2638 2639 2640 2641
/*
 * This is a special map_sg function which is used if we should map a
 * device which is not handled by an AMD IOMMU in the system.
 */
2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655
static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
			   int nelems, int dir)
{
	struct scatterlist *s;
	int i;

	for_each_sg(sglist, s, nelems, i) {
		s->dma_address = (dma_addr_t)sg_phys(s);
		s->dma_length  = s->length;
	}

	return nelems;
}

2656 2657 2658 2659
/*
 * The exported map_sg function for dma_ops (handles scatter-gather
 * lists).
 */
2660
static int map_sg(struct device *dev, struct scatterlist *sglist,
2661 2662
		  int nelems, enum dma_data_direction dir,
		  struct dma_attrs *attrs)
2663 2664 2665 2666 2667 2668 2669
{
	unsigned long flags;
	struct protection_domain *domain;
	int i;
	struct scatterlist *s;
	phys_addr_t paddr;
	int mapped_elems = 0;
2670
	u64 dma_mask;
2671

2672 2673
	INC_STATS_COUNTER(cnt_map_sg);

2674 2675
	domain = get_domain(dev);
	if (PTR_ERR(domain) == -EINVAL)
2676
		return map_sg_no_iommu(dev, sglist, nelems, dir);
2677 2678
	else if (IS_ERR(domain))
		return 0;
2679

2680
	dma_mask = *dev->dma_mask;
2681 2682 2683 2684 2685 2686

	spin_lock_irqsave(&domain->lock, flags);

	for_each_sg(sglist, s, nelems, i) {
		paddr = sg_phys(s);

2687
		s->dma_address = __map_single(dev, domain->priv,
2688 2689
					      paddr, s->length, dir, false,
					      dma_mask);
2690 2691 2692 2693 2694 2695 2696 2697

		if (s->dma_address) {
			s->dma_length = s->length;
			mapped_elems++;
		} else
			goto unmap;
	}

2698
	domain_flush_complete(domain);
2699 2700 2701 2702 2703 2704 2705 2706

out:
	spin_unlock_irqrestore(&domain->lock, flags);

	return mapped_elems;
unmap:
	for_each_sg(sglist, s, mapped_elems, i) {
		if (s->dma_address)
2707
			__unmap_single(domain->priv, s->dma_address,
2708 2709 2710 2711 2712 2713 2714 2715 2716
				       s->dma_length, dir);
		s->dma_address = s->dma_length = 0;
	}

	mapped_elems = 0;

	goto out;
}

2717 2718 2719 2720
/*
 * The exported map_sg function for dma_ops (handles scatter-gather
 * lists).
 */
2721
static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2722 2723
		     int nelems, enum dma_data_direction dir,
		     struct dma_attrs *attrs)
2724 2725 2726 2727 2728 2729
{
	unsigned long flags;
	struct protection_domain *domain;
	struct scatterlist *s;
	int i;

2730 2731
	INC_STATS_COUNTER(cnt_unmap_sg);

2732 2733
	domain = get_domain(dev);
	if (IS_ERR(domain))
2734 2735
		return;

2736 2737 2738
	spin_lock_irqsave(&domain->lock, flags);

	for_each_sg(sglist, s, nelems, i) {
2739
		__unmap_single(domain->priv, s->dma_address,
2740 2741 2742 2743
			       s->dma_length, dir);
		s->dma_address = s->dma_length = 0;
	}

2744
	domain_flush_complete(domain);
2745 2746 2747 2748

	spin_unlock_irqrestore(&domain->lock, flags);
}

2749 2750 2751
/*
 * The exported alloc_coherent function for dma_ops.
 */
2752
static void *alloc_coherent(struct device *dev, size_t size,
2753 2754
			    dma_addr_t *dma_addr, gfp_t flag,
			    struct dma_attrs *attrs)
2755 2756 2757 2758 2759
{
	unsigned long flags;
	void *virt_addr;
	struct protection_domain *domain;
	phys_addr_t paddr;
2760
	u64 dma_mask = dev->coherent_dma_mask;
2761

2762 2763
	INC_STATS_COUNTER(cnt_alloc_coherent);

2764 2765
	domain = get_domain(dev);
	if (PTR_ERR(domain) == -EINVAL) {
2766 2767 2768
		virt_addr = (void *)__get_free_pages(flag, get_order(size));
		*dma_addr = __pa(virt_addr);
		return virt_addr;
2769 2770
	} else if (IS_ERR(domain))
		return NULL;
2771

2772 2773 2774
	dma_mask  = dev->coherent_dma_mask;
	flag     &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
	flag     |= __GFP_ZERO;
2775 2776 2777

	virt_addr = (void *)__get_free_pages(flag, get_order(size));
	if (!virt_addr)
2778
		return NULL;
2779 2780 2781

	paddr = virt_to_phys(virt_addr);

2782 2783 2784
	if (!dma_mask)
		dma_mask = *dev->dma_mask;

2785 2786
	spin_lock_irqsave(&domain->lock, flags);

2787
	*dma_addr = __map_single(dev, domain->priv, paddr,
2788
				 size, DMA_BIDIRECTIONAL, true, dma_mask);
2789

2790
	if (*dma_addr == DMA_ERROR_CODE) {
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Jiri Slaby committed
2791
		spin_unlock_irqrestore(&domain->lock, flags);
2792
		goto out_free;
Jiri Slaby's avatar
Jiri Slaby committed
2793
	}
2794

2795
	domain_flush_complete(domain);
2796 2797 2798 2799

	spin_unlock_irqrestore(&domain->lock, flags);

	return virt_addr;
2800 2801 2802 2803 2804 2805

out_free:

	free_pages((unsigned long)virt_addr, get_order(size));

	return NULL;
2806 2807
}

2808 2809 2810
/*
 * The exported free_coherent function for dma_ops.
 */
2811
static void free_coherent(struct device *dev, size_t size,
2812 2813
			  void *virt_addr, dma_addr_t dma_addr,
			  struct dma_attrs *attrs)
2814 2815 2816 2817
{
	unsigned long flags;
	struct protection_domain *domain;

2818 2819
	INC_STATS_COUNTER(cnt_free_coherent);

2820 2821
	domain = get_domain(dev);
	if (IS_ERR(domain))
2822 2823
		goto free_mem;

2824 2825
	spin_lock_irqsave(&domain->lock, flags);

2826
	__unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2827

2828
	domain_flush_complete(domain);
2829 2830 2831 2832 2833 2834 2835

	spin_unlock_irqrestore(&domain->lock, flags);

free_mem:
	free_pages((unsigned long)virt_addr, get_order(size));
}

2836 2837 2838 2839 2840 2841
/*
 * This function is called by the DMA layer to find out if we can handle a
 * particular device. It is part of the dma_ops.
 */
static int amd_iommu_dma_supported(struct device *dev, u64 mask)
{
2842
	return check_device(dev);
2843 2844
}

2845
/*
2846 2847
 * The function for pre-allocating protection domains.
 *
2848 2849 2850 2851
 * If the driver core informs the DMA layer if a driver grabs a device
 * we don't need to preallocate the protection domains anymore.
 * For now we have to.
 */
Steffen Persvold's avatar
Steffen Persvold committed
2852
static void __init prealloc_protection_domains(void)
2853
{
2854
	struct iommu_dev_data *dev_data;
2855
	struct dma_ops_domain *dma_dom;
2856
	struct pci_dev *dev = NULL;
2857
	u16 devid;
2858

2859
	for_each_pci_dev(dev) {
2860 2861 2862

		/* Do we handle this device? */
		if (!check_device(&dev->dev))
2863
			continue;
2864

2865 2866 2867 2868 2869 2870 2871 2872 2873 2874
		dev_data = get_dev_data(&dev->dev);
		if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
			/* Make sure passthrough domain is allocated */
			alloc_passthrough_domain();
			dev_data->passthrough = true;
			attach_device(&dev->dev, pt_domain);
			pr_info("AMD-Vi: Using passthough domain for device %s\n",
				dev_name(&dev->dev));
		}

2875
		/* Is there already any domain for it? */
2876
		if (domain_for_device(&dev->dev))
2877
			continue;
2878 2879 2880

		devid = get_device_id(&dev->dev);

2881
		dma_dom = dma_ops_domain_alloc();
2882 2883 2884
		if (!dma_dom)
			continue;
		init_unity_mappings_for_device(dma_dom, devid);
2885 2886
		dma_dom->target_dev = devid;

2887
		attach_device(&dev->dev, &dma_dom->domain);
2888

2889
		list_add_tail(&dma_dom->list, &iommu_pd_list);
2890 2891 2892
	}
}

2893
static struct dma_map_ops amd_iommu_dma_ops = {
2894 2895
	.alloc = alloc_coherent,
	.free = free_coherent,
2896 2897
	.map_page = map_page,
	.unmap_page = unmap_page,
2898 2899
	.map_sg = map_sg,
	.unmap_sg = unmap_sg,
2900
	.dma_supported = amd_iommu_dma_supported,
2901 2902
};

2903 2904
static unsigned device_dma_ops_init(void)
{
2905
	struct iommu_dev_data *dev_data;
2906 2907 2908 2909 2910
	struct pci_dev *pdev = NULL;
	unsigned unhandled = 0;

	for_each_pci_dev(pdev) {
		if (!check_device(&pdev->dev)) {
2911 2912 2913

			iommu_ignore_device(&pdev->dev);

2914 2915 2916 2917
			unhandled += 1;
			continue;
		}

2918 2919 2920 2921 2922 2923
		dev_data = get_dev_data(&pdev->dev);

		if (!dev_data->passthrough)
			pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
		else
			pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2924 2925 2926 2927 2928
	}

	return unhandled;
}

2929 2930 2931
/*
 * The function which clues the AMD IOMMU driver into dma_ops.
 */
2932 2933 2934

void __init amd_iommu_init_api(void)
{
2935
	bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2936 2937
}

2938 2939 2940
int __init amd_iommu_init_dma_ops(void)
{
	struct amd_iommu *iommu;
2941
	int ret, unhandled;
2942

2943 2944 2945 2946 2947
	/*
	 * first allocate a default protection domain for every IOMMU we
	 * found in the system. Devices not assigned to any other
	 * protection domain will be assigned to the default one.
	 */
2948
	for_each_iommu(iommu) {
2949
		iommu->default_dom = dma_ops_domain_alloc();
2950 2951
		if (iommu->default_dom == NULL)
			return -ENOMEM;
2952
		iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2953 2954 2955 2956 2957
		ret = iommu_init_unity_mappings(iommu);
		if (ret)
			goto free_domains;
	}

2958
	/*
2959
	 * Pre-allocate the protection domains for each device.
2960
	 */
2961
	prealloc_protection_domains();
2962 2963

	iommu_detected = 1;
2964
	swiotlb = 0;
2965

2966
	/* Make the driver finally visible to the drivers */
2967 2968 2969 2970 2971
	unhandled = device_dma_ops_init();
	if (unhandled && max_pfn > MAX_DMA32_PFN) {
		/* There are unhandled devices - initialize swiotlb for them */
		swiotlb = 1;
	}
2972

2973 2974
	amd_iommu_stats_init();

2975 2976 2977 2978
	return 0;

free_domains:

2979
	for_each_iommu(iommu) {
2980 2981 2982 2983 2984 2985
		if (iommu->default_dom)
			dma_ops_domain_free(iommu->default_dom);
	}

	return ret;
}
2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998

/*****************************************************************************
 *
 * The following functions belong to the exported interface of AMD IOMMU
 *
 * This interface allows access to lower level functions of the IOMMU
 * like protection domain handling and assignement of devices to domains
 * which is not possible with the dma_ops interface.
 *
 *****************************************************************************/

static void cleanup_domain(struct protection_domain *domain)
{
2999
	struct iommu_dev_data *dev_data, *next;
3000 3001 3002 3003
	unsigned long flags;

	write_lock_irqsave(&amd_iommu_devtable_lock, flags);

3004
	list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
3005
		__detach_device(dev_data);
3006 3007
		atomic_set(&dev_data->bind, 0);
	}
3008 3009 3010 3011

	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
}

3012 3013 3014 3015 3016
static void protection_domain_free(struct protection_domain *domain)
{
	if (!domain)
		return;

3017 3018
	del_domain_from_list(domain);

3019 3020 3021 3022 3023 3024 3025
	if (domain->id)
		domain_id_free(domain->id);

	kfree(domain);
}

static struct protection_domain *protection_domain_alloc(void)
3026 3027 3028 3029 3030
{
	struct protection_domain *domain;

	domain = kzalloc(sizeof(*domain), GFP_KERNEL);
	if (!domain)
3031
		return NULL;
3032 3033

	spin_lock_init(&domain->lock);
3034
	mutex_init(&domain->api_lock);
3035 3036
	domain->id = domain_id_alloc();
	if (!domain->id)
3037
		goto out_err;
3038
	INIT_LIST_HEAD(&domain->dev_list);
3039

3040 3041
	add_domain_to_list(domain);

3042 3043 3044 3045 3046 3047 3048 3049
	return domain;

out_err:
	kfree(domain);

	return NULL;
}

3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063
static int __init alloc_passthrough_domain(void)
{
	if (pt_domain != NULL)
		return 0;

	/* allocate passthrough domain */
	pt_domain = protection_domain_alloc();
	if (!pt_domain)
		return -ENOMEM;

	pt_domain->mode = PAGE_MODE_NONE;

	return 0;
}
3064 3065 3066 3067 3068 3069
static int amd_iommu_domain_init(struct iommu_domain *dom)
{
	struct protection_domain *domain;

	domain = protection_domain_alloc();
	if (!domain)
3070
		goto out_free;
3071 3072

	domain->mode    = PAGE_MODE_3_LEVEL;
3073 3074 3075 3076
	domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
	if (!domain->pt_root)
		goto out_free;

3077 3078
	domain->iommu_domain = dom;

3079 3080 3081 3082 3083
	dom->priv = domain;

	return 0;

out_free:
3084
	protection_domain_free(domain);
3085 3086 3087 3088

	return -ENOMEM;
}

3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100
static void amd_iommu_domain_destroy(struct iommu_domain *dom)
{
	struct protection_domain *domain = dom->priv;

	if (!domain)
		return;

	if (domain->dev_cnt > 0)
		cleanup_domain(domain);

	BUG_ON(domain->dev_cnt != 0);

3101 3102
	if (domain->mode != PAGE_MODE_NONE)
		free_pagetable(domain);
3103

3104 3105 3106
	if (domain->flags & PD_IOMMUV2_MASK)
		free_gcr3_table(domain);

3107
	protection_domain_free(domain);
3108 3109 3110 3111

	dom->priv = NULL;
}

3112 3113 3114
static void amd_iommu_detach_device(struct iommu_domain *dom,
				    struct device *dev)
{
3115
	struct iommu_dev_data *dev_data = dev->archdata.iommu;
3116 3117 3118
	struct amd_iommu *iommu;
	u16 devid;

3119
	if (!check_device(dev))
3120 3121
		return;

3122
	devid = get_device_id(dev);
3123

3124
	if (dev_data->domain != NULL)
3125
		detach_device(dev);
3126 3127 3128 3129 3130 3131 3132 3133

	iommu = amd_iommu_rlookup_table[devid];
	if (!iommu)
		return;

	iommu_completion_wait(iommu);
}

3134 3135 3136 3137
static int amd_iommu_attach_device(struct iommu_domain *dom,
				   struct device *dev)
{
	struct protection_domain *domain = dom->priv;
3138
	struct iommu_dev_data *dev_data;
3139
	struct amd_iommu *iommu;
3140
	int ret;
3141

3142
	if (!check_device(dev))
3143 3144
		return -EINVAL;

3145 3146
	dev_data = dev->archdata.iommu;

3147
	iommu = amd_iommu_rlookup_table[dev_data->devid];
3148 3149 3150
	if (!iommu)
		return -EINVAL;

3151
	if (dev_data->domain)
3152
		detach_device(dev);
3153

3154
	ret = attach_device(dev, domain);
3155 3156 3157

	iommu_completion_wait(iommu);

3158
	return ret;
3159 3160
}

3161
static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3162
			 phys_addr_t paddr, size_t page_size, int iommu_prot)
3163 3164 3165 3166 3167
{
	struct protection_domain *domain = dom->priv;
	int prot = 0;
	int ret;

3168 3169 3170
	if (domain->mode == PAGE_MODE_NONE)
		return -EINVAL;

3171 3172 3173 3174 3175
	if (iommu_prot & IOMMU_READ)
		prot |= IOMMU_PROT_IR;
	if (iommu_prot & IOMMU_WRITE)
		prot |= IOMMU_PROT_IW;

3176
	mutex_lock(&domain->api_lock);
3177
	ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3178 3179
	mutex_unlock(&domain->api_lock);

3180
	return ret;
3181 3182
}

3183 3184
static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
			   size_t page_size)
3185 3186
{
	struct protection_domain *domain = dom->priv;
3187
	size_t unmap_size;
3188

3189 3190 3191
	if (domain->mode == PAGE_MODE_NONE)
		return -EINVAL;

3192
	mutex_lock(&domain->api_lock);
3193
	unmap_size = iommu_unmap_page(domain, iova, page_size);
3194
	mutex_unlock(&domain->api_lock);
3195

3196
	domain_flush_tlb_pde(domain);
3197

3198
	return unmap_size;
3199 3200
}

3201 3202 3203 3204
static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
					  unsigned long iova)
{
	struct protection_domain *domain = dom->priv;
3205
	unsigned long offset_mask;
3206
	phys_addr_t paddr;
3207
	u64 *pte, __pte;
3208

3209 3210 3211
	if (domain->mode == PAGE_MODE_NONE)
		return iova;

3212
	pte = fetch_pte(domain, iova);
3213

3214
	if (!pte || !IOMMU_PTE_PRESENT(*pte))
3215 3216
		return 0;

3217 3218 3219 3220 3221 3222 3223
	if (PM_PTE_LEVEL(*pte) == 0)
		offset_mask = PAGE_SIZE - 1;
	else
		offset_mask = PTE_PAGE_SIZE(*pte) - 1;

	__pte = *pte & PM_ADDR_MASK;
	paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3224 3225 3226 3227

	return paddr;
}

3228 3229 3230
static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
				    unsigned long cap)
{
3231 3232 3233 3234 3235
	switch (cap) {
	case IOMMU_CAP_CACHE_COHERENCY:
		return 1;
	}

3236 3237 3238
	return 0;
}

3239 3240 3241
static int amd_iommu_device_group(struct device *dev, unsigned int *groupid)
{
	struct iommu_dev_data *dev_data = dev->archdata.iommu;
3242 3243
	struct pci_dev *pdev = to_pci_dev(dev);
	u16 devid;
3244 3245 3246 3247

	if (!dev_data)
		return -ENODEV;

3248 3249 3250 3251 3252 3253 3254
	if (pdev->is_virtfn || !iommu_group_mf)
		devid = dev_data->devid;
	else
		devid = calc_devid(pdev->bus->number,
				   PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));

	*groupid = amd_iommu_alias_table[devid];
3255 3256 3257 3258

	return 0;
}

3259 3260 3261 3262 3263
static struct iommu_ops amd_iommu_ops = {
	.domain_init = amd_iommu_domain_init,
	.domain_destroy = amd_iommu_domain_destroy,
	.attach_dev = amd_iommu_attach_device,
	.detach_dev = amd_iommu_detach_device,
3264 3265
	.map = amd_iommu_map,
	.unmap = amd_iommu_unmap,
3266
	.iova_to_phys = amd_iommu_iova_to_phys,
3267
	.domain_has_cap = amd_iommu_domain_has_cap,
3268
	.device_group = amd_iommu_device_group,
3269
	.pgsize_bitmap	= AMD_IOMMU_PGSIZES,
3270 3271
};

3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283
/*****************************************************************************
 *
 * The next functions do a basic initialization of IOMMU for pass through
 * mode
 *
 * In passthrough mode the IOMMU is initialized and enabled but not used for
 * DMA-API translation.
 *
 *****************************************************************************/

int __init amd_iommu_init_passthrough(void)
{
3284
	struct iommu_dev_data *dev_data;
3285
	struct pci_dev *dev = NULL;
3286
	struct amd_iommu *iommu;
3287
	u16 devid;
3288
	int ret;
3289

3290 3291 3292
	ret = alloc_passthrough_domain();
	if (ret)
		return ret;
3293

3294
	for_each_pci_dev(dev) {
3295
		if (!check_device(&dev->dev))
3296 3297
			continue;

3298 3299 3300
		dev_data = get_dev_data(&dev->dev);
		dev_data->passthrough = true;

3301 3302
		devid = get_device_id(&dev->dev);

3303
		iommu = amd_iommu_rlookup_table[devid];
3304 3305 3306
		if (!iommu)
			continue;

3307
		attach_device(&dev->dev, pt_domain);
3308 3309
	}

3310 3311
	amd_iommu_stats_init();

3312 3313 3314 3315
	pr_info("AMD-Vi: Initialized for Passthrough Mode\n");

	return 0;
}
3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328

/* IOMMUv2 specific functions */
int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
{
	return atomic_notifier_chain_register(&ppr_notifier, nb);
}
EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);

int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
{
	return atomic_notifier_chain_unregister(&ppr_notifier, nb);
}
EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349

void amd_iommu_domain_direct_map(struct iommu_domain *dom)
{
	struct protection_domain *domain = dom->priv;
	unsigned long flags;

	spin_lock_irqsave(&domain->lock, flags);

	/* Update data structure */
	domain->mode    = PAGE_MODE_NONE;
	domain->updated = true;

	/* Make changes visible to IOMMUs */
	update_domain(domain);

	/* Page-table is not visible to IOMMU anymore, so free it */
	free_pagetable(domain);

	spin_unlock_irqrestore(&domain->lock, flags);
}
EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396

int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
{
	struct protection_domain *domain = dom->priv;
	unsigned long flags;
	int levels, ret;

	if (pasids <= 0 || pasids > (PASID_MASK + 1))
		return -EINVAL;

	/* Number of GCR3 table levels required */
	for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
		levels += 1;

	if (levels > amd_iommu_max_glx_val)
		return -EINVAL;

	spin_lock_irqsave(&domain->lock, flags);

	/*
	 * Save us all sanity checks whether devices already in the
	 * domain support IOMMUv2. Just force that the domain has no
	 * devices attached when it is switched into IOMMUv2 mode.
	 */
	ret = -EBUSY;
	if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
		goto out;

	ret = -ENOMEM;
	domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
	if (domain->gcr3_tbl == NULL)
		goto out;

	domain->glx      = levels;
	domain->flags   |= PD_IOMMUV2_MASK;
	domain->updated  = true;

	update_domain(domain);

	ret = 0;

out:
	spin_unlock_irqrestore(&domain->lock, flags);

	return ret;
}
EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
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static int __flush_pasid(struct protection_domain *domain, int pasid,
			 u64 address, bool size)
{
	struct iommu_dev_data *dev_data;
	struct iommu_cmd cmd;
	int i, ret;

	if (!(domain->flags & PD_IOMMUV2_MASK))
		return -EINVAL;

	build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);

	/*
	 * IOMMU TLB needs to be flushed before Device TLB to
	 * prevent device TLB refill from IOMMU TLB
	 */
	for (i = 0; i < amd_iommus_present; ++i) {
		if (domain->dev_iommu[i] == 0)
			continue;

		ret = iommu_queue_command(amd_iommus[i], &cmd);
		if (ret != 0)
			goto out;
	}

	/* Wait until IOMMU TLB flushes are complete */
	domain_flush_complete(domain);

	/* Now flush device TLBs */
	list_for_each_entry(dev_data, &domain->dev_list, list) {
		struct amd_iommu *iommu;
		int qdep;

		BUG_ON(!dev_data->ats.enabled);

		qdep  = dev_data->ats.qdep;
		iommu = amd_iommu_rlookup_table[dev_data->devid];

		build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
				      qdep, address, size);

		ret = iommu_queue_command(iommu, &cmd);
		if (ret != 0)
			goto out;
	}

	/* Wait until all device TLBs are flushed */
	domain_flush_complete(domain);

	ret = 0;

out:

	return ret;
}

static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
				  u64 address)
{
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	INC_STATS_COUNTER(invalidate_iotlb);

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	return __flush_pasid(domain, pasid, address, false);
}

int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
			 u64 address)
{
	struct protection_domain *domain = dom->priv;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&domain->lock, flags);
	ret = __amd_iommu_flush_page(domain, pasid, address);
	spin_unlock_irqrestore(&domain->lock, flags);

	return ret;
}
EXPORT_SYMBOL(amd_iommu_flush_page);

static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
{
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	INC_STATS_COUNTER(invalidate_iotlb_all);

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	return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
			     true);
}

int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
{
	struct protection_domain *domain = dom->priv;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&domain->lock, flags);
	ret = __amd_iommu_flush_tlb(domain, pasid);
	spin_unlock_irqrestore(&domain->lock, flags);

	return ret;
}
EXPORT_SYMBOL(amd_iommu_flush_tlb);

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static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
{
	int index;
	u64 *pte;

	while (true) {

		index = (pasid >> (9 * level)) & 0x1ff;
		pte   = &root[index];

		if (level == 0)
			break;

		if (!(*pte & GCR3_VALID)) {
			if (!alloc)
				return NULL;

			root = (void *)get_zeroed_page(GFP_ATOMIC);
			if (root == NULL)
				return NULL;

			*pte = __pa(root) | GCR3_VALID;
		}

		root = __va(*pte & PAGE_MASK);

		level -= 1;
	}

	return pte;
}

static int __set_gcr3(struct protection_domain *domain, int pasid,
		      unsigned long cr3)
{
	u64 *pte;

	if (domain->mode != PAGE_MODE_NONE)
		return -EINVAL;

	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
	if (pte == NULL)
		return -ENOMEM;

	*pte = (cr3 & PAGE_MASK) | GCR3_VALID;

	return __amd_iommu_flush_tlb(domain, pasid);
}

static int __clear_gcr3(struct protection_domain *domain, int pasid)
{
	u64 *pte;

	if (domain->mode != PAGE_MODE_NONE)
		return -EINVAL;

	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
	if (pte == NULL)
		return 0;

	*pte = 0;

	return __amd_iommu_flush_tlb(domain, pasid);
}

int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
			      unsigned long cr3)
{
	struct protection_domain *domain = dom->priv;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&domain->lock, flags);
	ret = __set_gcr3(domain, pasid, cr3);
	spin_unlock_irqrestore(&domain->lock, flags);

	return ret;
}
EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);

int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
{
	struct protection_domain *domain = dom->priv;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&domain->lock, flags);
	ret = __clear_gcr3(domain, pasid);
	spin_unlock_irqrestore(&domain->lock, flags);

	return ret;
}
EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
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int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
			   int status, int tag)
{
	struct iommu_dev_data *dev_data;
	struct amd_iommu *iommu;
	struct iommu_cmd cmd;

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	INC_STATS_COUNTER(complete_ppr);

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	dev_data = get_dev_data(&pdev->dev);
	iommu    = amd_iommu_rlookup_table[dev_data->devid];

	build_complete_ppr(&cmd, dev_data->devid, pasid, status,
			   tag, dev_data->pri_tlp);

	return iommu_queue_command(iommu, &cmd);
}
EXPORT_SYMBOL(amd_iommu_complete_ppr);
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struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
{
	struct protection_domain *domain;

	domain = get_domain(&pdev->dev);
	if (IS_ERR(domain))
		return NULL;

	/* Only return IOMMUv2 domains */
	if (!(domain->flags & PD_IOMMUV2_MASK))
		return NULL;

	return domain->iommu_domain;
}
EXPORT_SYMBOL(amd_iommu_get_v2_domain);
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void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
{
	struct iommu_dev_data *dev_data;

	if (!amd_iommu_v2_supported())
		return;

	dev_data = get_dev_data(&pdev->dev);
	dev_data->errata |= (1 << erratum);
}
EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
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int amd_iommu_device_info(struct pci_dev *pdev,
                          struct amd_iommu_device_info *info)
{
	int max_pasids;
	int pos;

	if (pdev == NULL || info == NULL)
		return -EINVAL;

	if (!amd_iommu_v2_supported())
		return -EINVAL;

	memset(info, 0, sizeof(*info));

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
	if (pos)
		info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (pos)
		info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (pos) {
		int features;

		max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
		max_pasids = min(max_pasids, (1 << 20));

		info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
		info->max_pasids = min(pci_max_pasids(pdev), max_pasids);

		features = pci_pasid_features(pdev);
		if (features & PCI_PASID_CAP_EXEC)
			info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
		if (features & PCI_PASID_CAP_PRIV)
			info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
	}

	return 0;
}
EXPORT_SYMBOL(amd_iommu_device_info);