p4-clockmod.c 8.87 KB
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/*
 *	Pentium 4/Xeon CPU on demand clock modulation/speed scaling
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 *	(C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
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 *	(C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
 *	(C) 2002 Arjan van de Ven <arjanv@redhat.com>
 *	(C) 2002 Tora T. Engstad
 *	All Rights Reserved
 *
 *	This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 *
 *      The author(s) of this software shall not be held liable for damages
 *      of any nature resulting due to the use of this software. This
 *      software is provided AS-IS with no warranties.
 *	
 *	Date		Errata			Description
 *	20020525	N44, O17	12.5% or 25% DC causes lockup
 *
 */

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#include <linux/config.h>
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#include <linux/kernel.h>
#include <linux/module.h> 
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
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#include <linux/cpumask.h>
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#include <asm/processor.h> 
#include <asm/msr.h>
#include <asm/timex.h>

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#include "speedstep-lib.h"

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#define PFX	"p4-clockmod: "
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/*
 * Duty Cycle (3bits), note DC_DISABLE is not specified in
 * intel docs i just use it to mean disable
 */
enum {
	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
};

#define DC_ENTRIES	8


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static int has_N44_O17_errata[NR_CPUS];
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static unsigned int stock_freq;
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static struct cpufreq_driver p4clockmod_driver;
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static unsigned int cpufreq_p4_get(unsigned int cpu);
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static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
{
	u32 l, h;

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	if (!cpu_online(cpu) || (newstate > DC_DISABLE) || (newstate == DC_RESV))
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		return -EINVAL;
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	rdmsr(MSR_IA32_THERM_STATUS, l, h);
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#if 0
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	if (l & 0x01)
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		printk(KERN_DEBUG PFX "CPU#%d currently thermal throttled\n", cpu);
#endif
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	if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
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		newstate = DC_38PT;

	rdmsr(MSR_IA32_THERM_CONTROL, l, h);
	if (newstate == DC_DISABLE) {
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		/* printk(KERN_INFO PFX "CPU#%d disabling modulation\n", cpu); */
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		wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
	} else {
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		/* printk(KERN_INFO PFX "CPU#%d setting duty cycle to %d%%\n",
			cpu, ((125 * newstate) / 10)); */
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		/* bits 63 - 5	: reserved 
		 * bit  4	: enable/disable
		 * bits 3-1	: duty cycle
		 * bit  0	: reserved
		 */
		l = (l & ~14);
		l = l | (1<<4) | ((newstate & 0x7)<<1);
		wrmsr(MSR_IA32_THERM_CONTROL, l, h);
	}

	return 0;
}


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static struct cpufreq_frequency_table p4clockmod_table[] = {
	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	{DC_DFLT, 0},
	{DC_25PT, 0},
	{DC_38PT, 0},
	{DC_50PT, 0},
	{DC_64PT, 0},
	{DC_75PT, 0},
	{DC_88PT, 0},
	{DC_DISABLE, 0},
	{DC_RESV, CPUFREQ_TABLE_END},
};


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static int cpufreq_p4_target(struct cpufreq_policy *policy,
			     unsigned int target_freq,
			     unsigned int relation)
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{
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	unsigned int    newstate = DC_RESV;
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	struct cpufreq_freqs freqs;
	cpumask_t cpus_allowed, affected_cpu_map;
	int i;
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	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
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		return -EINVAL;
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	freqs.old = cpufreq_p4_get(policy->cpu);
	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;

	if (freqs.new == freqs.old)
		return 0;

	/* switch to physical CPU where state is to be changed*/
	cpus_allowed = current->cpus_allowed;

	/* only run on CPU to be set, or on its sibling */
#ifdef CONFIG_SMP
	affected_cpu_map = cpu_sibling_map[policy->cpu];
#else
	affected_cpu_map = cpumask_of_cpu(policy->cpu);
#endif

	/* notifiers */
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	for_each_cpu_mask(i, affected_cpu_map) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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	}

	/* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
	 * Developer's Manual, Volume 3 
	 */
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	for_each_cpu_mask(i, affected_cpu_map) {
		cpumask_t this_cpu = cpumask_of_cpu(i);
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		set_cpus_allowed(current, this_cpu);
		BUG_ON(smp_processor_id() != i);
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		cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
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	}
	set_cpus_allowed(current, cpus_allowed);

	/* notifiers */
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	for_each_cpu_mask(i, affected_cpu_map) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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	}
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	return 0;
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}


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static int cpufreq_p4_verify(struct cpufreq_policy *policy)
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{
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	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
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}

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static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
{
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	if ((c->x86 == 0x06) && (c->x86_model == 0x09)) {
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		/* Pentium M (Banias) */
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		printk(KERN_WARNING PFX "Warning: Pentium M detected. "
		       "The speedstep_centrino module offers voltage scaling"
		       " in addition of frequency scaling. You should use "
		       "that instead of p4-clockmod, if possible.\n");
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		return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
	}
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	if ((c->x86 == 0x06) && (c->x86_model == 0x13)) {
		/* Pentium M (Dothan) */
		printk(KERN_WARNING PFX "Warning: Pentium M detected. "
		       "The speedstep_centrino module offers voltage scaling"
		       " in addition of frequency scaling. You should use "
		       "that instead of p4-clockmod, if possible.\n");
		/* on P-4s, the TSC runs with constant frequency independent wether
		 * throttling is active or not. */
		p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
		return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
	}

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	if (c->x86 != 0xF) {
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		printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <linux@brodo.de>\n");
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		return 0;
	}

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	/* on P-4s, the TSC runs with constant frequency independent wether
	 * throttling is active or not. */
	p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;

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	if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
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		printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
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		       "The speedstep-ich or acpi cpufreq modules offer "
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		       "voltage scaling in addition of frequency scaling. "
		       "You should use either one instead of p4-clockmod, "
		       "if possible.\n");
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		return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
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	}

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	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
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}

 
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static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
	int cpuid = 0;
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	unsigned int i;

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	/* Errata workaround */
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	cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
	switch (cpuid) {
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	case 0x0f07:
	case 0x0f0a:
	case 0x0f11:
	case 0x0f12:
		has_N44_O17_errata[policy->cpu] = 1;
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	}
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	/* get max frequency */
	stock_freq = cpufreq_p4_get_frequency(c);
	if (!stock_freq)
		return -EINVAL;
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	/* table init */
	for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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		if ((i<2) && (has_N44_O17_errata[policy->cpu]))
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			p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			p4clockmod_table[i].frequency = (stock_freq * i)/8;
	}
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	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
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	/* cpuinfo and default policy values */
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	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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	policy->cpuinfo.transition_latency = 1000000; /* assumed */
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	policy->cur = stock_freq;
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	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
}
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static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
{
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	cpufreq_frequency_table_put_attr(policy->cpu);    
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	return 0;
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}
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static unsigned int cpufreq_p4_get(unsigned int cpu)
{
	cpumask_t cpus_allowed, affected_cpu_map;
	u32 l, h;

	cpus_allowed = current->cpus_allowed;
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        affected_cpu_map = cpumask_of_cpu(cpu);
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	set_cpus_allowed(current, affected_cpu_map);
        BUG_ON(!cpu_isset(smp_processor_id(), affected_cpu_map));

	rdmsr(MSR_IA32_THERM_CONTROL, l, h);

	set_cpus_allowed(current, cpus_allowed);

	if (l & 0x10) {
		l = l >> 1;
		l &= 0x7;
	} else
		l = DC_DISABLE;

	if (l != DC_DISABLE)
		return (stock_freq * l / 8);

	return stock_freq;
}

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static struct freq_attr* p4clockmod_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};
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static struct cpufreq_driver p4clockmod_driver = {
	.verify 	= cpufreq_p4_verify,
	.target		= cpufreq_p4_target,
	.init		= cpufreq_p4_cpu_init,
	.exit		= cpufreq_p4_cpu_exit,
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	.get		= cpufreq_p4_get,
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	.name		= "p4-clockmod",
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	.owner		= THIS_MODULE,
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	.attr		= p4clockmod_attr,
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};


static int __init cpufreq_p4_init(void)
{	
	struct cpuinfo_x86 *c = cpu_data;

	/*
	 * THERM_CONTROL is architectural for IA32 now, so 
	 * we can rely on the capability checks
	 */
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return -ENODEV;

	if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
		!test_bit(X86_FEATURE_ACC, c->x86_capability))
		return -ENODEV;

	printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");

	return cpufreq_register_driver(&p4clockmod_driver);
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}


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static void __exit cpufreq_p4_exit(void)
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{
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	cpufreq_unregister_driver(&p4clockmod_driver);
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}

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MODULE_AUTHOR ("Zwane Mwaikambo <zwane@commfireservices.com>");
MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
MODULE_LICENSE ("GPL");

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late_initcall(cpufreq_p4_init);
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module_exit(cpufreq_p4_exit);