intel_sprite.c 68.2 KB
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/*
 * Copyright © 2011 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *   Jesse Barnes <jbarnes@virtuousgeek.org>
 *
 * New plane/sprite handling.
 *
 * The older chips had a separate interface for programming plane related
 * registers; newer ones are much simpler and we can use the new DRM plane
 * support.
 */
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_fourcc.h>
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#include <drm/drm_rect.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_plane_helper.h>
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#include "intel_drv.h"
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#include "intel_frontbuffer.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_color_mgmt.h>
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bool is_planar_yuv_format(u32 pixelformat)
{
	switch (pixelformat) {
	case DRM_FORMAT_NV12:
	case DRM_FORMAT_P010:
	case DRM_FORMAT_P012:
	case DRM_FORMAT_P016:
		return true;
	default:
		return false;
	}
}

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int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
			     int usecs)
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{
	/* paranoia */
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	if (!adjusted_mode->crtc_htotal)
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		return 1;

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	return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
			    1000 * adjusted_mode->crtc_htotal);
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}

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/* FIXME: We should instead only take spinlocks once for the entire update
 * instead of once per mmio. */
#if IS_ENABLED(CONFIG_PROVE_LOCKING)
#define VBLANK_EVASION_TIME_US 250
#else
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#define VBLANK_EVASION_TIME_US 100
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#endif
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/**
 * intel_pipe_update_start() - start update of a set of display registers
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 * @new_crtc_state: the new crtc state
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 *
 * Mark the start of an update to pipe registers that should be updated
 * atomically regarding vblank. If the next vblank will happens within
 * the next 100 us, this function waits until the vblank passes.
 *
 * After a successful call to this function, interrupts will be disabled
 * until a subsequent call to intel_pipe_update_end(). That is done to
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 * avoid random delays.
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 */
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void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
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	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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	const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
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	long timeout = msecs_to_jiffies_timeout(1);
	int scanline, min, max, vblank_start;
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	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
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	bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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		intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
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	DEFINE_WAIT(wait);
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	u32 psr_status;
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	vblank_start = adjusted_mode->crtc_vblank_start;
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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		vblank_start = DIV_ROUND_UP(vblank_start, 2);

	/* FIXME needs to be calibrated sensibly */
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	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
						      VBLANK_EVASION_TIME_US);
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	max = vblank_start - 1;

	if (min <= 0 || max <= 0)
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		goto irq_disable;
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	if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
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		goto irq_disable;

	/*
	 * Wait for psr to idle out after enabling the VBL interrupts
	 * VBL interrupts will start the PSR exit and prevent a PSR
	 * re-entry as well.
	 */
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	if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
		DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
			  psr_status);
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	local_irq_disable();
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	crtc->debug.min_vbl = min;
	crtc->debug.max_vbl = max;
	trace_i915_pipe_update_start(crtc);
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	for (;;) {
		/*
		 * prepare_to_wait() has a memory barrier, which guarantees
		 * other CPUs can see the task state update by the time we
		 * read the scanline.
		 */
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		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
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		scanline = intel_get_crtc_scanline(crtc);
		if (scanline < min || scanline > max)
			break;

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		if (!timeout) {
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			DRM_ERROR("Potential atomic update failure on pipe %c\n",
				  pipe_name(crtc->pipe));
			break;
		}

		local_irq_enable();

		timeout = schedule_timeout(timeout);

		local_irq_disable();
	}

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	finish_wait(wq, &wait);
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	drm_crtc_vblank_put(&crtc->base);
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	/*
	 * On VLV/CHV DSI the scanline counter would appear to
	 * increment approx. 1/3 of a scanline before start of vblank.
	 * The registers still get latched at start of vblank however.
	 * This means we must not write any registers on the first
	 * line of vblank (since not the whole line is actually in
	 * vblank). And unfortunately we can't use the interrupt to
	 * wait here since it will fire too soon. We could use the
	 * frame start interrupt instead since it will fire after the
	 * critical scanline, but that would require more changes
	 * in the interrupt code. So for now we'll just do the nasty
	 * thing and poll for the bad scanline to pass us by.
	 *
	 * FIXME figure out if BXT+ DSI suffers from this as well
	 */
	while (need_vlv_dsi_wa && scanline == vblank_start)
		scanline = intel_get_crtc_scanline(crtc);

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	crtc->debug.scanline_start = scanline;
	crtc->debug.start_vbl_time = ktime_get();
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	crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
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	trace_i915_pipe_update_vblank_evaded(crtc);
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	return;

irq_disable:
	local_irq_disable();
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}

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/**
 * intel_pipe_update_end() - end update of a set of display registers
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 * @new_crtc_state: the new crtc state
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 *
 * Mark the end of an update started with intel_pipe_update_start(). This
 * re-enables interrupts and verifies the update was actually completed
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 * before a vblank.
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 */
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void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
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	enum pipe pipe = crtc->pipe;
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	int scanline_end = intel_get_crtc_scanline(crtc);
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	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
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	ktime_t end_vbl_time = ktime_get();
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	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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	trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
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	/* We're still in the vblank-evade critical section, this can't race.
	 * Would be slightly nice to just grab the vblank count and arm the
	 * event outside of the critical section - the spinlock might spin for a
	 * while ... */
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	if (new_crtc_state->base.event) {
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		WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);

		spin_lock(&crtc->base.dev->event_lock);
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		drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
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		spin_unlock(&crtc->base.dev->event_lock);

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		new_crtc_state->base.event = NULL;
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	}

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	local_irq_enable();

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	if (intel_vgpu_active(dev_priv))
		return;

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	if (crtc->debug.start_vbl_count &&
	    crtc->debug.start_vbl_count != end_vbl_count) {
		DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
			  pipe_name(pipe), crtc->debug.start_vbl_count,
			  end_vbl_count,
			  ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
			  crtc->debug.min_vbl, crtc->debug.max_vbl,
			  crtc->debug.scanline_start, scanline_end);
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	}
#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
	else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
		 VBLANK_EVASION_TIME_US)
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		DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
			 pipe_name(pipe),
			 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
			 VBLANK_EVASION_TIME_US);
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#endif
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}

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int intel_plane_check_stride(const struct intel_plane_state *plane_state)
{
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	const struct drm_framebuffer *fb = plane_state->base.fb;
	unsigned int rotation = plane_state->base.rotation;
	u32 stride, max_stride;

	/* FIXME other color planes? */
	stride = plane_state->color_plane[0].stride;
	max_stride = plane->max_stride(plane, fb->format->format,
				       fb->modifier, rotation);

	if (stride > max_stride) {
		DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
			      fb->base.id, stride,
			      plane->base.base.id, plane->base.name, max_stride);
		return -EINVAL;
	}

	return 0;
}

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int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
{
	const struct drm_framebuffer *fb = plane_state->base.fb;
	struct drm_rect *src = &plane_state->base.src;
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	u32 src_x, src_y, src_w, src_h, hsub, vsub;
	bool rotated = drm_rotation_90_or_270(plane_state->base.rotation);
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	/*
	 * Hardware doesn't handle subpixel coordinates.
	 * Adjust to (macro)pixel boundary, but be careful not to
	 * increase the source viewport size, because that could
	 * push the downscaling factor out of bounds.
	 */
	src_x = src->x1 >> 16;
	src_w = drm_rect_width(src) >> 16;
	src_y = src->y1 >> 16;
	src_h = drm_rect_height(src) >> 16;

	src->x1 = src_x << 16;
	src->x2 = (src_x + src_w) << 16;
	src->y1 = src_y << 16;
	src->y2 = (src_y + src_h) << 16;

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	if (!fb->format->is_yuv)
		return 0;

	/* YUV specific checks */
	if (!rotated) {
		hsub = fb->format->hsub;
		vsub = fb->format->vsub;
	} else {
		hsub = vsub = max(fb->format->hsub, fb->format->vsub);
	}

	if (src_x % hsub || src_w % hsub) {
		DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for %sYUV planes\n",
			      src_x, src_w, hsub, rotated ? "rotated " : "");
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		return -EINVAL;
	}

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	if (src_y % vsub || src_h % vsub) {
		DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for %sYUV planes\n",
			      src_y, src_h, vsub, rotated ? "rotated " : "");
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		return -EINVAL;
	}

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	return 0;
}

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static unsigned int
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skl_plane_max_stride(struct intel_plane *plane,
		     u32 pixel_format, u64 modifier,
		     unsigned int rotation)
{
	int cpp = drm_format_plane_cpp(pixel_format, 0);

	/*
	 * "The stride in bytes must not exceed the
	 * of the size of 8K pixels and 32K bytes."
	 */
	if (drm_rotation_90_or_270(rotation))
		return min(8192, 32768 / cpp);
	else
		return min(8192 * cpp, 32768);
}

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static void
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skl_program_scaler(struct intel_plane *plane,
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		   const struct intel_crtc_state *crtc_state,
		   const struct intel_plane_state *plane_state)
{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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	enum pipe pipe = plane->pipe;
	int scaler_id = plane_state->scaler_id;
	const struct intel_scaler *scaler =
		&crtc_state->scaler_state.scalers[scaler_id];
	int crtc_x = plane_state->base.dst.x1;
	int crtc_y = plane_state->base.dst.y1;
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	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
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	u16 y_hphase, uv_rgb_hphase;
	u16 y_vphase, uv_rgb_vphase;
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	int hscale, vscale;

	hscale = drm_rect_calc_hscale(&plane_state->base.src,
				      &plane_state->base.dst,
				      0, INT_MAX);
	vscale = drm_rect_calc_vscale(&plane_state->base.src,
				      &plane_state->base.dst,
				      0, INT_MAX);
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	/* TODO: handle sub-pixel coordinates */
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	if (is_planar_yuv_format(plane_state->base.fb->format->format) &&
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	    !icl_is_hdr_plane(dev_priv, plane->id)) {
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		y_hphase = skl_scaler_calc_phase(1, hscale, false);
		y_vphase = skl_scaler_calc_phase(1, vscale, false);
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		/* MPEG2 chroma siting convention */
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		uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
		uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
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	} else {
		/* not used */
		y_hphase = 0;
		y_vphase = 0;

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		uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
		uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
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	}

	I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
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		      PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
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	I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
		      PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
	I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
		      PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
	I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
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	I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
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}

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/* Preoffset values for YUV to RGB Conversion */
#define PREOFF_YUV_TO_RGB_HI		0x1800
#define PREOFF_YUV_TO_RGB_ME		0x1F00
#define PREOFF_YUV_TO_RGB_LO		0x1800

#define  ROFF(x)          (((x) & 0xffff) << 16)
#define  GOFF(x)          (((x) & 0xffff) << 0)
#define  BOFF(x)          (((x) & 0xffff) << 16)

static void
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icl_program_input_csc(struct intel_plane *plane,
		      const struct intel_crtc_state *crtc_state,
		      const struct intel_plane_state *plane_state)
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{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
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	enum plane_id plane_id = plane->id;

	static const u16 input_csc_matrix[][9] = {
		/*
		 * BT.601 full range YCbCr -> full range RGB
		 * The matrix required is :
		 * [1.000, 0.000, 1.371,
		 *  1.000, -0.336, -0.698,
		 *  1.000, 1.732, 0.0000]
		 */
		[DRM_COLOR_YCBCR_BT601] = {
			0x7AF8, 0x7800, 0x0,
			0x8B28, 0x7800, 0x9AC0,
			0x0, 0x7800, 0x7DD8,
		},
		/*
		 * BT.709 full range YCbCr -> full range RGB
		 * The matrix required is :
		 * [1.000, 0.000, 1.574,
		 *  1.000, -0.187, -0.468,
		 *  1.000, 1.855, 0.0000]
		 */
		[DRM_COLOR_YCBCR_BT709] = {
			0x7C98, 0x7800, 0x0,
			0x9EF8, 0x7800, 0xABF8,
			0x0, 0x7800,  0x7ED8,
		},
	};

	/* Matrix for Limited Range to Full Range Conversion */
	static const u16 input_csc_matrix_lr[][9] = {
		/*
		 * BT.601 Limted range YCbCr -> full range RGB
		 * The matrix required is :
		 * [1.164384, 0.000, 1.596370,
		 *  1.138393, -0.382500, -0.794598,
		 *  1.138393, 1.971696, 0.0000]
		 */
		[DRM_COLOR_YCBCR_BT601] = {
			0x7CC8, 0x7950, 0x0,
			0x8CB8, 0x7918, 0x9C40,
			0x0, 0x7918, 0x7FC8,
		},
		/*
		 * BT.709 Limited range YCbCr -> full range RGB
		 * The matrix required is :
		 * [1.164, 0.000, 1.833671,
		 *  1.138393, -0.213249, -0.532909,
		 *  1.138393, 2.112402, 0.0000]
		 */
		[DRM_COLOR_YCBCR_BT709] = {
			0x7EA8, 0x7950, 0x0,
			0x8888, 0x7918, 0xADA8,
			0x0, 0x7918,  0x6870,
		},
	};
	const u16 *csc;

	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
		csc = input_csc_matrix[plane_state->base.color_encoding];
	else
		csc = input_csc_matrix_lr[plane_state->base.color_encoding];

	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
		      GOFF(csc[1]));
	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));
	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |
		      GOFF(csc[4]));
	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));
	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |
		      GOFF(csc[7]));
	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));

	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
		      PREOFF_YUV_TO_RGB_HI);
	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
		      PREOFF_YUV_TO_RGB_ME);
	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
		      PREOFF_YUV_TO_RGB_LO);
	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}

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static void
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skl_program_plane(struct intel_plane *plane,
		  const struct intel_crtc_state *crtc_state,
		  const struct intel_plane_state *plane_state,
		  int color_plane, bool slave, u32 plane_ctl)
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{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum plane_id plane_id = plane->id;
	enum pipe pipe = plane->pipe;
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	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
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	u32 surf_addr = plane_state->color_plane[color_plane].offset;
	u32 stride = skl_plane_stride(plane_state, color_plane);
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	u32 aux_stride = skl_plane_stride(plane_state, 1);
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	int crtc_x = plane_state->base.dst.x1;
	int crtc_y = plane_state->base.dst.y1;
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	u32 x = plane_state->color_plane[color_plane].x;
	u32 y = plane_state->color_plane[color_plane].y;
	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
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	struct intel_plane *linked = plane_state->linked_plane;
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	const struct drm_framebuffer *fb = plane_state->base.fb;
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	u8 alpha = plane_state->base.alpha >> 8;
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	u32 plane_color_ctl = 0;
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	unsigned long irqflags;
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	u32 keymsk, keymax;
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	plane_ctl |= skl_plane_ctl_crtc(crtc_state);

	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
		plane_color_ctl = plane_state->color_ctl |
			glk_plane_color_ctl_crtc(crtc_state);

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	/* Sizes are 0 based */
	src_w--;
	src_h--;

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	keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);

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	keymsk = key->channel_mask & 0x7ffffff;
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	if (alpha < 0xff)
		keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;

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	/* The scaler will handle the output position */
	if (plane_state->scaler_id >= 0) {
		crtc_x = 0;
		crtc_y = 0;
	}

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	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
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	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
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	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
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	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
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		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
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	if (icl_is_hdr_plane(dev_priv, plane_id)) {
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		u32 cus_ctl = 0;

		if (linked) {
			/* Enable and use MPEG-2 chroma siting */
			cus_ctl = PLANE_CUS_ENABLE |
				PLANE_CUS_HPHASE_0 |
				PLANE_CUS_VPHASE_SIGN_NEGATIVE |
				PLANE_CUS_VPHASE_0_25;

			if (linked->id == PLANE_SPRITE5)
				cus_ctl |= PLANE_CUS_PLANE_7;
			else if (linked->id == PLANE_SPRITE4)
				cus_ctl |= PLANE_CUS_PLANE_6;
			else
				MISSING_CASE(linked->id);
		}

		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
	}

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	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
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	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
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		icl_program_input_csc(plane, crtc_state, plane_state);
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	skl_write_plane_wm(plane, crtc_state);

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	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);

	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);

	if (INTEL_GEN(dev_priv) < 11)
		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
			      (plane_state->color_plane[1].y << 16) |
			      plane_state->color_plane[1].x);
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	/*
	 * The control register self-arms if the plane was previously
	 * disabled. Try to make the plane enable atomic by writing
	 * the control register just before the surface register.
	 */
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	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
		      intel_plane_ggtt_offset(plane_state) + surf_addr);

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	if (!slave && plane_state->scaler_id >= 0)
		skl_program_scaler(plane, crtc_state, plane_state);

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	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}

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static void
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skl_update_plane(struct intel_plane *plane,
		 const struct intel_crtc_state *crtc_state,
		 const struct intel_plane_state *plane_state)
{
	int color_plane = 0;

	if (plane_state->linked_plane) {
		/* Program the UV plane */
		color_plane = 1;
	}

	skl_program_plane(plane, crtc_state, plane_state,
			  color_plane, false, plane_state->ctl);
}

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static void
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icl_update_slave(struct intel_plane *plane,
		 const struct intel_crtc_state *crtc_state,
		 const struct intel_plane_state *plane_state)
{
	skl_program_plane(plane, crtc_state, plane_state, 0, true,
			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
}

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static void
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skl_disable_plane(struct intel_plane *plane,
		  const struct intel_crtc_state *crtc_state)
626
{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum plane_id plane_id = plane->id;
	enum pipe pipe = plane->pipe;
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	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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	if (icl_is_hdr_plane(dev_priv, plane_id))
		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0);

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	skl_write_plane_wm(plane, crtc_state);

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	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}

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static bool
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skl_plane_get_hw_state(struct intel_plane *plane,
		       enum pipe *pipe)
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{
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum intel_display_power_domain power_domain;
	enum plane_id plane_id = plane->id;
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	intel_wakeref_t wakeref;
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	bool ret;

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	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
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	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (!wakeref)
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		return false;

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	ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

	*pipe = plane->pipe;
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	intel_display_power_put(dev_priv, power_domain, wakeref);
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	return ret;
}

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static void
670
chv_update_csc(const struct intel_plane_state *plane_state)
671
{
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	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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	const struct drm_framebuffer *fb = plane_state->base.fb;
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	enum plane_id plane_id = plane->id;
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	/*
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	 * |r|   | c0 c1 c2 |   |cr|
	 * |g| = | c3 c4 c5 | x |y |
	 * |b|   | c6 c7 c8 |   |cb|
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	 *
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	 * Coefficients are s3.12.
682
	 *
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	 * Cb and Cr apparently come in as signed already, and
	 * we always get full range data in on account of CLRC0/1.
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	 */
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	static const s16 csc_matrix[][9] = {
		/* BT.601 full range YCbCr -> full range RGB */
		[DRM_COLOR_YCBCR_BT601] = {
			 5743, 4096,     0,
			-2925, 4096, -1410,
			    0, 4096,  7258,
		},
		/* BT.709 full range YCbCr -> full range RGB */
		[DRM_COLOR_YCBCR_BT709] = {
			 6450, 4096,     0,
			-1917, 4096,  -767,
			    0, 4096,  7601,
		},
	};
	const s16 *csc = csc_matrix[plane_state->base.color_encoding];
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	/* Seems RGB data bypasses the CSC always */
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	if (!fb->format->is_yuv)
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		return;

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	I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
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	I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
	I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));

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	I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
	I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
	I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
	I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
	I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
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	I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
	I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
	I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
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	I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
	I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
	I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
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}

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#define SIN_0 0
#define COS_0 1

static void
vlv_update_clrc(const struct intel_plane_state *plane_state)
{
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	const struct drm_framebuffer *fb = plane_state->base.fb;
	enum pipe pipe = plane->pipe;
	enum plane_id plane_id = plane->id;
	int contrast, brightness, sh_scale, sh_sin, sh_cos;

738
	if (fb->format->is_yuv &&
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	    plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
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		/*
		 * Expand limited range to full range:
		 * Contrast is applied first and is used to expand Y range.
		 * Brightness is applied second and is used to remove the
		 * offset from Y. Saturation/hue is used to expand CbCr range.
		 */
		contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
		brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
		sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
		sh_sin = SIN_0 * sh_scale;
		sh_cos = COS_0 * sh_scale;
	} else {
		/* Pass-through everything. */
		contrast = 1 << 6;
		brightness = 0;
		sh_scale = 1 << 7;
		sh_sin = SIN_0 * sh_scale;
		sh_cos = COS_0 * sh_scale;
	}

	/* FIXME these register are single buffered :( */
	I915_WRITE_FW(SPCLRC0(pipe, plane_id),
		      SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
	I915_WRITE_FW(SPCLRC1(pipe, plane_id),
		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
}

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static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
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	u32 sprctl = 0;

	if (crtc_state->gamma_enable)
		sprctl |= SP_GAMMA_ENABLE;

	return sprctl;
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}

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static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
			  const struct intel_plane_state *plane_state)
779
{
780
	const struct drm_framebuffer *fb = plane_state->base.fb;
781
	unsigned int rotation = plane_state->base.rotation;
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	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
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	u32 sprctl;
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785
	sprctl = SP_ENABLE;
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787
	switch (fb->format->format) {
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	case DRM_FORMAT_YUYV:
		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
		break;
	case DRM_FORMAT_YVYU:
		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
		break;
	case DRM_FORMAT_UYVY:
		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
		break;
	case DRM_FORMAT_VYUY:
		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
		break;
	case DRM_FORMAT_RGB565:
		sprctl |= SP_FORMAT_BGR565;
		break;
	case DRM_FORMAT_XRGB8888:
		sprctl |= SP_FORMAT_BGRX8888;
		break;
	case DRM_FORMAT_ARGB8888:
		sprctl |= SP_FORMAT_BGRA8888;
		break;
	case DRM_FORMAT_XBGR2101010:
		sprctl |= SP_FORMAT_RGBX1010102;
		break;
	case DRM_FORMAT_ABGR2101010:
		sprctl |= SP_FORMAT_RGBA1010102;
		break;
	case DRM_FORMAT_XBGR8888:
		sprctl |= SP_FORMAT_RGBX8888;
		break;
	case DRM_FORMAT_ABGR8888:
		sprctl |= SP_FORMAT_RGBA8888;
		break;
	default:
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		MISSING_CASE(fb->format->format);
		return 0;
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	}

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	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
		sprctl |= SP_YUV_FORMAT_BT709;

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	if (fb->modifier == I915_FORMAT_MOD_X_TILED)
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		sprctl |= SP_TILED;

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	if (rotation & DRM_MODE_ROTATE_180)
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		sprctl |= SP_ROTATE_180;

835
	if (rotation & DRM_MODE_REFLECT_X)
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		sprctl |= SP_MIRROR;

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	if (key->flags & I915_SET_COLORKEY_SOURCE)
		sprctl |= SP_SOURCE_KEY;

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	return sprctl;
}

static void
845
vlv_update_plane(struct intel_plane *plane,
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		 const struct intel_crtc_state *crtc_state,
		 const struct intel_plane_state *plane_state)
{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
	enum plane_id plane_id = plane->id;
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	u32 sprsurf_offset = plane_state->color_plane[0].offset;
853
	u32 linear_offset;
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	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
	int crtc_x = plane_state->base.dst.x1;
	int crtc_y = plane_state->base.dst.y1;
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	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
	u32 x = plane_state->color_plane[0].x;
	u32 y = plane_state->color_plane[0].y;
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	unsigned long irqflags;
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	u32 sprctl;

	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
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	/* Sizes are 0 based */
	crtc_w--;
	crtc_h--;

870
	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
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	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

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	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
		      plane_state->color_plane[0].stride);
	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);

880
	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
881
		chv_update_csc(plane_state);
882

883
	if (key->flags) {
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		I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
		I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
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		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
887
	}
888

889
	I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
890
	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
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	/*
	 * The control register self-arms if the plane was previously
	 * disabled. Try to make the plane enable atomic by writing
	 * the control register just before the surface register.
	 */
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	I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
	I915_WRITE_FW(SPSURF(pipe, plane_id),
		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);

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	vlv_update_clrc(plane_state);

903
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}

static void
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vlv_disable_plane(struct intel_plane *plane,
		  const struct intel_crtc_state *crtc_state)
909
{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
	enum plane_id plane_id = plane->id;
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	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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	I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
	I915_WRITE_FW(SPSURF(pipe, plane_id), 0);

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}

923
static bool
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vlv_plane_get_hw_state(struct intel_plane *plane,
		       enum pipe *pipe)
926 927 928 929
{
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum intel_display_power_domain power_domain;
	enum plane_id plane_id = plane->id;
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	intel_wakeref_t wakeref;
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	bool ret;

933
	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
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	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (!wakeref)
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		return false;

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	ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

	*pipe = plane->pipe;
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	intel_display_power_put(dev_priv, power_domain, wakeref);
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	return ret;
}

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static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
	u32 sprctl = 0;

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	if (crtc_state->gamma_enable)
		sprctl |= SPRITE_GAMMA_ENABLE;
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954
	if (crtc_state->csc_enable)
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		sprctl |= SPRITE_PIPE_CSC_ENABLE;

	return sprctl;
}

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static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
			  const struct intel_plane_state *plane_state)
962
{
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	struct drm_i915_private *dev_priv =
		to_i915(plane_state->base.plane->dev);
	const struct drm_framebuffer *fb = plane_state->base.fb;
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	unsigned int rotation = plane_state->base.rotation;
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	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
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	u32 sprctl;

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	sprctl = SPRITE_ENABLE;
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	if (IS_IVYBRIDGE(dev_priv))
		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;

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	switch (fb->format->format) {
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	case DRM_FORMAT_XBGR8888:
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		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
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		break;
	case DRM_FORMAT_XRGB8888:
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		sprctl |= SPRITE_FORMAT_RGBX888;
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		break;
	case DRM_FORMAT_YUYV:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
		break;
	case DRM_FORMAT_YVYU:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
		break;
	case DRM_FORMAT_UYVY:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
		break;
	case DRM_FORMAT_VYUY:
		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
		break;
	default:
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		MISSING_CASE(fb->format->format);
		return 0;
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	}

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	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
		sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;

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	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
		sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;

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1005
	if (fb->modifier == I915_FORMAT_MOD_X_TILED)
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		sprctl |= SPRITE_TILED;

1008
	if (rotation & DRM_MODE_ROTATE_180)
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		sprctl |= SPRITE_ROTATE_180;

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	if (key->flags & I915_SET_COLORKEY_DESTINATION)
		sprctl |= SPRITE_DEST_KEY;
	else if (key->flags & I915_SET_COLORKEY_SOURCE)
		sprctl |= SPRITE_SOURCE_KEY;

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	return sprctl;
}

static void
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ivb_update_plane(struct intel_plane *plane,
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		 const struct intel_crtc_state *crtc_state,
		 const struct intel_plane_state *plane_state)
{
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	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
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	u32 sprsurf_offset = plane_state->color_plane[0].offset;
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	u32 linear_offset;
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	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
	int crtc_x = plane_state->base.dst.x1;
	int crtc_y = plane_state->base.dst.y1;
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	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
	u32 x = plane_state->color_plane[0].x;
	u32 y = plane_state->color_plane[0].y;
	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
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	u32 sprctl, sprscale = 0;
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	unsigned long irqflags;

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	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);

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	/* Sizes are 0 based */
	src_w--;
	src_h--;
	crtc_w--;
	crtc_h--;

1048
	if (crtc_w != src_w || crtc_h != src_h)
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		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;

1051
	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1052

1053 1054
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

1055 1056 1057 1058 1059 1060
	I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
	I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
	I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
	if (IS_IVYBRIDGE(dev_priv))
		I915_WRITE_FW(SPRSCALE(pipe), sprscale);

1061
	if (key->flags) {
1062 1063
		I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
		I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
1064
		I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
1065 1066
	}

1067 1068
	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
	 * register */
1069
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1070
		I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
1071
	} else {
1072
		I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
1073
		I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
1074
	}
1075

1076 1077 1078 1079 1080
	/*
	 * The control register self-arms if the plane was previously
	 * disabled. Try to make the plane enable atomic by writing
	 * the control register just before the surface register.
	 */
1081 1082 1083 1084 1085
	I915_WRITE_FW(SPRCTL(pipe), sprctl);
	I915_WRITE_FW(SPRSURF(pipe),
		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1086 1087 1088
}

static void
1089 1090
ivb_disable_plane(struct intel_plane *plane,
		  const struct intel_crtc_state *crtc_state)
1091
{
1092 1093
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
1094 1095 1096
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1097

1098
	I915_WRITE_FW(SPRCTL(pipe), 0);
1099
	/* Disable the scaler */
1100
	if (IS_IVYBRIDGE(dev_priv))
1101 1102 1103 1104
		I915_WRITE_FW(SPRSCALE(pipe), 0);
	I915_WRITE_FW(SPRSURF(pipe), 0);

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1105 1106
}

1107
static bool
1108 1109
ivb_plane_get_hw_state(struct intel_plane *plane,
		       enum pipe *pipe)
1110 1111 1112
{
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum intel_display_power_domain power_domain;
1113
	intel_wakeref_t wakeref;
1114 1115
	bool ret;

1116
	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1117 1118
	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (!wakeref)
1119 1120
		return false;

1121 1122 1123
	ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;

	*pipe = plane->pipe;
1124

1125
	intel_display_power_put(dev_priv, power_domain, wakeref);
1126 1127 1128 1129

	return ret;
}

1130 1131 1132 1133 1134 1135 1136 1137
static unsigned int
g4x_sprite_max_stride(struct intel_plane *plane,
		      u32 pixel_format, u64 modifier,
		      unsigned int rotation)
{
	return 16384;
}

1138 1139
static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
1140 1141 1142 1143 1144
	u32 dvscntr = 0;

	if (crtc_state->gamma_enable)
		dvscntr |= DVS_GAMMA_ENABLE;

1145 1146 1147
	if (crtc_state->csc_enable)
		dvscntr |= DVS_PIPE_CSC_ENABLE;

1148
	return dvscntr;
1149 1150
}

1151
static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1152
			  const struct intel_plane_state *plane_state)
1153
{
1154 1155 1156
	struct drm_i915_private *dev_priv =
		to_i915(plane_state->base.plane->dev);
	const struct drm_framebuffer *fb = plane_state->base.fb;
1157
	unsigned int rotation = plane_state->base.rotation;
1158
	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1159 1160
	u32 dvscntr;

1161
	dvscntr = DVS_ENABLE;
1162

1163
	if (IS_GEN(dev_priv, 6))
1164
		dvscntr |= DVS_TRICKLE_FEED_DISABLE;
1165

1166
	switch (fb->format->format) {
1167
	case DRM_FORMAT_XBGR8888:
1168
		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
1169 1170
		break;
	case DRM_FORMAT_XRGB8888:
1171
		dvscntr |= DVS_FORMAT_RGBX888;
1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185
		break;
	case DRM_FORMAT_YUYV:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
		break;
	case DRM_FORMAT_YVYU:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
		break;
	case DRM_FORMAT_UYVY:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
		break;
	case DRM_FORMAT_VYUY:
		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
		break;
	default:
1186 1187
		MISSING_CASE(fb->format->format);
		return 0;
1188 1189
	}

1190 1191 1192
	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
		dvscntr |= DVS_YUV_FORMAT_BT709;

1193 1194 1195
	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
		dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;

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Ville Syrjälä committed
1196
	if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1197 1198
		dvscntr |= DVS_TILED;

1199
	if (rotation & DRM_MODE_ROTATE_180)
1200 1201
		dvscntr |= DVS_ROTATE_180;

1202 1203 1204 1205 1206
	if (key->flags & I915_SET_COLORKEY_DESTINATION)
		dvscntr |= DVS_DEST_KEY;
	else if (key->flags & I915_SET_COLORKEY_SOURCE)
		dvscntr |= DVS_SOURCE_KEY;

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	return dvscntr;
}

static void
1211
g4x_update_plane(struct intel_plane *plane,
1212 1213 1214
		 const struct intel_crtc_state *crtc_state,
		 const struct intel_plane_state *plane_state)
{
1215 1216
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
1217
	u32 dvssurf_offset = plane_state->color_plane[0].offset;
1218
	u32 linear_offset;
1219 1220 1221
	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
	int crtc_x = plane_state->base.dst.x1;
	int crtc_y = plane_state->base.dst.y1;
1222 1223 1224 1225 1226 1227
	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
	u32 x = plane_state->color_plane[0].x;
	u32 y = plane_state->color_plane[0].y;
	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
1228
	u32 dvscntr, dvsscale = 0;
1229 1230
	unsigned long irqflags;

1231 1232
	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);

1233 1234 1235 1236 1237 1238
	/* Sizes are 0 based */
	src_w--;
	src_h--;
	crtc_w--;
	crtc_h--;

1239
	if (crtc_w != src_w || crtc_h != src_h)
1240 1241
		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;

1242
	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1243

1244 1245
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

1246 1247 1248 1249 1250
	I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
	I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
	I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
	I915_WRITE_FW(DVSSCALE(pipe), dvsscale);

1251
	if (key->flags) {
1252 1253
		I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
		I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
1254
		I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
1255 1256
	}

1257
	I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1258
	I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1259

1260 1261 1262 1263 1264
	/*
	 * The control register self-arms if the plane was previously
	 * disabled. Try to make the plane enable atomic by writing
	 * the control register just before the surface register.
	 */
1265 1266 1267 1268 1269
	I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
	I915_WRITE_FW(DVSSURF(pipe),
		      intel_plane_ggtt_offset(plane_state) + dvssurf_offset);

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1270 1271 1272
}

static void
1273 1274
g4x_disable_plane(struct intel_plane *plane,
		  const struct intel_crtc_state *crtc_state)
1275
{
1276 1277
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum pipe pipe = plane->pipe;
1278
	unsigned long irqflags;
1279

1280 1281 1282
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

	I915_WRITE_FW(DVSCNTR(pipe), 0);
1283
	/* Disable the scaler */
1284 1285
	I915_WRITE_FW(DVSSCALE(pipe), 0);
	I915_WRITE_FW(DVSSURF(pipe), 0);
1286

1287
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1288 1289
}

1290
static bool
1291 1292
g4x_plane_get_hw_state(struct intel_plane *plane,
		       enum pipe *pipe)
1293 1294 1295
{
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	enum intel_display_power_domain power_domain;
1296
	intel_wakeref_t wakeref;
1297 1298
	bool ret;

1299
	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1300 1301
	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (!wakeref)
1302 1303
		return false;

1304 1305 1306
	ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;

	*pipe = plane->pipe;
1307

1308
	intel_display_power_put(dev_priv, power_domain, wakeref);
1309 1310 1311 1312

	return ret;
}

1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
static bool intel_fb_scalable(const struct drm_framebuffer *fb)
{
	if (!fb)
		return false;

	switch (fb->format->format) {
	case DRM_FORMAT_C8:
		return false;
	default:
		return true;
	}
}

1326
static int
1327 1328
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
			 struct intel_plane_state *plane_state)
1329
{
1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348
	const struct drm_framebuffer *fb = plane_state->base.fb;
	const struct drm_rect *src = &plane_state->base.src;
	const struct drm_rect *dst = &plane_state->base.dst;
	int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
	const struct drm_display_mode *adjusted_mode =
		&crtc_state->base.adjusted_mode;
	unsigned int cpp = fb->format->cpp[0];
	unsigned int width_bytes;
	int min_width, min_height;

	crtc_w = drm_rect_width(dst);
	crtc_h = drm_rect_height(dst);

	src_x = src->x1 >> 16;
	src_y = src->y1 >> 16;
	src_w = drm_rect_width(src) >> 16;
	src_h = drm_rect_height(src) >> 16;

	if (src_w == crtc_w && src_h == crtc_h)
1349
		return 0;
1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360

	min_width = 3;

	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (src_h & 1) {
			DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
			return -EINVAL;
		}
		min_height = 6;
	} else {
		min_height = 3;
1361
	}
1362

1363 1364 1365 1366 1367 1368
	width_bytes = ((src_x * cpp) & 63) + src_w * cpp;

	if (src_w < min_width || src_h < min_height ||
	    src_w > 2048 || src_h > 2048) {
		DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
			      src_w, src_h, min_width, min_height, 2048, 2048);
1369
		return -EINVAL;
1370
	}
1371

1372 1373 1374
	if (width_bytes > 4096) {
		DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
			      width_bytes, 4096);
1375
		return -EINVAL;
1376
	}
1377

1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
	if (width_bytes > 4096 || fb->pitches[0] > 4096) {
		DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
			      fb->pitches[0], 4096);
		return -EINVAL;
	}

	return 0;
}

static int
g4x_sprite_check(struct intel_crtc_state *crtc_state,
		 struct intel_plane_state *plane_state)
{
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1393 1394
	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1395 1396
	int ret;

1397 1398 1399 1400 1401 1402 1403 1404
	if (intel_fb_scalable(plane_state->base.fb)) {
		if (INTEL_GEN(dev_priv) < 7) {
			min_scale = 1;
			max_scale = 16 << 16;
		} else if (IS_IVYBRIDGE(dev_priv)) {
			min_scale = 1;
			max_scale = 2 << 16;
		}
1405 1406
	}

1407
	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1408 1409 1410 1411 1412
						  &crtc_state->base,
						  min_scale, max_scale,
						  true, true);
	if (ret)
		return ret;
1413

1414 1415
	if (!plane_state->base.visible)
		return 0;
1416

1417 1418 1419
	ret = intel_plane_check_src_coordinates(plane_state);
	if (ret)
		return ret;
1420

1421 1422 1423
	ret = g4x_sprite_check_scaling(crtc_state, plane_state);
	if (ret)
		return ret;
1424

1425 1426 1427
	ret = i9xx_check_plane_surface(plane_state);
	if (ret)
		return ret;
1428

1429 1430 1431 1432
	if (INTEL_GEN(dev_priv) >= 7)
		plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
	else
		plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1433

1434 1435
	return 0;
}
1436

1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
{
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	unsigned int rotation = plane_state->base.rotation;

	/* CHV ignores the mirror bit when the rotate bit is set :( */
	if (IS_CHERRYVIEW(dev_priv) &&
	    rotation & DRM_MODE_ROTATE_180 &&
	    rotation & DRM_MODE_REFLECT_X) {
		DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
		return -EINVAL;
	}

	return 0;
}

1454 1455 1456 1457 1458 1459
static int
vlv_sprite_check(struct intel_crtc_state *crtc_state,
		 struct intel_plane_state *plane_state)
{
	int ret;

1460 1461 1462 1463
	ret = chv_plane_check_rotation(plane_state);
	if (ret)
		return ret;

1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
						  &crtc_state->base,
						  DRM_PLANE_HELPER_NO_SCALING,
						  DRM_PLANE_HELPER_NO_SCALING,
						  true, true);
	if (ret)
		return ret;

	if (!plane_state->base.visible)
		return 0;

	ret = intel_plane_check_src_coordinates(plane_state);
	if (ret)
		return ret;

	ret = i9xx_check_plane_surface(plane_state);
	if (ret)
		return ret;

	plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1484

1485 1486 1487
	return 0;
}

1488 1489 1490
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
			      const struct intel_plane_state *plane_state)
{
1491 1492
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1493 1494 1495 1496 1497 1498 1499 1500
	const struct drm_framebuffer *fb = plane_state->base.fb;
	unsigned int rotation = plane_state->base.rotation;
	struct drm_format_name_buf format_name;

	if (!fb)
		return 0;

	if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1501
	    is_ccs_modifier(fb->modifier)) {
1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520
		DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
			      rotation);
		return -EINVAL;
	}

	if (rotation & DRM_MODE_REFLECT_X &&
	    fb->modifier == DRM_FORMAT_MOD_LINEAR) {
		DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
		return -EINVAL;
	}

	if (drm_rotation_90_or_270(rotation)) {
		if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
		    fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
			DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
			return -EINVAL;
		}

		/*
1521 1522
		 * 90/270 is not allowed with RGB64 16:16:16:16 and
		 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1523 1524 1525
		 */
		switch (fb->format->format) {
		case DRM_FORMAT_RGB565:
1526 1527 1528 1529
			if (INTEL_GEN(dev_priv) >= 11)
				break;
			/* fall through */
		case DRM_FORMAT_C8:
1530 1531 1532 1533
		case DRM_FORMAT_XRGB16161616F:
		case DRM_FORMAT_XBGR16161616F:
		case DRM_FORMAT_ARGB16161616F:
		case DRM_FORMAT_ABGR16161616F:
1534 1535 1536 1537 1538
		case DRM_FORMAT_Y210:
		case DRM_FORMAT_Y212:
		case DRM_FORMAT_Y216:
		case DRM_FORMAT_XVYU12_16161616:
		case DRM_FORMAT_XVYU16161616:
1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
				      drm_get_format_name(fb->format->format,
							  &format_name));
			return -EINVAL;
		default:
			break;
		}
	}

	/* Y-tiling is not supported in IF-ID Interlace mode */
	if (crtc_state->base.enable &&
	    crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
		return -EINVAL;
	}

	return 0;
}

1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591
static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
					   const struct intel_plane_state *plane_state)
{
	struct drm_i915_private *dev_priv =
		to_i915(plane_state->base.plane->dev);
	int crtc_x = plane_state->base.dst.x1;
	int crtc_w = drm_rect_width(&plane_state->base.dst);
	int pipe_src_w = crtc_state->pipe_src_w;

	/*
	 * Display WA #1175: cnl,glk
	 * Planes other than the cursor may cause FIFO underflow and display
	 * corruption if starting less than 4 pixels from the right edge of
	 * the screen.
	 * Besides the above WA fix the similar problem, where planes other
	 * than the cursor ending less than 4 pixels from the left edge of the
	 * screen may cause FIFO underflow and display corruption.
	 */
	if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
	    (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
		DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
			      crtc_x + crtc_w < 4 ? "end" : "start",
			      crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
			      4, pipe_src_w - 4);
		return -ERANGE;
	}

	return 0;
}

1592 1593 1594 1595 1596 1597 1598
static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
{
	const struct drm_framebuffer *fb = plane_state->base.fb;
	unsigned int rotation = plane_state->base.rotation;
	int src_w = drm_rect_width(&plane_state->base.src) >> 16;

	/* Display WA #1106 */
1599
	if (is_planar_yuv_format(fb->format->format) && src_w & 3 &&
1600 1601
	    (rotation == DRM_MODE_ROTATE_270 ||
	     rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1602
		DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
1603 1604 1605 1606 1607 1608
		return -EINVAL;
	}

	return 0;
}

1609 1610
static int skl_plane_check(struct intel_crtc_state *crtc_state,
			   struct intel_plane_state *plane_state)
1611 1612 1613
{
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1614 1615 1616
	const struct drm_framebuffer *fb = plane_state->base.fb;
	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1617 1618
	int ret;

1619 1620 1621 1622
	ret = skl_plane_check_fb(crtc_state, plane_state);
	if (ret)
		return ret;

1623
	/* use scaler when colorkey is not required */
1624
	if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
1625
		min_scale = 1;
1626
		max_scale = skl_max_scale(crtc_state, fb->format->format);
1627 1628
	}

1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
						  &crtc_state->base,
						  min_scale, max_scale,
						  true, true);
	if (ret)
		return ret;

	if (!plane_state->base.visible)
		return 0;

1639 1640 1641 1642
	ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
	if (ret)
		return ret;

1643 1644 1645 1646
	ret = intel_plane_check_src_coordinates(plane_state);
	if (ret)
		return ret;

1647 1648 1649 1650
	ret = skl_plane_check_nv12_rotation(plane_state);
	if (ret)
		return ret;

1651
	ret = skl_check_plane_surface(plane_state);
1652 1653 1654
	if (ret)
		return ret;

1655 1656 1657 1658
	/* HW only has 8 bits pixel precision, disable plane if invisible */
	if (!(plane_state->base.alpha >> 8))
		plane_state->base.visible = false;

1659 1660
	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);

1661
	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1662 1663
		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
							     plane_state);
1664

1665 1666 1667
	return 0;
}

1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698
static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 9;
}

static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
				 const struct drm_intel_sprite_colorkey *set)
{
	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
	struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

	*key = *set;

	/*
	 * We want src key enabled on the
	 * sprite and not on the primary.
	 */
	if (plane->id == PLANE_PRIMARY &&
	    set->flags & I915_SET_COLORKEY_SOURCE)
		key->flags = 0;

	/*
	 * On SKL+ we want dst key enabled on
	 * the primary and not on the sprite.
	 */
	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
	    set->flags & I915_SET_COLORKEY_DESTINATION)
		key->flags = 0;
}

1699 1700
int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv)
1701
{
1702
	struct drm_i915_private *dev_priv = to_i915(dev);
1703 1704
	struct drm_intel_sprite_colorkey *set = data;
	struct drm_plane *plane;
1705 1706 1707
	struct drm_plane_state *plane_state;
	struct drm_atomic_state *state;
	struct drm_modeset_acquire_ctx ctx;
1708 1709
	int ret = 0;

1710 1711 1712
	/* ignore the pointless "none" flag */
	set->flags &= ~I915_SET_COLORKEY_NONE;

1713 1714 1715
	if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
		return -EINVAL;

1716 1717 1718 1719
	/* Make sure we don't try to enable both src & dest simultaneously */
	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
		return -EINVAL;

1720
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1721 1722 1723
	    set->flags & I915_SET_COLORKEY_DESTINATION)
		return -EINVAL;

1724
	plane = drm_plane_find(dev, file_priv, set->plane_id);
1725 1726
	if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
		return -ENOENT;
1727

1728 1729 1730 1731 1732 1733 1734 1735 1736 1737
	/*
	 * SKL+ only plane 2 can do destination keying against plane 1.
	 * Also multiple planes can't do destination keying on the same
	 * pipe simultaneously.
	 */
	if (INTEL_GEN(dev_priv) >= 9 &&
	    to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
	    set->flags & I915_SET_COLORKEY_DESTINATION)
		return -EINVAL;

1738
	drm_modeset_acquire_init(&ctx, 0);
1739

1740 1741 1742 1743
	state = drm_atomic_state_alloc(plane->dev);
	if (!state) {
		ret = -ENOMEM;
		goto out;
1744
	}
1745 1746 1747 1748 1749
	state->acquire_ctx = &ctx;

	while (1) {
		plane_state = drm_atomic_get_plane_state(state, plane);
		ret = PTR_ERR_OR_ZERO(plane_state);
1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
		if (!ret)
			intel_plane_set_ckey(to_intel_plane_state(plane_state), set);

		/*
		 * On some platforms we have to configure
		 * the dst colorkey on the primary plane.
		 */
		if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
			struct intel_crtc *crtc =
				intel_get_crtc_for_pipe(dev_priv,
							to_intel_plane(plane)->pipe);

			plane_state = drm_atomic_get_plane_state(state,
								 crtc->base.primary);
			ret = PTR_ERR_OR_ZERO(plane_state);
			if (!ret)
				intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1767
		}
1768

1769 1770 1771
		if (!ret)
			ret = drm_atomic_commit(state);

1772 1773
		if (ret != -EDEADLK)
			break;
1774

1775 1776 1777
		drm_atomic_state_clear(state);
		drm_modeset_backoff(&ctx);
	}
1778

1779
	drm_atomic_state_put(state);
1780 1781 1782 1783
out:
	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);
	return ret;
1784 1785
}

1786
static const u32 g4x_plane_formats[] = {
1787 1788 1789 1790 1791 1792 1793
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
};

1794
static const u64 i9xx_plane_format_modifiers[] = {
1795 1796 1797 1798 1799
	I915_FORMAT_MOD_X_TILED,
	DRM_FORMAT_MOD_LINEAR,
	DRM_FORMAT_MOD_INVALID
};

1800
static const u32 snb_plane_formats[] = {
1801 1802 1803 1804 1805 1806 1807 1808
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
};

1809
static const u32 vlv_plane_formats[] = {
1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822
	DRM_FORMAT_RGB565,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_ABGR2101010,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
};

1823
static const u32 skl_plane_formats[] = {
1824
	DRM_FORMAT_C8,
1825 1826
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
1827 1828 1829 1830 1831
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
1832 1833 1834 1835 1836 1837
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
};

1838
static const u32 icl_plane_formats[] = {
1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853
	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_Y210,
	DRM_FORMAT_Y212,
	DRM_FORMAT_Y216,
1854 1855 1856
	DRM_FORMAT_XVYU2101010,
	DRM_FORMAT_XVYU12_16161616,
	DRM_FORMAT_XVYU16161616,
1857 1858
};

1859
static const u32 icl_hdr_plane_formats[] = {
1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878
	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_XRGB16161616F,
	DRM_FORMAT_XBGR16161616F,
	DRM_FORMAT_ARGB16161616F,
	DRM_FORMAT_ABGR16161616F,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_Y210,
	DRM_FORMAT_Y212,
	DRM_FORMAT_Y216,
1879 1880 1881
	DRM_FORMAT_XVYU2101010,
	DRM_FORMAT_XVYU12_16161616,
	DRM_FORMAT_XVYU16161616,
1882 1883
};

1884
static const u32 skl_planar_formats[] = {
1885
	DRM_FORMAT_C8,
1886 1887
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
1888 1889 1890 1891 1892
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
1893 1894 1895 1896 1897 1898 1899
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_NV12,
};

1900
static const u32 glk_planar_formats[] = {
1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918
	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_NV12,
	DRM_FORMAT_P010,
	DRM_FORMAT_P012,
	DRM_FORMAT_P016,
};

1919
static const u32 icl_planar_formats[] = {
1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938
	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_NV12,
	DRM_FORMAT_P010,
	DRM_FORMAT_P012,
	DRM_FORMAT_P016,
	DRM_FORMAT_Y210,
	DRM_FORMAT_Y212,
	DRM_FORMAT_Y216,
1939 1940 1941
	DRM_FORMAT_XVYU2101010,
	DRM_FORMAT_XVYU12_16161616,
	DRM_FORMAT_XVYU16161616,
1942 1943
};

1944
static const u32 icl_hdr_planar_formats[] = {
1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967
	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_XRGB16161616F,
	DRM_FORMAT_XBGR16161616F,
	DRM_FORMAT_ARGB16161616F,
	DRM_FORMAT_ABGR16161616F,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_UYVY,
	DRM_FORMAT_VYUY,
	DRM_FORMAT_NV12,
	DRM_FORMAT_P010,
	DRM_FORMAT_P012,
	DRM_FORMAT_P016,
	DRM_FORMAT_Y210,
	DRM_FORMAT_Y212,
	DRM_FORMAT_Y216,
1968 1969 1970
	DRM_FORMAT_XVYU2101010,
	DRM_FORMAT_XVYU12_16161616,
	DRM_FORMAT_XVYU16161616,
1971 1972
};

1973
static const u64 skl_plane_format_modifiers_noccs[] = {
1974 1975 1976 1977 1978 1979 1980
	I915_FORMAT_MOD_Yf_TILED,
	I915_FORMAT_MOD_Y_TILED,
	I915_FORMAT_MOD_X_TILED,
	DRM_FORMAT_MOD_LINEAR,
	DRM_FORMAT_MOD_INVALID
};

1981
static const u64 skl_plane_format_modifiers_ccs[] = {
1982 1983
	I915_FORMAT_MOD_Yf_TILED_CCS,
	I915_FORMAT_MOD_Y_TILED_CCS,
1984 1985
	I915_FORMAT_MOD_Yf_TILED,
	I915_FORMAT_MOD_Y_TILED,
1986 1987 1988 1989 1990
	I915_FORMAT_MOD_X_TILED,
	DRM_FORMAT_MOD_LINEAR,
	DRM_FORMAT_MOD_INVALID
};

1991 1992
static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
					    u32 format, u64 modifier)
1993
{
1994 1995 1996 1997 1998 1999 2000 2001
	switch (modifier) {
	case DRM_FORMAT_MOD_LINEAR:
	case I915_FORMAT_MOD_X_TILED:
		break;
	default:
		return false;
	}

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016
	switch (format) {
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_VYUY:
		if (modifier == DRM_FORMAT_MOD_LINEAR ||
		    modifier == I915_FORMAT_MOD_X_TILED)
			return true;
		/* fall through */
	default:
		return false;
	}
}

2017 2018
static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
					    u32 format, u64 modifier)
2019
{
2020 2021 2022 2023 2024 2025 2026 2027
	switch (modifier) {
	case DRM_FORMAT_MOD_LINEAR:
	case I915_FORMAT_MOD_X_TILED:
		break;
	default:
		return false;
	}

2028
	switch (format) {
2029 2030
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_XBGR8888:
2031 2032 2033 2034
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_VYUY:
2035 2036 2037 2038 2039 2040 2041 2042 2043
		if (modifier == DRM_FORMAT_MOD_LINEAR ||
		    modifier == I915_FORMAT_MOD_X_TILED)
			return true;
		/* fall through */
	default:
		return false;
	}
}

2044 2045
static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
					    u32 format, u64 modifier)
2046
{
2047 2048 2049 2050 2051 2052 2053 2054
	switch (modifier) {
	case DRM_FORMAT_MOD_LINEAR:
	case I915_FORMAT_MOD_X_TILED:
		break;
	default:
		return false;
	}

2055
	switch (format) {
2056
	case DRM_FORMAT_RGB565:
2057
	case DRM_FORMAT_ABGR8888:
2058
	case DRM_FORMAT_ARGB8888:
2059 2060
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_XRGB8888:
2061 2062
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
2063 2064 2065 2066
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_VYUY:
2067 2068 2069 2070 2071 2072 2073 2074 2075
		if (modifier == DRM_FORMAT_MOD_LINEAR ||
		    modifier == I915_FORMAT_MOD_X_TILED)
			return true;
		/* fall through */
	default:
		return false;
	}
}

2076 2077
static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
					   u32 format, u64 modifier)
2078
{
2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
	struct intel_plane *plane = to_intel_plane(_plane);

	switch (modifier) {
	case DRM_FORMAT_MOD_LINEAR:
	case I915_FORMAT_MOD_X_TILED:
	case I915_FORMAT_MOD_Y_TILED:
	case I915_FORMAT_MOD_Yf_TILED:
		break;
	case I915_FORMAT_MOD_Y_TILED_CCS:
	case I915_FORMAT_MOD_Yf_TILED_CCS:
		if (!plane->has_ccs)
			return false;
		break;
	default:
		return false;
	}

2096 2097 2098 2099 2100
	switch (format) {
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ARGB8888:
	case DRM_FORMAT_ABGR8888:
2101
		if (is_ccs_modifier(modifier))
2102 2103
			return true;
		/* fall through */
2104 2105 2106 2107 2108 2109 2110
	case DRM_FORMAT_RGB565:
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_VYUY:
2111
	case DRM_FORMAT_NV12:
2112 2113 2114
	case DRM_FORMAT_P010:
	case DRM_FORMAT_P012:
	case DRM_FORMAT_P016:
2115
	case DRM_FORMAT_XVYU2101010:
2116 2117 2118 2119
		if (modifier == I915_FORMAT_MOD_Yf_TILED)
			return true;
		/* fall through */
	case DRM_FORMAT_C8:
2120 2121 2122 2123
	case DRM_FORMAT_XBGR16161616F:
	case DRM_FORMAT_ABGR16161616F:
	case DRM_FORMAT_XRGB16161616F:
	case DRM_FORMAT_ARGB16161616F:
2124 2125 2126 2127 2128
	case DRM_FORMAT_Y210:
	case DRM_FORMAT_Y212:
	case DRM_FORMAT_Y216:
	case DRM_FORMAT_XVYU12_16161616:
	case DRM_FORMAT_XVYU16161616:
2129 2130 2131 2132 2133 2134 2135 2136 2137 2138
		if (modifier == DRM_FORMAT_MOD_LINEAR ||
		    modifier == I915_FORMAT_MOD_X_TILED ||
		    modifier == I915_FORMAT_MOD_Y_TILED)
			return true;
		/* fall through */
	default:
		return false;
	}
}

2139 2140 2141 2142 2143 2144 2145 2146 2147 2148
static const struct drm_plane_funcs g4x_sprite_funcs = {
	.update_plane = drm_atomic_helper_update_plane,
	.disable_plane = drm_atomic_helper_disable_plane,
	.destroy = intel_plane_destroy,
	.atomic_get_property = intel_plane_atomic_get_property,
	.atomic_set_property = intel_plane_atomic_set_property,
	.atomic_duplicate_state = intel_plane_duplicate_state,
	.atomic_destroy_state = intel_plane_destroy_state,
	.format_mod_supported = g4x_sprite_format_mod_supported,
};
2149

2150 2151 2152 2153 2154 2155 2156 2157 2158 2159
static const struct drm_plane_funcs snb_sprite_funcs = {
	.update_plane = drm_atomic_helper_update_plane,
	.disable_plane = drm_atomic_helper_disable_plane,
	.destroy = intel_plane_destroy,
	.atomic_get_property = intel_plane_atomic_get_property,
	.atomic_set_property = intel_plane_atomic_set_property,
	.atomic_duplicate_state = intel_plane_duplicate_state,
	.atomic_destroy_state = intel_plane_destroy_state,
	.format_mod_supported = snb_sprite_format_mod_supported,
};
2160

2161 2162 2163 2164 2165 2166 2167 2168 2169 2170
static const struct drm_plane_funcs vlv_sprite_funcs = {
	.update_plane = drm_atomic_helper_update_plane,
	.disable_plane = drm_atomic_helper_disable_plane,
	.destroy = intel_plane_destroy,
	.atomic_get_property = intel_plane_atomic_get_property,
	.atomic_set_property = intel_plane_atomic_set_property,
	.atomic_duplicate_state = intel_plane_duplicate_state,
	.atomic_destroy_state = intel_plane_destroy_state,
	.format_mod_supported = vlv_sprite_format_mod_supported,
};
2171

2172
static const struct drm_plane_funcs skl_plane_funcs = {
2173 2174 2175 2176 2177 2178 2179
	.update_plane = drm_atomic_helper_update_plane,
	.disable_plane = drm_atomic_helper_disable_plane,
	.destroy = intel_plane_destroy,
	.atomic_get_property = intel_plane_atomic_get_property,
	.atomic_set_property = intel_plane_atomic_set_property,
	.atomic_duplicate_state = intel_plane_duplicate_state,
	.atomic_destroy_state = intel_plane_destroy_state,
2180
	.format_mod_supported = skl_plane_format_mod_supported,
2181 2182
};

2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
			      enum pipe pipe, enum plane_id plane_id)
{
	if (!HAS_FBC(dev_priv))
		return false;

	return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
}

static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
				 enum pipe pipe, enum plane_id plane_id)
{
	if (INTEL_GEN(dev_priv) >= 11)
2196
		return plane_id <= PLANE_SPRITE3;
2197

2198
	/* Display WA #0870: skl, bxt */
2199 2200 2201
	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
		return false;

2202
	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
2203 2204 2205 2206 2207 2208 2209 2210 2211 2212
		return false;

	if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
		return false;

	return true;
}

static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
			      enum pipe pipe, enum plane_id plane_id)
2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227
{
	if (plane_id == PLANE_CURSOR)
		return false;

	if (INTEL_GEN(dev_priv) >= 10)
		return true;

	if (IS_GEMINILAKE(dev_priv))
		return pipe != PIPE_C;

	return pipe != PIPE_C &&
		(plane_id == PLANE_PRIMARY ||
		 plane_id == PLANE_SPRITE0);
}

2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260
struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
			   enum pipe pipe, enum plane_id plane_id)
{
	struct intel_plane *plane;
	enum drm_plane_type plane_type;
	unsigned int supported_rotations;
	unsigned int possible_crtcs;
	const u64 *modifiers;
	const u32 *formats;
	int num_formats;
	int ret;

	plane = intel_plane_alloc();
	if (IS_ERR(plane))
		return plane;

	plane->pipe = pipe;
	plane->id = plane_id;
	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);

	plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
	if (plane->has_fbc) {
		struct intel_fbc *fbc = &dev_priv->fbc;

		fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
	}

	plane->max_stride = skl_plane_max_stride;
	plane->update_plane = skl_update_plane;
	plane->disable_plane = skl_disable_plane;
	plane->get_hw_state = skl_plane_get_hw_state;
	plane->check_plane = skl_plane_check;
2261 2262
	if (icl_is_nv12_y_plane(plane_id))
		plane->update_slave = icl_update_slave;
2263 2264

	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2265 2266 2267 2268
		if (icl_is_hdr_plane(dev_priv, plane_id)) {
			formats = icl_hdr_planar_formats;
			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
		} else if (INTEL_GEN(dev_priv) >= 11) {
2269 2270 2271
			formats = icl_planar_formats;
			num_formats = ARRAY_SIZE(icl_planar_formats);
		} else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
2272 2273 2274 2275 2276 2277
			formats = glk_planar_formats;
			num_formats = ARRAY_SIZE(glk_planar_formats);
		} else {
			formats = skl_planar_formats;
			num_formats = ARRAY_SIZE(skl_planar_formats);
		}
2278 2279 2280
	} else if (icl_is_hdr_plane(dev_priv, plane_id)) {
		formats = icl_hdr_plane_formats;
		num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2281 2282 2283
	} else if (INTEL_GEN(dev_priv) >= 11) {
		formats = icl_plane_formats;
		num_formats = ARRAY_SIZE(icl_plane_formats);
2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345
	} else {
		formats = skl_plane_formats;
		num_formats = ARRAY_SIZE(skl_plane_formats);
	}

	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
	if (plane->has_ccs)
		modifiers = skl_plane_format_modifiers_ccs;
	else
		modifiers = skl_plane_format_modifiers_noccs;

	if (plane_id == PLANE_PRIMARY)
		plane_type = DRM_PLANE_TYPE_PRIMARY;
	else
		plane_type = DRM_PLANE_TYPE_OVERLAY;

	possible_crtcs = BIT(pipe);

	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
				       possible_crtcs, &skl_plane_funcs,
				       formats, num_formats, modifiers,
				       plane_type,
				       "plane %d%c", plane_id + 1,
				       pipe_name(pipe));
	if (ret)
		goto fail;

	supported_rotations =
		DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
		DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;

	if (INTEL_GEN(dev_priv) >= 10)
		supported_rotations |= DRM_MODE_REFLECT_X;

	drm_plane_create_rotation_property(&plane->base,
					   DRM_MODE_ROTATE_0,
					   supported_rotations);

	drm_plane_create_color_properties(&plane->base,
					  BIT(DRM_COLOR_YCBCR_BT601) |
					  BIT(DRM_COLOR_YCBCR_BT709),
					  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
					  BIT(DRM_COLOR_YCBCR_FULL_RANGE),
					  DRM_COLOR_YCBCR_BT709,
					  DRM_COLOR_YCBCR_LIMITED_RANGE);

	drm_plane_create_alpha_property(&plane->base);
	drm_plane_create_blend_mode_property(&plane->base,
					     BIT(DRM_MODE_BLEND_PIXEL_NONE) |
					     BIT(DRM_MODE_BLEND_PREMULTI) |
					     BIT(DRM_MODE_BLEND_COVERAGE));

	drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);

	return plane;

fail:
	intel_plane_free(plane);

	return ERR_PTR(ret);
}

2346
struct intel_plane *
2347
intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2348
			  enum pipe pipe, int sprite)
2349
{
2350
	struct intel_plane *plane;
2351
	const struct drm_plane_funcs *plane_funcs;
2352
	unsigned long possible_crtcs;
2353
	unsigned int supported_rotations;
2354 2355 2356
	const u64 *modifiers;
	const u32 *formats;
	int num_formats;
2357 2358
	int ret;

2359 2360
	if (INTEL_GEN(dev_priv) >= 9)
		return skl_universal_plane_create(dev_priv, pipe,
2361
						  PLANE_SPRITE0 + sprite);
2362

2363 2364 2365
	plane = intel_plane_alloc();
	if (IS_ERR(plane))
		return plane;
2366

2367
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2368 2369 2370 2371 2372 2373 2374 2375
		plane->max_stride = i9xx_plane_max_stride;
		plane->update_plane = vlv_update_plane;
		plane->disable_plane = vlv_disable_plane;
		plane->get_hw_state = vlv_plane_get_hw_state;
		plane->check_plane = vlv_sprite_check;

		formats = vlv_plane_formats;
		num_formats = ARRAY_SIZE(vlv_plane_formats);
2376
		modifiers = i9xx_plane_format_modifiers;
2377 2378

		plane_funcs = &vlv_sprite_funcs;
2379
	} else if (INTEL_GEN(dev_priv) >= 7) {
2380 2381 2382 2383 2384 2385 2386 2387
		plane->max_stride = g4x_sprite_max_stride;
		plane->update_plane = ivb_update_plane;
		plane->disable_plane = ivb_disable_plane;
		plane->get_hw_state = ivb_plane_get_hw_state;
		plane->check_plane = g4x_sprite_check;

		formats = snb_plane_formats;
		num_formats = ARRAY_SIZE(snb_plane_formats);
2388
		modifiers = i9xx_plane_format_modifiers;
2389 2390

		plane_funcs = &snb_sprite_funcs;
2391
	} else {
2392 2393 2394 2395 2396
		plane->max_stride = g4x_sprite_max_stride;
		plane->update_plane = g4x_update_plane;
		plane->disable_plane = g4x_disable_plane;
		plane->get_hw_state = g4x_plane_get_hw_state;
		plane->check_plane = g4x_sprite_check;
2397

2398
		modifiers = i9xx_plane_format_modifiers;
2399
		if (IS_GEN(dev_priv, 6)) {
2400 2401
			formats = snb_plane_formats;
			num_formats = ARRAY_SIZE(snb_plane_formats);
2402 2403

			plane_funcs = &snb_sprite_funcs;
2404
		} else {
2405 2406
			formats = g4x_plane_formats;
			num_formats = ARRAY_SIZE(g4x_plane_formats);
2407 2408

			plane_funcs = &g4x_sprite_funcs;
2409
		}
2410 2411
	}

2412
	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2413
		supported_rotations =
2414 2415
			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
			DRM_MODE_REFLECT_X;
2416 2417
	} else {
		supported_rotations =
2418
			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2419 2420
	}

2421 2422 2423
	plane->pipe = pipe;
	plane->id = PLANE_SPRITE0 + sprite;
	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
2424

2425
	possible_crtcs = BIT(pipe);
2426

2427
	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2428
				       possible_crtcs, plane_funcs,
2429
				       formats, num_formats, modifiers,
2430
				       DRM_PLANE_TYPE_OVERLAY,
2431
				       "sprite %c", sprite_name(pipe, sprite));
2432 2433
	if (ret)
		goto fail;
2434

2435
	drm_plane_create_rotation_property(&plane->base,
2436
					   DRM_MODE_ROTATE_0,
2437
					   supported_rotations);
2438

2439
	drm_plane_create_color_properties(&plane->base,
2440 2441
					  BIT(DRM_COLOR_YCBCR_BT601) |
					  BIT(DRM_COLOR_YCBCR_BT709),
2442 2443
					  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
					  BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2444
					  DRM_COLOR_YCBCR_BT709,
2445 2446
					  DRM_COLOR_YCBCR_LIMITED_RANGE);

2447
	drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
2448

2449
	return plane;
2450 2451

fail:
2452
	intel_plane_free(plane);
2453

2454
	return ERR_PTR(ret);
2455
}