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/*

  Broadcom B43 wireless driver

  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
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  Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
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  Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
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  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
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  Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
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  SDIO support
  Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>

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  Some parts of the code in this file are derived from the ipw2200
  driver  Copyright(c) 2003 - 2004 Intel Corporation.

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include <linux/delay.h>
#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/if_arp.h>
#include <linux/etherdevice.h>
#include <linux/firmware.h>
#include <linux/workqueue.h>
#include <linux/skbuff.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <asm/unaligned.h>

#include "b43.h"
#include "main.h"
#include "debugfs.h"
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#include "phy_common.h"
#include "phy_g.h"
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#include "phy_n.h"
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#include "dma.h"
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#include "pio.h"
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#include "sysfs.h"
#include "xmit.h"
#include "lo.h"
#include "pcmcia.h"
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#include "sdio.h"
#include <linux/mmc/sdio_func.h>
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MODULE_DESCRIPTION("Broadcom B43 wireless driver");
MODULE_AUTHOR("Martin Langer");
MODULE_AUTHOR("Stefano Brivio");
MODULE_AUTHOR("Michael Buesch");
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MODULE_AUTHOR("Gábor Stefanik");
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MODULE_AUTHOR("Rafał Miłecki");
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MODULE_LICENSE("GPL");

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MODULE_FIRMWARE("b43/ucode11.fw");
MODULE_FIRMWARE("b43/ucode13.fw");
MODULE_FIRMWARE("b43/ucode14.fw");
MODULE_FIRMWARE("b43/ucode15.fw");
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MODULE_FIRMWARE("b43/ucode16_mimo.fw");
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MODULE_FIRMWARE("b43/ucode5.fw");
MODULE_FIRMWARE("b43/ucode9.fw");
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static int modparam_bad_frames_preempt;
module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
MODULE_PARM_DESC(bad_frames_preempt,
		 "enable(1) / disable(0) Bad Frames Preemption");

static char modparam_fwpostfix[16];
module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");

static int modparam_hwpctl;
module_param_named(hwpctl, modparam_hwpctl, int, 0444);
MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");

static int modparam_nohwcrypt;
module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");

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static int modparam_hwtkip;
module_param_named(hwtkip, modparam_hwtkip, int, 0444);
MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");

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static int modparam_qos = 1;
module_param_named(qos, modparam_qos, int, 0444);
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MODULE_PARM_DESC(qos, "Enable QOS support (default on)");

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static int modparam_btcoex = 1;
module_param_named(btcoex, modparam_btcoex, int, 0444);
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MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
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int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
module_param_named(verbose, b43_modparam_verbose, int, 0644);
MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");

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static int b43_modparam_pio = 0;
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module_param_named(pio, b43_modparam_pio, int, 0644);
MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
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static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");

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#ifdef CONFIG_B43_BCMA
static const struct bcma_device_id b43_bcma_tbl[] = {
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	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
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	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
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	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
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	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
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	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
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	BCMA_CORETABLE_END
};
MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
#endif

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#ifdef CONFIG_B43_SSB
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static const struct ssb_device_id b43_ssb_tbl[] = {
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
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	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
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	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
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	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
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	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
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	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
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	SSB_DEVTABLE_END
};
MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
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#endif
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/* Channel and ratetables are shared for all devices.
 * They can't be const, because ieee80211 puts some precalculated
 * data in there. This data is the same for all devices, so we don't
 * get concurrency issues */
#define RATETAB_ENT(_rateid, _flags) \
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	{								\
		.bitrate	= B43_RATE_TO_BASE100KBPS(_rateid),	\
		.hw_value	= (_rateid),				\
		.flags		= (_flags),				\
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	}
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/*
 * NOTE: When changing this, sync with xmit.c's
 *	 b43_plcp_get_bitrate_idx_* functions!
 */
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static struct ieee80211_rate __b43_ratetable[] = {
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	RATETAB_ENT(B43_CCK_RATE_1MB, 0),
	RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
	RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
	RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
	RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
	RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
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};

#define b43_a_ratetable		(__b43_ratetable + 4)
#define b43_a_ratetable_size	8
#define b43_b_ratetable		(__b43_ratetable + 0)
#define b43_b_ratetable_size	4
#define b43_g_ratetable		(__b43_ratetable + 0)
#define b43_g_ratetable_size	12

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#define CHAN2G(_channel, _freq, _flags) {			\
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	.band			= IEEE80211_BAND_2GHZ,		\
	.center_freq		= (_freq),			\
	.hw_value		= (_channel),			\
	.flags			= (_flags),			\
	.max_antenna_gain	= 0,				\
	.max_power		= 30,				\
}
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static struct ieee80211_channel b43_2ghz_chantable[] = {
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	CHAN2G(1, 2412, 0),
	CHAN2G(2, 2417, 0),
	CHAN2G(3, 2422, 0),
	CHAN2G(4, 2427, 0),
	CHAN2G(5, 2432, 0),
	CHAN2G(6, 2437, 0),
	CHAN2G(7, 2442, 0),
	CHAN2G(8, 2447, 0),
	CHAN2G(9, 2452, 0),
	CHAN2G(10, 2457, 0),
	CHAN2G(11, 2462, 0),
	CHAN2G(12, 2467, 0),
	CHAN2G(13, 2472, 0),
	CHAN2G(14, 2484, 0),
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};
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#undef CHAN2G
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#define CHAN4G(_channel, _flags) {				\
	.band			= IEEE80211_BAND_5GHZ,		\
	.center_freq		= 4000 + (5 * (_channel)),	\
	.hw_value		= (_channel),			\
	.flags			= (_flags),			\
	.max_antenna_gain	= 0,				\
	.max_power		= 30,				\
}
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#define CHAN5G(_channel, _flags) {				\
	.band			= IEEE80211_BAND_5GHZ,		\
	.center_freq		= 5000 + (5 * (_channel)),	\
	.hw_value		= (_channel),			\
	.flags			= (_flags),			\
	.max_antenna_gain	= 0,				\
	.max_power		= 30,				\
}
static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
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	CHAN4G(184, 0),		CHAN4G(186, 0),
	CHAN4G(188, 0),		CHAN4G(190, 0),
	CHAN4G(192, 0),		CHAN4G(194, 0),
	CHAN4G(196, 0),		CHAN4G(198, 0),
	CHAN4G(200, 0),		CHAN4G(202, 0),
	CHAN4G(204, 0),		CHAN4G(206, 0),
	CHAN4G(208, 0),		CHAN4G(210, 0),
	CHAN4G(212, 0),		CHAN4G(214, 0),
	CHAN4G(216, 0),		CHAN4G(218, 0),
	CHAN4G(220, 0),		CHAN4G(222, 0),
	CHAN4G(224, 0),		CHAN4G(226, 0),
	CHAN4G(228, 0),
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	CHAN5G(32, 0),		CHAN5G(34, 0),
	CHAN5G(36, 0),		CHAN5G(38, 0),
	CHAN5G(40, 0),		CHAN5G(42, 0),
	CHAN5G(44, 0),		CHAN5G(46, 0),
	CHAN5G(48, 0),		CHAN5G(50, 0),
	CHAN5G(52, 0),		CHAN5G(54, 0),
	CHAN5G(56, 0),		CHAN5G(58, 0),
	CHAN5G(60, 0),		CHAN5G(62, 0),
	CHAN5G(64, 0),		CHAN5G(66, 0),
	CHAN5G(68, 0),		CHAN5G(70, 0),
	CHAN5G(72, 0),		CHAN5G(74, 0),
	CHAN5G(76, 0),		CHAN5G(78, 0),
	CHAN5G(80, 0),		CHAN5G(82, 0),
	CHAN5G(84, 0),		CHAN5G(86, 0),
	CHAN5G(88, 0),		CHAN5G(90, 0),
	CHAN5G(92, 0),		CHAN5G(94, 0),
	CHAN5G(96, 0),		CHAN5G(98, 0),
	CHAN5G(100, 0),		CHAN5G(102, 0),
	CHAN5G(104, 0),		CHAN5G(106, 0),
	CHAN5G(108, 0),		CHAN5G(110, 0),
	CHAN5G(112, 0),		CHAN5G(114, 0),
	CHAN5G(116, 0),		CHAN5G(118, 0),
	CHAN5G(120, 0),		CHAN5G(122, 0),
	CHAN5G(124, 0),		CHAN5G(126, 0),
	CHAN5G(128, 0),		CHAN5G(130, 0),
	CHAN5G(132, 0),		CHAN5G(134, 0),
	CHAN5G(136, 0),		CHAN5G(138, 0),
	CHAN5G(140, 0),		CHAN5G(142, 0),
	CHAN5G(144, 0),		CHAN5G(145, 0),
	CHAN5G(146, 0),		CHAN5G(147, 0),
	CHAN5G(148, 0),		CHAN5G(149, 0),
	CHAN5G(150, 0),		CHAN5G(151, 0),
	CHAN5G(152, 0),		CHAN5G(153, 0),
	CHAN5G(154, 0),		CHAN5G(155, 0),
	CHAN5G(156, 0),		CHAN5G(157, 0),
	CHAN5G(158, 0),		CHAN5G(159, 0),
	CHAN5G(160, 0),		CHAN5G(161, 0),
	CHAN5G(162, 0),		CHAN5G(163, 0),
	CHAN5G(164, 0),		CHAN5G(165, 0),
	CHAN5G(166, 0),		CHAN5G(168, 0),
	CHAN5G(170, 0),		CHAN5G(172, 0),
	CHAN5G(174, 0),		CHAN5G(176, 0),
	CHAN5G(178, 0),		CHAN5G(180, 0),
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	CHAN5G(182, 0),
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};

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static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
	CHAN5G(34, 0),		CHAN5G(36, 0),
	CHAN5G(38, 0),		CHAN5G(40, 0),
	CHAN5G(42, 0),		CHAN5G(44, 0),
	CHAN5G(46, 0),		CHAN5G(48, 0),
	CHAN5G(52, 0),		CHAN5G(56, 0),
	CHAN5G(60, 0),		CHAN5G(64, 0),
	CHAN5G(100, 0),		CHAN5G(104, 0),
	CHAN5G(108, 0),		CHAN5G(112, 0),
	CHAN5G(116, 0),		CHAN5G(120, 0),
	CHAN5G(124, 0),		CHAN5G(128, 0),
	CHAN5G(132, 0),		CHAN5G(136, 0),
	CHAN5G(140, 0),		CHAN5G(149, 0),
	CHAN5G(153, 0),		CHAN5G(157, 0),
	CHAN5G(161, 0),		CHAN5G(165, 0),
	CHAN5G(184, 0),		CHAN5G(188, 0),
	CHAN5G(192, 0),		CHAN5G(196, 0),
	CHAN5G(200, 0),		CHAN5G(204, 0),
	CHAN5G(208, 0),		CHAN5G(212, 0),
	CHAN5G(216, 0),
};
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#undef CHAN4G
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#undef CHAN5G

static struct ieee80211_supported_band b43_band_5GHz_nphy = {
	.band		= IEEE80211_BAND_5GHZ,
	.channels	= b43_5ghz_nphy_chantable,
	.n_channels	= ARRAY_SIZE(b43_5ghz_nphy_chantable),
	.bitrates	= b43_a_ratetable,
	.n_bitrates	= b43_a_ratetable_size,
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};
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static struct ieee80211_supported_band b43_band_5GHz_aphy = {
	.band		= IEEE80211_BAND_5GHZ,
	.channels	= b43_5ghz_aphy_chantable,
	.n_channels	= ARRAY_SIZE(b43_5ghz_aphy_chantable),
	.bitrates	= b43_a_ratetable,
	.n_bitrates	= b43_a_ratetable_size,
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};
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static struct ieee80211_supported_band b43_band_2GHz = {
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	.band		= IEEE80211_BAND_2GHZ,
	.channels	= b43_2ghz_chantable,
	.n_channels	= ARRAY_SIZE(b43_2ghz_chantable),
	.bitrates	= b43_g_ratetable,
	.n_bitrates	= b43_g_ratetable_size,
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};

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static void b43_wireless_core_exit(struct b43_wldev *dev);
static int b43_wireless_core_init(struct b43_wldev *dev);
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static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
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static int b43_wireless_core_start(struct b43_wldev *dev);
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static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
				    struct ieee80211_vif *vif,
				    struct ieee80211_bss_conf *conf,
				    u32 changed);
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static int b43_ratelimit(struct b43_wl *wl)
{
	if (!wl || !wl->current_dev)
		return 1;
	if (b43_status(wl->current_dev) < B43_STAT_STARTED)
		return 1;
	/* We are up and running.
	 * Ratelimit the messages to avoid DoS over the net. */
	return net_ratelimit();
}

void b43info(struct b43_wl *wl, const char *fmt, ...)
{
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	struct va_format vaf;
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	va_list args;

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	if (b43_modparam_verbose < B43_VERBOSITY_INFO)
		return;
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	if (!b43_ratelimit(wl))
		return;
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	va_start(args, fmt);
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	vaf.fmt = fmt;
	vaf.va = &args;

	printk(KERN_INFO "b43-%s: %pV",
	       (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);

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	va_end(args);
}

void b43err(struct b43_wl *wl, const char *fmt, ...)
{
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	struct va_format vaf;
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	va_list args;

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	if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
		return;
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	if (!b43_ratelimit(wl))
		return;
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	va_start(args, fmt);
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	vaf.fmt = fmt;
	vaf.va = &args;

	printk(KERN_ERR "b43-%s ERROR: %pV",
	       (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);

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	va_end(args);
}

void b43warn(struct b43_wl *wl, const char *fmt, ...)
{
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	struct va_format vaf;
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	va_list args;

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	if (b43_modparam_verbose < B43_VERBOSITY_WARN)
		return;
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	if (!b43_ratelimit(wl))
		return;
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	va_start(args, fmt);
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	vaf.fmt = fmt;
	vaf.va = &args;

	printk(KERN_WARNING "b43-%s warning: %pV",
	       (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);

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	va_end(args);
}

void b43dbg(struct b43_wl *wl, const char *fmt, ...)
{
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	struct va_format vaf;
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	va_list args;

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	if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
		return;
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	va_start(args, fmt);
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	vaf.fmt = fmt;
	vaf.va = &args;

	printk(KERN_DEBUG "b43-%s debug: %pV",
	       (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);

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	va_end(args);
}

static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
{
	u32 macctl;

	B43_WARN_ON(offset % 4 != 0);

	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	if (macctl & B43_MACCTL_BE)
		val = swab32(val);

	b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
	mmiowb();
	b43_write32(dev, B43_MMIO_RAM_DATA, val);
}

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static inline void b43_shm_control_word(struct b43_wldev *dev,
					u16 routing, u16 offset)
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{
	u32 control;

	/* "offset" is the WORD offset. */
	control = routing;
	control <<= 16;
	control |= offset;
	b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
}

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u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
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{
	u32 ret;

	if (routing == B43_SHM_SHARED) {
		B43_WARN_ON(offset & 0x0001);
		if (offset & 0x0003) {
			/* Unaligned access */
			b43_shm_control_word(dev, routing, offset >> 2);
			ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
			b43_shm_control_word(dev, routing, (offset >> 2) + 1);
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			ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
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			goto out;
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		}
		offset >>= 2;
	}
	b43_shm_control_word(dev, routing, offset);
	ret = b43_read32(dev, B43_MMIO_SHM_DATA);
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out:
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	return ret;
}

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u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
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{
	u16 ret;

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	if (routing == B43_SHM_SHARED) {
		B43_WARN_ON(offset & 0x0001);
		if (offset & 0x0003) {
			/* Unaligned access */
			b43_shm_control_word(dev, routing, offset >> 2);
			ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);

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			goto out;
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		}
		offset >>= 2;
	}
	b43_shm_control_word(dev, routing, offset);
	ret = b43_read16(dev, B43_MMIO_SHM_DATA);
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out:
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	return ret;
}

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void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
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{
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	if (routing == B43_SHM_SHARED) {
		B43_WARN_ON(offset & 0x0001);
		if (offset & 0x0003) {
			/* Unaligned access */
			b43_shm_control_word(dev, routing, offset >> 2);
			b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
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				    value & 0xFFFF);
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			b43_shm_control_word(dev, routing, (offset >> 2) + 1);
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			b43_write16(dev, B43_MMIO_SHM_DATA,
				    (value >> 16) & 0xFFFF);
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			return;
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		}
		offset >>= 2;
	}
	b43_shm_control_word(dev, routing, offset);
	b43_write32(dev, B43_MMIO_SHM_DATA, value);
}

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void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
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{
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	if (routing == B43_SHM_SHARED) {
		B43_WARN_ON(offset & 0x0001);
		if (offset & 0x0003) {
			/* Unaligned access */
			b43_shm_control_word(dev, routing, offset >> 2);
			b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
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			return;
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		}
		offset >>= 2;
	}
	b43_shm_control_word(dev, routing, offset);
	b43_write16(dev, B43_MMIO_SHM_DATA, value);
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}

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/* Read HostFlags */
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u64 b43_hf_read(struct b43_wldev *dev)
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{
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	u64 ret;
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	ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
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	ret <<= 16;
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	ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
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	ret <<= 16;
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	ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
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	return ret;
}

/* Write HostFlags */
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void b43_hf_write(struct b43_wldev *dev, u64 value)
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{
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	u16 lo, mi, hi;

	lo = (value & 0x00000000FFFFULL);
	mi = (value & 0x0000FFFF0000ULL) >> 16;
	hi = (value & 0xFFFF00000000ULL) >> 32;
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	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
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}

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/* Read the firmware capabilities bitmask (Opensource firmware only) */
static u16 b43_fwcapa_read(struct b43_wldev *dev)
{
	B43_WARN_ON(!dev->fw.opensource);
	return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
}

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void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
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{
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	u32 low, high;

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	B43_WARN_ON(dev->dev->core_rev < 3);
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	/* The hardware guarantees us an atomic read, if we
	 * read the low register first. */
	low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
	high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);

	*tsf = high;
	*tsf <<= 32;
	*tsf |= low;
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}

static void b43_time_lock(struct b43_wldev *dev)
{
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	b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
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	/* Commit the write */
	b43_read32(dev, B43_MMIO_MACCTL);
}

static void b43_time_unlock(struct b43_wldev *dev)
{
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	b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
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	/* Commit the write */
	b43_read32(dev, B43_MMIO_MACCTL);
}

static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
{
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	u32 low, high;

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	B43_WARN_ON(dev->dev->core_rev < 3);
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	low = tsf;
	high = (tsf >> 32);
	/* The hardware guarantees us an atomic write, if we
	 * write the low register first. */
	b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
	mmiowb();
	b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
	mmiowb();
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}

void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
{
	b43_time_lock(dev);
	b43_tsf_write_locked(dev, tsf);
	b43_time_unlock(dev);
}

static
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void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
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{
	static const u8 zero_addr[ETH_ALEN] = { 0 };
	u16 data;

	if (!mac)
		mac = zero_addr;

	offset |= 0x0020;
	b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);

	data = mac[0];
	data |= mac[1] << 8;
	b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
	data = mac[2];
	data |= mac[3] << 8;
	b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
	data = mac[4];
	data |= mac[5] << 8;
	b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
}

static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
{
	const u8 *mac;
	const u8 *bssid;
	u8 mac_bssid[ETH_ALEN * 2];
	int i;
	u32 tmp;

	bssid = dev->wl->bssid;
	mac = dev->wl->mac_addr;

	b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);

	memcpy(mac_bssid, mac, ETH_ALEN);
	memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);

	/* Write our MAC address and BSSID to template ram */
	for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
		tmp = (u32) (mac_bssid[i + 0]);
		tmp |= (u32) (mac_bssid[i + 1]) << 8;
		tmp |= (u32) (mac_bssid[i + 2]) << 16;
		tmp |= (u32) (mac_bssid[i + 3]) << 24;
		b43_ram_write(dev, 0x20 + i, tmp);
	}
}

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static void b43_upload_card_macaddress(struct b43_wldev *dev)
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{
	b43_write_mac_bssid_templates(dev);
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	b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
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}

static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
{
	/* slot_time is in usec. */
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	/* This test used to exit for all but a G PHY. */
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
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		return;
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	b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
	/* Shared memory location 0x0010 is the slot time and should be
	 * set to slot_time; however, this register is initially 0 and changing
	 * the value adversely affects the transmit rate for BCM4311
	 * devices. Until this behavior is unterstood, delete this step
	 *
	 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
	 */
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}

static void b43_short_slot_timing_enable(struct b43_wldev *dev)
{
	b43_set_slot_time(dev, 9);
}

static void b43_short_slot_timing_disable(struct b43_wldev *dev)
{
	b43_set_slot_time(dev, 20);
}

/* DummyTransmission function, as documented on
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 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
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 */
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void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
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{
	struct b43_phy *phy = &dev->phy;
	unsigned int i, max_loop;
	u16 value;
	u32 buffer[5] = {
		0x00000000,
		0x00D40000,
		0x00000000,
		0x01000000,
		0x00000000,
	};

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	if (ofdm) {
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		max_loop = 0x1E;
		buffer[0] = 0x000201CC;
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	} else {
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		max_loop = 0xFA;
		buffer[0] = 0x000B846E;
	}

	for (i = 0; i < 5; i++)
		b43_ram_write(dev, i * 4, buffer[i]);

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	b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);

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	if (dev->dev->core_rev < 11)
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		b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
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	else
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		b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);

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	value = (ofdm ? 0x41 : 0x40);
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	b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
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	if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
	    phy->type == B43_PHYTYPE_LCN)
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		b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);

	b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
	b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);

	b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
	b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
	b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
	b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
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	if (!pa_on && phy->type == B43_PHYTYPE_N)
		; /*b43_nphy_pa_override(dev, false) */
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	switch (phy->type) {
	case B43_PHYTYPE_N:
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	case B43_PHYTYPE_LCN:
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		b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
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		break;
	case B43_PHYTYPE_LP:
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		b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
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		break;
	default:
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		b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
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	}
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	b43_read16(dev, B43_MMIO_TXE0_AUX);
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	if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
		b43_radio_write16(dev, 0x0051, 0x0017);
	for (i = 0x00; i < max_loop; i++) {
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		value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
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		if (value & 0x0080)
			break;
		udelay(10);
	}
	for (i = 0x00; i < 0x0A; i++) {
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		value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
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		if (value & 0x0400)
			break;
		udelay(10);
	}
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	for (i = 0x00; i < 0x19; i++) {
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		value = b43_read16(dev, B43_MMIO_IFSSTAT);
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		if (!(value & 0x0100))
			break;
		udelay(10);
	}
	if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
		b43_radio_write16(dev, 0x0051, 0x0037);
}

static void key_write(struct b43_wldev *dev,
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		      u8 index, u8 algorithm, const u8 *key)
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{
	unsigned int i;
	u32 offset;
	u16 value;
	u16 kidx;

	/* Key index/algo block */
	kidx = b43_kidx_to_fw(dev, index);
	value = ((kidx << 4) | algorithm);
	b43_shm_write16(dev, B43_SHM_SHARED,
			B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);

	/* Write the key to the Key Table Pointer offset */
	offset = dev->ktp + (index * B43_SEC_KEYSIZE);
	for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
		value = key[i];
		value |= (u16) (key[i + 1]) << 8;
		b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
	}
}

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static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
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{
	u32 addrtmp[2] = { 0, 0, };
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	u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
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	if (b43_new_kidx_api(dev))
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		pairwise_keys_start = B43_NR_GROUP_KEYS;
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	B43_WARN_ON(index < pairwise_keys_start);
	/* We have four default TX keys and possibly four default RX keys.
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	 * Physical mac 0 is mapped to physical key 4 or 8, depending
	 * on the firmware version.
	 * So we must adjust the index here.
	 */
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	index -= pairwise_keys_start;
	B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
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	if (addr) {
		addrtmp[0] = addr[0];
		addrtmp[0] |= ((u32) (addr[1]) << 8);
		addrtmp[0] |= ((u32) (addr[2]) << 16);
		addrtmp[0] |= ((u32) (addr[3]) << 24);
		addrtmp[1] = addr[4];
		addrtmp[1] |= ((u32) (addr[5]) << 8);
	}

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	/* Receive match transmitter address (RCMTA) mechanism */
	b43_shm_write32(dev, B43_SHM_RCMTA,
			(index * 2) + 0, addrtmp[0]);
	b43_shm_write16(dev, B43_SHM_RCMTA,
			(index * 2) + 1, addrtmp[1]);
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}

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/* The ucode will use phase1 key with TEK key to decrypt rx packets.
 * When a packet is received, the iv32 is checked.
 * - if it doesn't the packet is returned without modification (and software
 *   decryption can be done). That's what happen when iv16 wrap.
 * - if it does, the rc4 key is computed, and decryption is tried.
 *   Either it will success and B43_RX_MAC_DEC is returned,
 *   either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
 *   and the packet is not usable (it got modified by the ucode).
 * So in order to never have B43_RX_MAC_DECERR, we should provide
 * a iv32 and phase1key that match. Because we drop packets in case of
 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
 * packets will be lost without higher layer knowing (ie no resync possible
 * until next wrap).
 *
 * NOTE : this should support 50 key like RCMTA because
 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
 */
static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
		u16 *phase1key)
{
	unsigned int i;
	u32 offset;
	u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;

	if (!modparam_hwtkip)
		return;

	if (b43_new_kidx_api(dev))
		pairwise_keys_start = B43_NR_GROUP_KEYS;

	B43_WARN_ON(index < pairwise_keys_start);
	/* We have four default TX keys and possibly four default RX keys.
	 * Physical mac 0 is mapped to physical key 4 or 8, depending
	 * on the firmware version.
	 * So we must adjust the index here.
	 */
	index -= pairwise_keys_start;
	B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);

	if (b43_debug(dev, B43_DBG_KEYS)) {
		b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
				index, iv32);
	}
	/* Write the key to the  RX tkip shared mem */
	offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
	for (i = 0; i < 10; i += 2) {
		b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
				phase1key ? phase1key[i / 2] : 0);
	}
	b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
	b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
}

static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
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				   struct ieee80211_vif *vif,
				   struct ieee80211_key_conf *keyconf,
				   struct ieee80211_sta *sta,
				   u32 iv32, u16 *phase1key)
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{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;
	int index = keyconf->hw_key_idx;

	if (B43_WARN_ON(!modparam_hwtkip))
		return;

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	/* This is only called from the RX path through mac80211, where
	 * our mutex is already locked. */
	B43_WARN_ON(!mutex_is_locked(&wl->mutex));
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	dev = wl->current_dev;
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	B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
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	keymac_write(dev, index, NULL);	/* First zero out mac to avoid race */

	rx_tkip_phase1_write(dev, index, iv32, phase1key);
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	/* only pairwise TKIP keys are supported right now */
	if (WARN_ON(!sta))
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		return;
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	keymac_write(dev, index, sta->addr);
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}

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static void do_key_write(struct b43_wldev *dev,
			 u8 index, u8 algorithm,
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			 const u8 *key, size_t key_len, const u8 *mac_addr)
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{
	u8 buf[B43_SEC_KEYSIZE] = { 0, };
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	u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
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	if (b43_new_kidx_api(dev))
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		pairwise_keys_start = B43_NR_GROUP_KEYS;
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	B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
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	B43_WARN_ON(key_len > B43_SEC_KEYSIZE);

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	if (index >= pairwise_keys_start)
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		keymac_write(dev, index, NULL);	/* First zero out mac. */
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	if (algorithm == B43_SEC_ALGO_TKIP) {
		/*
		 * We should provide an initial iv32, phase1key pair.
		 * We could start with iv32=0 and compute the corresponding
		 * phase1key, but this means calling ieee80211_get_tkip_key
		 * with a fake skb (or export other tkip function).
		 * Because we are lazy we hope iv32 won't start with
		 * 0xffffffff and let's b43_op_update_tkip_key provide a
		 * correct pair.
		 */
		rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
	} else if (index >= pairwise_keys_start) /* clear it */
		rx_tkip_phase1_write(dev, index, 0, NULL);
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	if (key)
		memcpy(buf, key, key_len);
	key_write(dev, index, algorithm, buf);
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	if (index >= pairwise_keys_start)
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		keymac_write(dev, index, mac_addr);

	dev->key[index].algorithm = algorithm;
}

static int b43_key_write(struct b43_wldev *dev,
			 int index, u8 algorithm,
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			 const u8 *key, size_t key_len,
			 const u8 *mac_addr,
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			 struct ieee80211_key_conf *keyconf)
{
	int i;
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	int pairwise_keys_start;
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	/* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
	 * 	- Temporal Encryption Key (128 bits)
	 * 	- Temporal Authenticator Tx MIC Key (64 bits)
	 * 	- Temporal Authenticator Rx MIC Key (64 bits)
	 *
	 * 	Hardware only store TEK
	 */
	if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
		key_len = 16;
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	if (key_len > B43_SEC_KEYSIZE)
		return -EINVAL;
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	for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
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		/* Check that we don't already have this key. */
		B43_WARN_ON(dev->key[i].keyconf == keyconf);
	}
	if (index < 0) {
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		/* Pairwise key. Get an empty slot for the key. */
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		if (b43_new_kidx_api(dev))
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			pairwise_keys_start = B43_NR_GROUP_KEYS;
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		else
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			pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
		for (i = pairwise_keys_start;
		     i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
		     i++) {
			B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
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			if (!dev->key[i].keyconf) {
				/* found empty */
				index = i;
				break;
			}
		}
		if (index < 0) {
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			b43warn(dev->wl, "Out of hardware key memory\n");
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			return -ENOSPC;
		}
	} else
		B43_WARN_ON(index > 3);

	do_key_write(dev, index, algorithm, key, key_len, mac_addr);
	if ((index <= 3) && !b43_new_kidx_api(dev)) {
		/* Default RX key */
		B43_WARN_ON(mac_addr);
		do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
	}
	keyconf->hw_key_idx = index;
	dev->key[index].keyconf = keyconf;

	return 0;
}

static int b43_key_clear(struct b43_wldev *dev, int index)
{
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	if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
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		return -EINVAL;
	do_key_write(dev, index, B43_SEC_ALGO_NONE,
		     NULL, B43_SEC_KEYSIZE, NULL);
	if ((index <= 3) && !b43_new_kidx_api(dev)) {
		do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
			     NULL, B43_SEC_KEYSIZE, NULL);
	}
	dev->key[index].keyconf = NULL;

	return 0;
}

static void b43_clear_keys(struct b43_wldev *dev)
{
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	int i, count;
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	if (b43_new_kidx_api(dev))
		count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
	else
		count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
	for (i = 0; i < count; i++)
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		b43_key_clear(dev, i);
}

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static void b43_dump_keymemory(struct b43_wldev *dev)
{
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	unsigned int i, index, count, offset, pairwise_keys_start;
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	u8 mac[ETH_ALEN];
	u16 algo;
	u32 rcmta0;
	u16 rcmta1;
	u64 hf;
	struct b43_key *key;

	if (!b43_debug(dev, B43_DBG_KEYS))
		return;

	hf = b43_hf_read(dev);
	b43dbg(dev->wl, "Hardware key memory dump:  USEDEFKEYS=%u\n",
	       !!(hf & B43_HF_USEDEFKEYS));
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	if (b43_new_kidx_api(dev)) {
		pairwise_keys_start = B43_NR_GROUP_KEYS;
		count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
	} else {
		pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
		count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
	}
	for (index = 0; index < count; index++) {
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		key = &(dev->key[index]);
		printk(KERN_DEBUG "Key slot %02u: %s",
		       index, (key->keyconf == NULL) ? " " : "*");
		offset = dev->ktp + (index * B43_SEC_KEYSIZE);
		for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
			u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
			printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
		}

		algo = b43_shm_read16(dev, B43_SHM_SHARED,
				      B43_SHM_SH_KEYIDXBLOCK + (index * 2));
		printk("   Algo: %04X/%02X", algo, key->algorithm);

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		if (index >= pairwise_keys_start) {
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			if (key->algorithm == B43_SEC_ALGO_TKIP) {
				printk("   TKIP: ");
				offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
				for (i = 0; i < 14; i += 2) {
					u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
					printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
				}
			}
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			rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
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						((index - pairwise_keys_start) * 2) + 0);
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			rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
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						((index - pairwise_keys_start) * 2) + 1);
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			*((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
			*((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
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			printk("   MAC: %pM", mac);
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		} else
			printk("   DEFAULT KEY");
		printk("\n");
	}
}

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void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
{
	u32 macctl;
	u16 ucstat;
	bool hwps;
	bool awake;
	int i;

	B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
		    (ps_flags & B43_PS_DISABLED));
	B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));

	if (ps_flags & B43_PS_ENABLED) {
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		hwps = true;
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	} else if (ps_flags & B43_PS_DISABLED) {
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		hwps = false;
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	} else {
		//TODO: If powersave is not off and FIXME is not set and we are not in adhoc
		//      and thus is not an AP and we are associated, set bit 25
	}
	if (ps_flags & B43_PS_AWAKE) {
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		awake = true;
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	} else if (ps_flags & B43_PS_ASLEEP) {
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		awake = false;
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	} else {
		//TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
		//      or we are associated, or FIXME, or the latest PS-Poll packet sent was
		//      successful, set bit26
	}

/* FIXME: For now we force awake-on and hwps-off */
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	hwps = false;
	awake = true;
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	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	if (hwps)
		macctl |= B43_MACCTL_HWPS;
	else
		macctl &= ~B43_MACCTL_HWPS;
	if (awake)
		macctl |= B43_MACCTL_AWAKE;
	else
		macctl &= ~B43_MACCTL_AWAKE;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	/* Commit write */
	b43_read32(dev, B43_MMIO_MACCTL);
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	if (awake && dev->dev->core_rev >= 5) {
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		/* Wait for the microcode to wake up. */
		for (i = 0; i < 100; i++) {
			ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
						B43_SHM_SH_UCODESTAT);
			if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
				break;
			udelay(10);
		}
	}
}

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#ifdef CONFIG_B43_BCMA
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static void b43_bcma_phy_reset(struct b43_wldev *dev)
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{
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	u32 flags;
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	/* Put PHY into reset */
	flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	flags |= B43_BCMA_IOCTL_PHY_RESET;
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	flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
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	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
	udelay(2);

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	b43_phy_take_out_of_reset(dev);
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}
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static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
{
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	u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
		  B43_BCMA_CLKCTLST_PHY_PLL_REQ;
	u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
		     B43_BCMA_CLKCTLST_PHY_PLL_ST;
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	u32 flags;

	flags = B43_BCMA_IOCTL_PHY_CLKEN;
	if (gmode)
		flags |= B43_BCMA_IOCTL_GMODE;
	b43_device_enable(dev, flags);
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	bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
	b43_bcma_phy_reset(dev);
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	bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
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}
#endif

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#ifdef CONFIG_B43_SSB
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static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
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{
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	u32 flags = 0;
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	if (gmode)
		flags |= B43_TMSLOW_GMODE;
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	flags |= B43_TMSLOW_PHYCLKEN;
	flags |= B43_TMSLOW_PHYRESET;
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	if (dev->phy.type == B43_PHYTYPE_N)
		flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
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	b43_device_enable(dev, flags);
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	msleep(2);		/* Wait for the PLL to turn on. */

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	b43_phy_take_out_of_reset(dev);
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}
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#endif
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void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
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{
	u32 macctl;

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	switch (dev->dev->bus_type) {
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#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		b43_bcma_wireless_core_reset(dev, gmode);
		break;
#endif
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#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		b43_ssb_wireless_core_reset(dev, gmode);
		break;
#endif
	}
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	/* Turn Analog ON, but only if we already know the PHY-type.
	 * This protects against very early setup where we don't know the
	 * PHY-type, yet. wireless_core_reset will be called once again later,
	 * when we know the PHY-type. */
	if (dev->phy.ops)
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		dev->phy.ops->switch_analog(dev, 1);
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	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl &= ~B43_MACCTL_GMODE;
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	if (gmode)
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		macctl |= B43_MACCTL_GMODE;
	macctl |= B43_MACCTL_IHR_ENABLED;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
}

static void handle_irq_transmit_status(struct b43_wldev *dev)
{
	u32 v0, v1;
	u16 tmp;
	struct b43_txstatus stat;

	while (1) {
		v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
		if (!(v0 & 0x00000001))
			break;
		v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);

		stat.cookie = (v0 >> 16);
		stat.seq = (v1 & 0x0000FFFF);
		stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
		tmp = (v0 & 0x0000FFFF);
		stat.frame_count = ((tmp & 0xF000) >> 12);
		stat.rts_count = ((tmp & 0x0F00) >> 8);
		stat.supp_reason = ((tmp & 0x001C) >> 2);
		stat.pm_indicated = !!(tmp & 0x0080);
		stat.intermediate = !!(tmp & 0x0040);
		stat.for_ampdu = !!(tmp & 0x0020);
		stat.acked = !!(tmp & 0x0002);

		b43_handle_txstatus(dev, &stat);
	}
}

static void drain_txstatus_queue(struct b43_wldev *dev)
{
	u32 dummy;

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	if (dev->dev->core_rev < 5)
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		return;
	/* Read all entries from the microcode TXstatus FIFO
	 * and throw them away.
	 */
	while (1) {
		dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
		if (!(dummy & 0x00000001))
			break;
		dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
	}
}

static u32 b43_jssi_read(struct b43_wldev *dev)
{
	u32 val = 0;

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	val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
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	val <<= 16;
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	val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
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	return val;
}

static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
{
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	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
			(jssi & 0x0000FFFF));
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
			(jssi & 0xFFFF0000) >> 16);
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}

static void b43_generate_noise_sample(struct b43_wldev *dev)
{
	b43_jssi_write(dev, 0x7F7F7F7F);
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	b43_write32(dev, B43_MMIO_MACCMD,
		    b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
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}

static void b43_calculate_link_quality(struct b43_wldev *dev)
{
	/* Top half of Link Quality calculation. */

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	if (dev->phy.type != B43_PHYTYPE_G)
		return;
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	if (dev->noisecalc.calculation_running)
		return;
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	dev->noisecalc.calculation_running = true;
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	dev->noisecalc.nr_samples = 0;

	b43_generate_noise_sample(dev);
}

static void handle_irq_noise(struct b43_wldev *dev)
{
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	struct b43_phy_g *phy = dev->phy.g;
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	u16 tmp;
	u8 noise[4];
	u8 i, j;
	s32 average;

	/* Bottom half of Link Quality calculation. */

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	if (dev->phy.type != B43_PHYTYPE_G)
		return;

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	/* Possible race condition: It might be possible that the user
	 * changed to a different channel in the meantime since we
	 * started the calculation. We ignore that fact, since it's
	 * not really that much of a problem. The background noise is
	 * an estimation only anyway. Slightly wrong results will get damped
	 * by the averaging of the 8 sample rounds. Additionally the
	 * value is shortlived. So it will be replaced by the next noise
	 * calculation round soon. */

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	B43_WARN_ON(!dev->noisecalc.calculation_running);
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	*((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
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	if (noise[0] == 0x7F || noise[1] == 0x7F ||
	    noise[2] == 0x7F || noise[3] == 0x7F)
		goto generate_new;

	/* Get the noise samples. */
	B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
	i = dev->noisecalc.nr_samples;
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	noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
	noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
	noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
	noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
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	dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
	dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
	dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
	dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
	dev->noisecalc.nr_samples++;
	if (dev->noisecalc.nr_samples == 8) {
		/* Calculate the Link Quality by the noise samples. */
		average = 0;
		for (i = 0; i < 8; i++) {
			for (j = 0; j < 4; j++)
				average += dev->noisecalc.samples[i][j];
		}
		average /= (8 * 4);
		average *= 125;
		average += 64;
		average /= 128;
		tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
		tmp = (tmp / 128) & 0x1F;
		if (tmp >= 8)
			average += 2;
		else
			average -= 25;
		if (tmp == 8)
			average -= 72;
		else
			average -= 48;

		dev->stats.link_noise = average;
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		dev->noisecalc.calculation_running = false;
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		return;
	}
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generate_new:
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	b43_generate_noise_sample(dev);
}

static void handle_irq_tbtt_indication(struct b43_wldev *dev)
{
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	if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
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		///TODO: PS TBTT
	} else {
		if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
			b43_power_saving_ctl_bits(dev, 0);
	}
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	if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
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		dev->dfq_valid = true;
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}

static void handle_irq_atim_end(struct b43_wldev *dev)
{
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	if (dev->dfq_valid) {
		b43_write32(dev, B43_MMIO_MACCMD,
			    b43_read32(dev, B43_MMIO_MACCMD)
			    | B43_MACCMD_DFQ_VALID);
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		dev->dfq_valid = false;
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	}
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}

static void handle_irq_pmq(struct b43_wldev *dev)
{
	u32 tmp;

	//TODO: AP mode.

	while (1) {
		tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
		if (!(tmp & 0x00000008))
			break;
	}
	/* 16bit write is odd, but correct. */
	b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
}

static void b43_write_template_common(struct b43_wldev *dev,
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				      const u8 *data, u16 size,
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				      u16 ram_offset,
				      u16 shm_size_offset, u8 rate)
{
	u32 i, tmp;
	struct b43_plcp_hdr4 plcp;

	plcp.data = 0;
	b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
	b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
	ram_offset += sizeof(u32);
	/* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
	 * So leave the first two bytes of the next write blank.
	 */
	tmp = (u32) (data[0]) << 16;
	tmp |= (u32) (data[1]) << 24;
	b43_ram_write(dev, ram_offset, tmp);
	ram_offset += sizeof(u32);
	for (i = 2; i < size; i += sizeof(u32)) {
		tmp = (u32) (data[i + 0]);
		if (i + 1 < size)
			tmp |= (u32) (data[i + 1]) << 8;
		if (i + 2 < size)
			tmp |= (u32) (data[i + 2]) << 16;
		if (i + 3 < size)
			tmp |= (u32) (data[i + 3]) << 24;
		b43_ram_write(dev, ram_offset + i - 2, tmp);
	}
	b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
			size + sizeof(struct b43_plcp_hdr6));
}

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/* Check if the use of the antenna that ieee80211 told us to
 * use is possible. This will fall back to DEFAULT.
 * "antenna_nr" is the antenna identifier we got from ieee80211. */
u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
				  u8 antenna_nr)
{
	u8 antenna_mask;

	if (antenna_nr == 0) {
		/* Zero means "use default antenna". That's always OK. */
		return 0;
	}

	/* Get the mask of available antennas. */
	if (dev->phy.gmode)
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		antenna_mask = dev->dev->bus_sprom->ant_available_bg;
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	else
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		antenna_mask = dev->dev->bus_sprom->ant_available_a;
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	if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
		/* This antenna is not available. Fall back to default. */
		return 0;
	}

	return antenna_nr;
}

/* Convert a b43 antenna number value to the PHY TX control value. */
static u16 b43_antenna_to_phyctl(int antenna)
{
	switch (antenna) {
	case B43_ANTENNA0:
		return B43_TXH_PHY_ANT0;
	case B43_ANTENNA1:
		return B43_TXH_PHY_ANT1;
	case B43_ANTENNA2:
		return B43_TXH_PHY_ANT2;
	case B43_ANTENNA3:
		return B43_TXH_PHY_ANT3;
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	case B43_ANTENNA_AUTO0:
	case B43_ANTENNA_AUTO1:
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		return B43_TXH_PHY_ANT01AUTO;
	}
	B43_WARN_ON(1);
	return 0;
}

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static void b43_write_beacon_template(struct b43_wldev *dev,
				      u16 ram_offset,
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				      u16 shm_size_offset)
1539
{
1540
	unsigned int i, len, variable_len;
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	const struct ieee80211_mgmt *bcn;
	const u8 *ie;
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	bool tim_found = false;
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	unsigned int rate;
	u16 ctl;
	int antenna;
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	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1548

1549
	bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
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	len = min_t(size_t, dev->wl->current_beacon->len,
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		  0x200 - sizeof(struct b43_plcp_hdr6));
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	rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
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	b43_write_template_common(dev, (const u8 *)bcn,
1555
				  len, ram_offset, shm_size_offset, rate);
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1557
	/* Write the PHY TX control parameters. */
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	antenna = B43_ANTENNA_DEFAULT;
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	antenna = b43_antenna_to_phyctl(antenna);
	ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
	/* We can't send beacons with short preamble. Would get PHY errors. */
	ctl &= ~B43_TXH_PHY_SHORTPRMBL;
	ctl &= ~B43_TXH_PHY_ANT;
	ctl &= ~B43_TXH_PHY_ENC;
	ctl |= antenna;
	if (b43_is_cck_rate(rate))
		ctl |= B43_TXH_PHY_ENC_CCK;
	else
		ctl |= B43_TXH_PHY_ENC_OFDM;
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);

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	/* Find the position of the TIM and the DTIM_period value
	 * and write them to SHM. */
	ie = bcn->u.beacon.variable;
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	variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
	for (i = 0; i < variable_len - 2; ) {
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		uint8_t ie_id, ie_len;

		ie_id = ie[i];
		ie_len = ie[i + 1];
		if (ie_id == 5) {
			u16 tim_position;
			u16 dtim_period;
			/* This is the TIM Information Element */

			/* Check whether the ie_len is in the beacon data range. */
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			if (variable_len < ie_len + 2 + i)
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				break;
			/* A valid TIM is at least 4 bytes long. */
			if (ie_len < 4)
				break;
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			tim_found = true;
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			tim_position = sizeof(struct b43_plcp_hdr6);
			tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
			tim_position += i;

			dtim_period = ie[i + 3];

			b43_shm_write16(dev, B43_SHM_SHARED,
					B43_SHM_SH_TIMBPOS, tim_position);
			b43_shm_write16(dev, B43_SHM_SHARED,
					B43_SHM_SH_DTIMPER, dtim_period);
			break;
		}
		i += ie_len + 2;
	}
	if (!tim_found) {
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		/*
		 * If ucode wants to modify TIM do it behind the beacon, this
		 * will happen, for example, when doing mesh networking.
		 */
		b43_shm_write16(dev, B43_SHM_SHARED,
				B43_SHM_SH_TIMBPOS,
				len + sizeof(struct b43_plcp_hdr6));
		b43_shm_write16(dev, B43_SHM_SHARED,
				B43_SHM_SH_DTIMPER, 0);
	}
	b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
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}

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static void b43_upload_beacon0(struct b43_wldev *dev)
{
	struct b43_wl *wl = dev->wl;

	if (wl->beacon0_uploaded)
		return;
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	b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
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	wl->beacon0_uploaded = true;
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}

static void b43_upload_beacon1(struct b43_wldev *dev)
{
	struct b43_wl *wl = dev->wl;

	if (wl->beacon1_uploaded)
		return;
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	b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
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	wl->beacon1_uploaded = true;
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}

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static void handle_irq_beacon(struct b43_wldev *dev)
{
	struct b43_wl *wl = dev->wl;
	u32 cmd, beacon0_valid, beacon1_valid;

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	if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
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	    !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
	    !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
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		return;

	/* This is the bottom half of the asynchronous beacon update. */

	/* Ignore interrupt in the future. */
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	dev->irq_mask &= ~B43_IRQ_BEACON;
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	cmd = b43_read32(dev, B43_MMIO_MACCMD);
	beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
	beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);

	/* Schedule interrupt manually, if busy. */
	if (beacon0_valid && beacon1_valid) {
		b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
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		dev->irq_mask |= B43_IRQ_BEACON;
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		return;
	}

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	if (unlikely(wl->beacon_templates_virgin)) {
		/* We never uploaded a beacon before.
		 * Upload both templates now, but only mark one valid. */
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		wl->beacon_templates_virgin = false;
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		b43_upload_beacon0(dev);
		b43_upload_beacon1(dev);
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		cmd = b43_read32(dev, B43_MMIO_MACCMD);
		cmd |= B43_MACCMD_BEACON0_VALID;
		b43_write32(dev, B43_MMIO_MACCMD, cmd);
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	} else {
		if (!beacon0_valid) {
			b43_upload_beacon0(dev);
			cmd = b43_read32(dev, B43_MMIO_MACCMD);
			cmd |= B43_MACCMD_BEACON0_VALID;
			b43_write32(dev, B43_MMIO_MACCMD, cmd);
		} else if (!beacon1_valid) {
			b43_upload_beacon1(dev);
			cmd = b43_read32(dev, B43_MMIO_MACCMD);
			cmd |= B43_MACCMD_BEACON1_VALID;
			b43_write32(dev, B43_MMIO_MACCMD, cmd);
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		}
	}
}

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static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
{
	u32 old_irq_mask = dev->irq_mask;

	/* update beacon right away or defer to irq */
	handle_irq_beacon(dev);
	if (old_irq_mask != dev->irq_mask) {
		/* The handler updated the IRQ mask. */
		B43_WARN_ON(!dev->irq_mask);
		if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
			b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
		} else {
			/* Device interrupts are currently disabled. That means
			 * we just ran the hardirq handler and scheduled the
			 * IRQ thread. The thread will write the IRQ mask when
			 * it finished, so there's nothing to do here. Writing
			 * the mask _here_ would incorrectly re-enable IRQs. */
		}
	}
}

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static void b43_beacon_update_trigger_work(struct work_struct *work)
{
	struct b43_wl *wl = container_of(work, struct b43_wl,
					 beacon_update_trigger);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
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		if (b43_bus_host_is_sdio(dev->dev)) {
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			/* wl->mutex is enough. */
			b43_do_beacon_update_trigger_work(dev);
			mmiowb();
		} else {
			spin_lock_irq(&wl->hardirq_lock);
			b43_do_beacon_update_trigger_work(dev);
			mmiowb();
			spin_unlock_irq(&wl->hardirq_lock);
		}
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	}
	mutex_unlock(&wl->mutex);
}

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/* Asynchronously update the packet templates in template RAM.
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 * Locking: Requires wl->mutex to be locked. */
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static void b43_update_templates(struct b43_wl *wl)
1739
{
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	struct sk_buff *beacon;

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	/* This is the top half of the ansynchronous beacon update.
	 * The bottom half is the beacon IRQ.
	 * Beacon update must be asynchronous to avoid sending an
	 * invalid beacon. This can happen for example, if the firmware
	 * transmits a beacon while we are updating it. */
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	/* We could modify the existing beacon and set the aid bit in
	 * the TIM field, but that would probably require resizing and
	 * moving of data within the beacon template.
	 * Simply request a new beacon and let mac80211 do the hard work. */
	beacon = ieee80211_beacon_get(wl->hw, wl->vif);
	if (unlikely(!beacon))
		return;

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	if (wl->current_beacon)
		dev_kfree_skb_any(wl->current_beacon);
	wl->current_beacon = beacon;
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	wl->beacon0_uploaded = false;
	wl->beacon1_uploaded = false;
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	ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
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}

static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
{
	b43_time_lock(dev);
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	if (dev->dev->core_rev >= 3) {
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		b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
		b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
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	} else {
		b43_write16(dev, 0x606, (beacon_int >> 6));
		b43_write16(dev, 0x610, beacon_int);
	}
	b43_time_unlock(dev);
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	b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
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}

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static void b43_handle_firmware_panic(struct b43_wldev *dev)
{
	u16 reason;

	/* Read the register that contains the reason code for the panic. */
	reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
	b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);

	switch (reason) {
	default:
		b43dbg(dev->wl, "The panic reason is unknown.\n");
		/* fallthrough */
	case B43_FWPANIC_DIE:
		/* Do not restart the controller or firmware.
		 * The device is nonfunctional from now on.
		 * Restarting would result in this panic to trigger again,
		 * so we avoid that recursion. */
		break;
	case B43_FWPANIC_RESTART:
		b43_controller_restart(dev, "Microcode panic");
		break;
	}
}

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static void handle_irq_ucode_debug(struct b43_wldev *dev)
{
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	unsigned int i, cnt;
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	u16 reason, marker_id, marker_line;
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	__le16 *buf;

	/* The proprietary firmware doesn't have this IRQ. */
	if (!dev->fw.opensource)
		return;

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	/* Read the register that contains the reason code for this IRQ. */
	reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);

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	switch (reason) {
	case B43_DEBUGIRQ_PANIC:
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		b43_handle_firmware_panic(dev);
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		break;
	case B43_DEBUGIRQ_DUMP_SHM:
		if (!B43_DEBUG)
			break; /* Only with driver debugging enabled. */
		buf = kmalloc(4096, GFP_ATOMIC);
		if (!buf) {
			b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
			goto out;
		}
		for (i = 0; i < 4096; i += 2) {
			u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
			buf[i / 2] = cpu_to_le16(tmp);
		}
		b43info(dev->wl, "Shared memory dump:\n");
		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
			       16, 2, buf, 4096, 1);
		kfree(buf);
		break;
	case B43_DEBUGIRQ_DUMP_REGS:
		if (!B43_DEBUG)
			break; /* Only with driver debugging enabled. */
		b43info(dev->wl, "Microcode register dump:\n");
		for (i = 0, cnt = 0; i < 64; i++) {
			u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
			if (cnt == 0)
				printk(KERN_INFO);
			printk("r%02u: 0x%04X  ", i, tmp);
			cnt++;
			if (cnt == 6) {
				printk("\n");
				cnt = 0;
			}
		}
		printk("\n");
		break;
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	case B43_DEBUGIRQ_MARKER:
		if (!B43_DEBUG)
			break; /* Only with driver debugging enabled. */
		marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
					   B43_MARKER_ID_REG);
		marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
					     B43_MARKER_LINE_REG);
		b43info(dev->wl, "The firmware just executed the MARKER(%u) "
			"at line number %u\n",
			marker_id, marker_line);
		break;
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	default:
		b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
		       reason);
	}
out:
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	/* Acknowledge the debug-IRQ, so the firmware can continue. */
	b43_shm_write16(dev, B43_SHM_SCRATCH,
			B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
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}

1874
static void b43_do_interrupt_thread(struct b43_wldev *dev)
1875 1876 1877 1878
{
	u32 reason;
	u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
	u32 merged_dma_reason = 0;
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	int i;
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	if (unlikely(b43_status(dev) != B43_STAT_STARTED))
		return;
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	reason = dev->irq_reason;
	for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
		dma_reason[i] = dev->dma_reason[i];
		merged_dma_reason |= dma_reason[i];
	}

	if (unlikely(reason & B43_IRQ_MAC_TXERR))
		b43err(dev->wl, "MAC transmission error\n");

1893
	if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1894
		b43err(dev->wl, "PHY transmission error\n");
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		rmb();
		if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
			atomic_set(&dev->phy.txerr_cnt,
				   B43_PHY_TX_BADNESS_LIMIT);
			b43err(dev->wl, "Too many PHY TX errors, "
					"restarting the controller\n");
			b43_controller_restart(dev, "PHY TX errors");
		}
	}
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	if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
		b43err(dev->wl,
			"Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
			dma_reason[0], dma_reason[1],
			dma_reason[2], dma_reason[3],
			dma_reason[4], dma_reason[5]);
		b43err(dev->wl, "This device does not support DMA "
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			       "on your system. It will now be switched to PIO.\n");
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		/* Fall back to PIO transfers if we get fatal DMA errors! */
		dev->use_pio = true;
		b43_controller_restart(dev, "DMA error");
		return;
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	}

	if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
		handle_irq_ucode_debug(dev);
	if (reason & B43_IRQ_TBTT_INDI)
		handle_irq_tbtt_indication(dev);
	if (reason & B43_IRQ_ATIM_END)
		handle_irq_atim_end(dev);
	if (reason & B43_IRQ_BEACON)
		handle_irq_beacon(dev);
	if (reason & B43_IRQ_PMQ)
		handle_irq_pmq(dev);
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	if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
		;/* TODO */
	if (reason & B43_IRQ_NOISESAMPLE_OK)
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		handle_irq_noise(dev);

	/* Check the DMA reason registers for received data. */
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	if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
		if (B43_DEBUG)
			b43warn(dev->wl, "RX descriptor underrun\n");
		b43_dma_handle_rx_overflow(dev->dma.rx_ring);
	}
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	if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
		if (b43_using_pio_transfers(dev))
			b43_pio_rx(dev->pio.rx_queue);
		else
			b43_dma_rx(dev->dma.rx_ring);
	}
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	B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
	B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
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	B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
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	B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
	B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);

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	if (reason & B43_IRQ_TX_OK)
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		handle_irq_transmit_status(dev);

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	/* Re-enable interrupts on the device by restoring the current interrupt mask. */
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	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
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#if B43_DEBUG
	if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
		dev->irq_count++;
		for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
			if (reason & (1 << i))
				dev->irq_bit_count[i]++;
		}
	}
#endif
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}

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/* Interrupt thread handler. Handles device interrupts in thread context. */
static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1971
{
1972
	struct b43_wldev *dev = dev_id;
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	mutex_lock(&dev->wl->mutex);
	b43_do_interrupt_thread(dev);
	mmiowb();
	mutex_unlock(&dev->wl->mutex);

	return IRQ_HANDLED;
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}

1982
static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1983 1984 1985
{
	u32 reason;

1986 1987
	/* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
	 * On SDIO, this runs under wl->mutex. */
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	reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
	if (reason == 0xffffffff)	/* shared IRQ */
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		return IRQ_NONE;
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	reason &= dev->irq_mask;
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	if (!reason)
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		return IRQ_NONE;
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	dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
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	    & 0x0001FC00;
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	dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
	    & 0x0000DC00;
	dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
	    & 0x0000DC00;
	dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
	    & 0x0001DC00;
	dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
	    & 0x0000DC00;
2006
/* Unused ring
2007 2008
	dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
	    & 0x0000DC00;
2009
*/
2010

2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
	/* ACK the interrupt. */
	b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
	b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
	b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
	b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
	b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
	b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
/* Unused ring
	b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
*/

	/* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2023
	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2024
	/* Save the reason bitmasks for the IRQ thread handler. */
2025
	dev->irq_reason = reason;
2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040

	return IRQ_WAKE_THREAD;
}

/* Interrupt handler top-half. This runs with interrupts disabled. */
static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
{
	struct b43_wldev *dev = dev_id;
	irqreturn_t ret;

	if (unlikely(b43_status(dev) < B43_STAT_STARTED))
		return IRQ_NONE;

	spin_lock(&dev->wl->hardirq_lock);
	ret = b43_do_interrupt(dev);
2041
	mmiowb();
2042
	spin_unlock(&dev->wl->hardirq_lock);
2043 2044 2045 2046

	return ret;
}

2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
/* SDIO interrupt handler. This runs in process context. */
static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
{
	struct b43_wl *wl = dev->wl;
	irqreturn_t ret;

	mutex_lock(&wl->mutex);

	ret = b43_do_interrupt(dev);
	if (ret == IRQ_WAKE_THREAD)
		b43_do_interrupt_thread(dev);

	mutex_unlock(&wl->mutex);
}

2062
void b43_do_release_fw(struct b43_firmware_file *fw)
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{
	release_firmware(fw->data);
	fw->data = NULL;
	fw->filename = NULL;
}

2069 2070
static void b43_release_firmware(struct b43_wldev *dev)
{
2071
	complete(&dev->fw_load_complete);
2072 2073 2074 2075
	b43_do_release_fw(&dev->fw.ucode);
	b43_do_release_fw(&dev->fw.pcm);
	b43_do_release_fw(&dev->fw.initvals);
	b43_do_release_fw(&dev->fw.initvals_band);
2076 2077
}

2078
static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2079
{
2080 2081 2082 2083 2084
	const char text[] =
		"You must go to " \
		"http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
		"and download the correct firmware for this driver version. " \
		"Please carefully read all instructions on this website.\n";
2085 2086 2087 2088 2089

	if (error)
		b43err(wl, text);
	else
		b43warn(wl, text);
2090 2091
}

2092 2093 2094 2095 2096
static void b43_fw_cb(const struct firmware *firmware, void *context)
{
	struct b43_request_fw_context *ctx = context;

	ctx->blob = firmware;
2097
	complete(&ctx->dev->fw_load_complete);
2098 2099
}

2100 2101
int b43_do_request_fw(struct b43_request_fw_context *ctx,
		      const char *name,
2102
		      struct b43_firmware_file *fw, bool async)
2103 2104 2105 2106 2107
{
	struct b43_fw_header *hdr;
	u32 size;
	int err;

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	if (!name) {
		/* Don't fetch anything. Free possibly cached firmware. */
2110 2111 2112
		/* FIXME: We should probably keep it anyway, to save some headache
		 * on suspend/resume with multiband devices. */
		b43_do_release_fw(fw);
2113
		return 0;
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	}
	if (fw->filename) {
2116 2117
		if ((fw->type == ctx->req_type) &&
		    (strcmp(fw->filename, name) == 0))
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			return 0; /* Already have this fw. */
		/* Free the cached firmware first. */
2120 2121 2122 2123 2124
		/* FIXME: We should probably do this later after we successfully
		 * got the new fw. This could reduce headache with multiband devices.
		 * We could also redesign this to cache the firmware for all possible
		 * bands all the time. */
		b43_do_release_fw(fw);
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2125
	}
2126

2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141
	switch (ctx->req_type) {
	case B43_FWTYPE_PROPRIETARY:
		snprintf(ctx->fwname, sizeof(ctx->fwname),
			 "b43%s/%s.fw",
			 modparam_fwpostfix, name);
		break;
	case B43_FWTYPE_OPENSOURCE:
		snprintf(ctx->fwname, sizeof(ctx->fwname),
			 "b43-open%s/%s.fw",
			 modparam_fwpostfix, name);
		break;
	default:
		B43_WARN_ON(1);
		return -ENOSYS;
	}
2142 2143
	if (async) {
		/* do this part asynchronously */
2144
		init_completion(&ctx->dev->fw_load_complete);
2145 2146 2147 2148 2149 2150 2151
		err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
					      ctx->dev->dev->dev, GFP_KERNEL,
					      ctx, b43_fw_cb);
		if (err < 0) {
			pr_err("Unable to load firmware\n");
			return err;
		}
2152
		wait_for_completion(&ctx->dev->fw_load_complete);
2153 2154 2155
		if (ctx->blob)
			goto fw_ready;
	/* On some ARM systems, the async request will fail, but the next sync
2156
	 * request works. For this reason, we fall through here
2157 2158 2159 2160
	 */
	}
	err = request_firmware(&ctx->blob, ctx->fwname,
			       ctx->dev->dev->dev);
2161
	if (err == -ENOENT) {
2162 2163
		snprintf(ctx->errors[ctx->req_type],
			 sizeof(ctx->errors[ctx->req_type]),
2164 2165
			 "Firmware file \"%s\" not found\n",
			 ctx->fwname);
2166 2167
		return err;
	} else if (err) {
2168 2169 2170 2171
		snprintf(ctx->errors[ctx->req_type],
			 sizeof(ctx->errors[ctx->req_type]),
			 "Firmware file \"%s\" request failed (err=%d)\n",
			 ctx->fwname, err);
2172 2173
		return err;
	}
2174 2175
fw_ready:
	if (ctx->blob->size < sizeof(struct b43_fw_header))
2176
		goto err_format;
2177
	hdr = (struct b43_fw_header *)(ctx->blob->data);
2178 2179 2180 2181
	switch (hdr->type) {
	case B43_FW_TYPE_UCODE:
	case B43_FW_TYPE_PCM:
		size = be32_to_cpu(hdr->size);
2182
		if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
			goto err_format;
		/* fallthrough */
	case B43_FW_TYPE_IV:
		if (hdr->ver != 1)
			goto err_format;
		break;
	default:
		goto err_format;
	}

2193
	fw->data = ctx->blob;
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2194
	fw->filename = name;
2195
	fw->type = ctx->req_type;
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	return 0;
2198 2199

err_format:
2200 2201 2202
	snprintf(ctx->errors[ctx->req_type],
		 sizeof(ctx->errors[ctx->req_type]),
		 "Firmware file \"%s\" format error.\n", ctx->fwname);
2203
	release_firmware(ctx->blob);
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2204

2205 2206 2207
	return -EPROTO;
}

2208
/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
2209
static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2210
{
2211 2212
	struct b43_wldev *dev = ctx->dev;
	struct b43_firmware *fw = &ctx->dev->fw;
2213
	struct b43_phy *phy = &dev->phy;
2214
	const u8 rev = ctx->dev->dev->core_rev;
2215 2216 2217
	const char *filename;
	int err;

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2218
	/* Get microcode */
2219 2220 2221 2222 2223 2224
	filename = NULL;
	switch (rev) {
	case 42:
		if (phy->type == B43_PHYTYPE_AC)
			filename = "ucode42";
		break;
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2225 2226 2227 2228
	case 40:
		if (phy->type == B43_PHYTYPE_AC)
			filename = "ucode40";
		break;
2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266
	case 33:
		if (phy->type == B43_PHYTYPE_LCN40)
			filename = "ucode33_lcn40";
		break;
	case 30:
		if (phy->type == B43_PHYTYPE_N)
			filename = "ucode30_mimo";
		break;
	case 29:
		if (phy->type == B43_PHYTYPE_HT)
			filename = "ucode29_mimo";
		break;
	case 26:
		if (phy->type == B43_PHYTYPE_HT)
			filename = "ucode26_mimo";
		break;
	case 28:
	case 25:
		if (phy->type == B43_PHYTYPE_N)
			filename = "ucode25_mimo";
		else if (phy->type == B43_PHYTYPE_LCN)
			filename = "ucode25_lcn";
		break;
	case 24:
		if (phy->type == B43_PHYTYPE_LCN)
			filename = "ucode24_lcn";
		break;
	case 23:
		if (phy->type == B43_PHYTYPE_N)
			filename = "ucode16_mimo";
		break;
	case 16 ... 19:
		if (phy->type == B43_PHYTYPE_N)
			filename = "ucode16_mimo";
		else if (phy->type == B43_PHYTYPE_LP)
			filename = "ucode16_lp";
		break;
	case 15:
2267
		filename = "ucode15";
2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280
		break;
	case 14:
		filename = "ucode14";
		break;
	case 13:
		filename = "ucode13";
		break;
	case 11 ... 12:
		filename = "ucode11";
		break;
	case 5 ... 10:
		filename = "ucode5";
		break;
2281
	}
2282 2283
	if (!filename)
		goto err_no_ucode;
2284
	err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
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	if (err)
		goto err_load;

	/* Get PCM code */
	if ((rev >= 5) && (rev <= 10))
		filename = "pcm5";
	else if (rev >= 11)
		filename = NULL;
	else
		goto err_no_pcm;
2295
	fw->pcm_request_failed = false;
2296
	err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2297 2298 2299
	if (err == -ENOENT) {
		/* We did not find a PCM file? Not fatal, but
		 * core rev <= 10 must do without hwcrypto then. */
2300
		fw->pcm_request_failed = true;
2301
	} else if (err)
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2302 2303 2304
		goto err_load;

	/* Get initvals */
2305
	filename = NULL;
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2306 2307
	switch (dev->phy.type) {
	case B43_PHYTYPE_G:
2308
		if (rev == 13)
2309
			filename = "b0g0initvals13";
2310 2311
		else if (rev >= 5 && rev <= 10)
			filename = "b0g0initvals5";
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		break;
	case B43_PHYTYPE_N:
2314 2315 2316 2317 2318 2319 2320 2321 2322
		if (rev == 30)
			filename = "n16initvals30";
		else if (rev == 28 || rev == 25)
			filename = "n0initvals25";
		else if (rev == 24)
			filename = "n0initvals24";
		else if (rev == 23)
			filename = "n0initvals16"; /* What about n0initvals22? */
		else if (rev >= 16 && rev <= 18)
2323
			filename = "n0initvals16";
2324
		else if (rev >= 11 && rev <= 12)
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			filename = "n0initvals11";
		break;
2327
	case B43_PHYTYPE_LP:
2328 2329 2330 2331
		if (rev >= 16 && rev <= 18)
			filename = "lp0initvals16";
		else if (rev == 15)
			filename = "lp0initvals15";
2332 2333
		else if (rev == 14)
			filename = "lp0initvals14";
2334 2335
		else if (rev == 13)
			filename = "lp0initvals13";
2336
		break;
2337 2338 2339
	case B43_PHYTYPE_HT:
		if (rev == 29)
			filename = "ht0initvals29";
2340 2341
		else if (rev == 26)
			filename = "ht0initvals26";
2342 2343 2344 2345 2346
		break;
	case B43_PHYTYPE_LCN:
		if (rev == 24)
			filename = "lcn0initvals24";
		break;
2347 2348 2349 2350 2351 2352 2353
	case B43_PHYTYPE_LCN40:
		if (rev == 33)
			filename = "lcn400initvals33";
		break;
	case B43_PHYTYPE_AC:
		if (rev == 42)
			filename = "ac1initvals42";
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2354 2355
		else if (rev == 40)
			filename = "ac0initvals40";
2356
		break;
2357
	}
2358 2359
	if (!filename)
		goto err_no_initvals;
2360
	err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
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2361 2362 2363 2364
	if (err)
		goto err_load;

	/* Get bandswitch initvals */
2365
	filename = NULL;
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2366 2367
	switch (dev->phy.type) {
	case B43_PHYTYPE_G:
2368 2369 2370
		if (rev == 13)
			filename = "b0g0bsinitvals13";
		else if (rev >= 5 && rev <= 10)
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2371 2372 2373
			filename = "b0g0bsinitvals5";
		break;
	case B43_PHYTYPE_N:
2374 2375 2376 2377 2378 2379 2380 2381 2382
		if (rev == 30)
			filename = "n16bsinitvals30";
		else if (rev == 28 || rev == 25)
			filename = "n0bsinitvals25";
		else if (rev == 24)
			filename = "n0bsinitvals24";
		else if (rev == 23)
			filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
		else if (rev >= 16 && rev <= 18)
2383
			filename = "n0bsinitvals16";
2384
		else if (rev >= 11 && rev <= 12)
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2385 2386
			filename = "n0bsinitvals11";
		break;
2387
	case B43_PHYTYPE_LP:
2388 2389 2390 2391
		if (rev >= 16 && rev <= 18)
			filename = "lp0bsinitvals16";
		else if (rev == 15)
			filename = "lp0bsinitvals15";
2392 2393
		else if (rev == 14)
			filename = "lp0bsinitvals14";
2394 2395
		else if (rev == 13)
			filename = "lp0bsinitvals13";
2396
		break;
2397 2398 2399
	case B43_PHYTYPE_HT:
		if (rev == 29)
			filename = "ht0bsinitvals29";
2400 2401
		else if (rev == 26)
			filename = "ht0bsinitvals26";
2402 2403 2404 2405 2406
		break;
	case B43_PHYTYPE_LCN:
		if (rev == 24)
			filename = "lcn0bsinitvals24";
		break;
2407 2408 2409 2410 2411 2412 2413
	case B43_PHYTYPE_LCN40:
		if (rev == 33)
			filename = "lcn400bsinitvals33";
		break;
	case B43_PHYTYPE_AC:
		if (rev == 42)
			filename = "ac1bsinitvals42";
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2414 2415
		else if (rev == 40)
			filename = "ac0bsinitvals40";
2416
		break;
2417
	}
2418 2419
	if (!filename)
		goto err_no_initvals;
2420
	err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
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2421 2422
	if (err)
		goto err_load;
2423

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2424 2425
	fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);

2426 2427 2428
	return 0;

err_no_ucode:
2429 2430 2431
	err = ctx->fatal_failure = -EOPNOTSUPP;
	b43err(dev->wl, "The driver does not know which firmware (ucode) "
	       "is required for your device (wl-core rev %u)\n", rev);
2432 2433 2434
	goto error;

err_no_pcm:
2435 2436 2437
	err = ctx->fatal_failure = -EOPNOTSUPP;
	b43err(dev->wl, "The driver does not know which firmware (PCM) "
	       "is required for your device (wl-core rev %u)\n", rev);
2438 2439 2440
	goto error;

err_no_initvals:
2441 2442 2443 2444 2445 2446 2447 2448 2449
	err = ctx->fatal_failure = -EOPNOTSUPP;
	b43err(dev->wl, "The driver does not know which firmware (initvals) "
	       "is required for your device (wl-core rev %u)\n", rev);
	goto error;

err_load:
	/* We failed to load this firmware image. The error message
	 * already is in ctx->errors. Return and let our caller decide
	 * what to do. */
2450 2451 2452 2453 2454 2455 2456
	goto error;

error:
	b43_release_firmware(dev);
	return err;
}

2457 2458
static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
static void b43_one_core_detach(struct b43_bus_dev *dev);
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2459
static int b43_rng_init(struct b43_wl *wl);
2460 2461

static void b43_request_firmware(struct work_struct *work)
2462
{
2463 2464 2465
	struct b43_wl *wl = container_of(work,
			    struct b43_wl, firmware_load);
	struct b43_wldev *dev = wl->current_dev;
2466 2467 2468 2469 2470 2471 2472
	struct b43_request_fw_context *ctx;
	unsigned int i;
	int err;
	const char *errmsg;

	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
2473
		return;
2474 2475 2476 2477 2478
	ctx->dev = dev;

	ctx->req_type = B43_FWTYPE_PROPRIETARY;
	err = b43_try_request_fw(ctx);
	if (!err)
2479 2480 2481
		goto start_ieee80211; /* Successfully loaded it. */
	/* Was fw version known? */
	if (ctx->fatal_failure)
2482 2483
		goto out;

2484
	/* proprietary fw not found, try open source */
2485 2486 2487
	ctx->req_type = B43_FWTYPE_OPENSOURCE;
	err = b43_try_request_fw(ctx);
	if (!err)
2488 2489
		goto start_ieee80211; /* Successfully loaded it. */
	if(ctx->fatal_failure)
2490 2491 2492 2493 2494 2495
		goto out;

	/* Could not find a usable firmware. Print the errors. */
	for (i = 0; i < B43_NR_FWTYPES; i++) {
		errmsg = ctx->errors[i];
		if (strlen(errmsg))
2496
			b43err(dev->wl, "%s", errmsg);
2497 2498
	}
	b43_print_fw_helptext(dev->wl, 1);
2499 2500 2501
	goto out;

start_ieee80211:
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2502 2503 2504 2505
	wl->hw->queues = B43_QOS_QUEUE_NUM;
	if (!modparam_qos || dev->fw.opensource)
		wl->hw->queues = 1;

2506 2507 2508
	err = ieee80211_register_hw(wl->hw);
	if (err)
		goto err_one_core_detach;
2509
	wl->hw_registred = true;
2510
	b43_leds_register(wl->current_dev);
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	/* Register HW RNG driver */
	b43_rng_init(wl);

2515 2516 2517 2518
	goto out;

err_one_core_detach:
	b43_one_core_detach(dev->dev);
2519 2520 2521 2522 2523

out:
	kfree(ctx);
}

2524 2525
static int b43_upload_microcode(struct b43_wldev *dev)
{
2526
	struct wiphy *wiphy = dev->wl->hw->wiphy;
2527 2528 2529 2530
	const size_t hdr_len = sizeof(struct b43_fw_header);
	const __be32 *data;
	unsigned int i, len;
	u16 fwrev, fwpatch, fwdate, fwtime;
2531
	u32 tmp, macctl;
2532 2533
	int err = 0;

2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544
	/* Jump the microcode PSM to offset 0 */
	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
	macctl |= B43_MACCTL_PSM_JMP0;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	/* Zero out all microcode PSM registers and shared memory. */
	for (i = 0; i < 64; i++)
		b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
	for (i = 0; i < 4096; i += 2)
		b43_shm_write16(dev, B43_SHM_SHARED, i, 0);

2545
	/* Upload Microcode. */
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2546 2547
	data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
	len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
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	b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
	for (i = 0; i < len; i++) {
		b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
		udelay(10);
	}

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2554
	if (dev->fw.pcm.data) {
2555
		/* Upload PCM data. */
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		data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
		len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
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		b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
		b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
		/* No need for autoinc bit in SHM_HW */
		b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
		for (i = 0; i < len; i++) {
			b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
			udelay(10);
		}
	}

	b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2569 2570

	/* Start the microcode PSM */
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	b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
		      B43_MACCTL_PSM_RUN);
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	/* Wait for the microcode to load and respond */
	i = 0;
	while (1) {
		tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
		if (tmp == B43_IRQ_MAC_SUSPENDED)
			break;
		i++;
2581
		if (i >= 20) {
2582
			b43err(dev->wl, "Microcode not responding\n");
2583
			b43_print_fw_helptext(dev->wl, 1);
2584
			err = -ENODEV;
2585 2586
			goto error;
		}
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		msleep(50);
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	}
	b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);	/* dummy read */

	/* Get and check the revisions. */
	fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
	fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
	fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
	fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);

	if (fwrev <= 0x128) {
		b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
		       "binary drivers older than version 4.x is unsupported. "
		       "You must upgrade your firmware files.\n");
2601
		b43_print_fw_helptext(dev->wl, 1);
2602
		err = -EOPNOTSUPP;
2603
		goto error;
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	}
	dev->fw.rev = fwrev;
	dev->fw.patch = fwpatch;
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	if (dev->fw.rev >= 598)
		dev->fw.hdr_format = B43_FW_HDR_598;
	else if (dev->fw.rev >= 410)
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		dev->fw.hdr_format = B43_FW_HDR_410;
	else
		dev->fw.hdr_format = B43_FW_HDR_351;
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	WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2614

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	dev->qos_enabled = dev->wl->hw->queues > 1;
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2616
	/* Default to firmware/hardware crypto acceleration. */
2617
	dev->hwcrypto_enabled = true;
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2618

2619
	if (dev->fw.opensource) {
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		u16 fwcapa;

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		/* Patchlevel info is encoded in the "time" field. */
		dev->fw.patch = fwtime;
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		b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
			dev->fw.rev, dev->fw.patch);

		fwcapa = b43_fwcapa_read(dev);
		if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
			b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
			/* Disable hardware crypto and fall back to software crypto. */
2631
			dev->hwcrypto_enabled = false;
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2632
		}
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2633 2634
		/* adding QoS support should use an offline discovery mechanism */
		WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
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	} else {
		b43info(dev->wl, "Loading firmware version %u.%u "
			"(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
			fwrev, fwpatch,
			(fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
			(fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
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		if (dev->fw.pcm_request_failed) {
			b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
				"Hardware accelerated cryptography is disabled.\n");
			b43_print_fw_helptext(dev->wl, 0);
		}
2646
	}
2647

2648 2649
	snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
			dev->fw.rev, dev->fw.patch);
2650
	wiphy->hw_version = dev->dev->core_id;
2651

2652
	if (dev->fw.hdr_format == B43_FW_HDR_351) {
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		/* We're over the deadline, but we keep support for old fw
		 * until it turns out to be in major conflict with something new. */
2655
		b43warn(dev->wl, "You are using an old firmware image. "
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			"Support for old firmware will be removed soon "
			"(official deadline was July 2008).\n");
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		b43_print_fw_helptext(dev->wl, 0);
	}

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	return 0;

error:
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	/* Stop the microcode PSM. */
	b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
		      B43_MACCTL_PSM_JMP0);
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	return err;
}

static int b43_write_initvals(struct b43_wldev *dev,
			      const struct b43_iv *ivals,
			      size_t count,
			      size_t array_size)
{
	const struct b43_iv *iv;
	u16 offset;
	size_t i;
	bool bit32;

	BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
	iv = ivals;
	for (i = 0; i < count; i++) {
		if (array_size < sizeof(iv->offset_size))
			goto err_format;
		array_size -= sizeof(iv->offset_size);
		offset = be16_to_cpu(iv->offset_size);
		bit32 = !!(offset & B43_IV_32BIT);
		offset &= B43_IV_OFFSET_MASK;
		if (offset >= 0x1000)
			goto err_format;
		if (bit32) {
			u32 value;

			if (array_size < sizeof(iv->data.d32))
				goto err_format;
			array_size -= sizeof(iv->data.d32);

2699
			value = get_unaligned_be32(&iv->data.d32);
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			b43_write32(dev, offset, value);

			iv = (const struct b43_iv *)((const uint8_t *)iv +
							sizeof(__be16) +
							sizeof(__be32));
		} else {
			u16 value;

			if (array_size < sizeof(iv->data.d16))
				goto err_format;
			array_size -= sizeof(iv->data.d16);

			value = be16_to_cpu(iv->data.d16);
			b43_write16(dev, offset, value);

			iv = (const struct b43_iv *)((const uint8_t *)iv +
							sizeof(__be16) +
							sizeof(__be16));
		}
	}
	if (array_size)
		goto err_format;

	return 0;

err_format:
	b43err(dev->wl, "Initial Values Firmware file-format error.\n");
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	b43_print_fw_helptext(dev->wl, 1);
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	return -EPROTO;
}

static int b43_upload_initvals(struct b43_wldev *dev)
{
	const size_t hdr_len = sizeof(struct b43_fw_header);
	const struct b43_fw_header *hdr;
	struct b43_firmware *fw = &dev->fw;
	const struct b43_iv *ivals;
	size_t count;

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	hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
	ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2742
	count = be32_to_cpu(hdr->size);
2743
	return b43_write_initvals(dev, ivals, count,
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				 fw->initvals.data->size - hdr_len);
2745
}
2746

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static int b43_upload_initvals_band(struct b43_wldev *dev)
{
	const size_t hdr_len = sizeof(struct b43_fw_header);
	const struct b43_fw_header *hdr;
	struct b43_firmware *fw = &dev->fw;
	const struct b43_iv *ivals;
	size_t count;

	if (!fw->initvals_band.data)
		return 0;

	hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
	ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
	count = be32_to_cpu(hdr->size);
	return b43_write_initvals(dev, ivals, count,
				  fw->initvals_band.data->size - hdr_len);
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}

/* Initialize the GPIOs
 * http://bcm-specs.sipsolutions.net/GPIO
 */
2768 2769

#ifdef CONFIG_B43_SSB
2770
static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2771
{
2772
	struct ssb_bus *bus = dev->dev->sdev->bus;
2773 2774 2775 2776 2777 2778 2779

#ifdef CONFIG_SSB_DRIVER_PCICORE
	return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
#else
	return bus->chipco.dev;
#endif
}
2780
#endif
2781

2782 2783
static int b43_gpio_init(struct b43_wldev *dev)
{
2784
#ifdef CONFIG_B43_SSB
2785
	struct ssb_device *gpiodev;
2786
#endif
2787 2788
	u32 mask, set;

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	b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
	b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2791 2792 2793

	mask = 0x0000001F;
	set = 0x0000000F;
2794
	if (dev->dev->chip_id == 0x4301) {
2795 2796
		mask |= 0x0060;
		set |= 0x0060;
2797 2798 2799
	} else if (dev->dev->chip_id == 0x5354) {
		/* Don't allow overtaking buttons GPIOs */
		set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2800
	}
2801

2802 2803 2804 2805
	if (0 /* FIXME: conditional unknown */ ) {
		b43_write16(dev, B43_MMIO_GPIO_MASK,
			    b43_read16(dev, B43_MMIO_GPIO_MASK)
			    | 0x0100);
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		/* BT Coexistance Input */
		mask |= 0x0080;
		set |= 0x0080;
		/* BT Coexistance Out */
		mask |= 0x0100;
		set |= 0x0100;
2812
	}
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	if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2814
		/* PA is controlled by gpio 9, let ucode handle it */
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		b43_write16(dev, B43_MMIO_GPIO_MASK,
			    b43_read16(dev, B43_MMIO_GPIO_MASK)
			    | 0x0200);
		mask |= 0x0200;
		set |= 0x0200;
	}

2822
	switch (dev->dev->bus_type) {
2823 2824
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
2825
		bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2826 2827
		break;
#endif
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#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		gpiodev = b43_ssb_gpio_dev(dev);
		if (gpiodev)
			ssb_write32(gpiodev, B43_GPIO_CONTROL,
				    (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2834
				    & ~mask) | set);
2835 2836 2837
		break;
#endif
	}
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	return 0;
}

/* Turn off all GPIO stuff. Call this on module unload, for example. */
static void b43_gpio_cleanup(struct b43_wldev *dev)
{
2845
#ifdef CONFIG_B43_SSB
2846
	struct ssb_device *gpiodev;
2847
#endif
2848

2849
	switch (dev->dev->bus_type) {
2850 2851
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
2852
		bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2853 2854
		break;
#endif
2855 2856 2857 2858 2859 2860 2861 2862
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		gpiodev = b43_ssb_gpio_dev(dev);
		if (gpiodev)
			ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
		break;
#endif
	}
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}

/* http://bcm-specs.sipsolutions.net/EnableMac */
2866
void b43_mac_enable(struct b43_wldev *dev)
2867
{
2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880
	if (b43_debug(dev, B43_DBG_FIRMWARE)) {
		u16 fwstate;

		fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
					 B43_SHM_SH_UCODESTAT);
		if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
		    (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
			b43err(dev->wl, "b43_mac_enable(): The firmware "
			       "should be suspended, but current state is %u\n",
			       fwstate);
		}
	}

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	dev->mac_suspended--;
	B43_WARN_ON(dev->mac_suspended < 0);
	if (dev->mac_suspended == 0) {
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		b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
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		b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
			    B43_IRQ_MAC_SUSPENDED);
		/* Commit writes */
		b43_read32(dev, B43_MMIO_MACCTL);
		b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
		b43_power_saving_ctl_bits(dev, 0);
	}
}

/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2895
void b43_mac_suspend(struct b43_wldev *dev)
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{
	int i;
	u32 tmp;

2900
	might_sleep();
2901
	B43_WARN_ON(dev->mac_suspended < 0);
2902

2903 2904
	if (dev->mac_suspended == 0) {
		b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
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		b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2906 2907
		/* force pci to flush the write */
		b43_read32(dev, B43_MMIO_MACCTL);
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		for (i = 35; i; i--) {
			tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
			if (tmp & B43_IRQ_MAC_SUSPENDED)
				goto out;
			udelay(10);
		}
		/* Hm, it seems this will take some time. Use msleep(). */
2915
		for (i = 40; i; i--) {
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			tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
			if (tmp & B43_IRQ_MAC_SUSPENDED)
				goto out;
2919
			msleep(1);
2920 2921 2922
		}
		b43err(dev->wl, "MAC suspend failed\n");
	}
2923
out:
2924 2925 2926
	dev->mac_suspended++;
}

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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
{
2930 2931 2932
	u32 tmp;

	switch (dev->dev->bus_type) {
2933 2934
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
2935
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2936 2937 2938 2939
		if (on)
			tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
		else
			tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2940
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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		break;
#endif
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#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		if (on)
			tmp |= B43_TMSLOW_MACPHYCLKEN;
		else
			tmp &= ~B43_TMSLOW_MACPHYCLKEN;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		break;
#endif
	}
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}

2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968
static void b43_adjust_opmode(struct b43_wldev *dev)
{
	struct b43_wl *wl = dev->wl;
	u32 ctl;
	u16 cfp_pretbtt;

	ctl = b43_read32(dev, B43_MMIO_MACCTL);
	/* Reset status to STA infrastructure mode. */
	ctl &= ~B43_MACCTL_AP;
	ctl &= ~B43_MACCTL_KEEP_CTL;
	ctl &= ~B43_MACCTL_KEEP_BADPLCP;
	ctl &= ~B43_MACCTL_KEEP_BAD;
	ctl &= ~B43_MACCTL_PROMISC;
2969
	ctl &= ~B43_MACCTL_BEACPROMISC;
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	ctl |= B43_MACCTL_INFRA;

2972 2973
	if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
	    b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2974
		ctl |= B43_MACCTL_AP;
2975
	else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2976 2977 2978
		ctl &= ~B43_MACCTL_INFRA;

	if (wl->filter_flags & FIF_CONTROL)
2979
		ctl |= B43_MACCTL_KEEP_CTL;
2980 2981 2982 2983 2984
	if (wl->filter_flags & FIF_FCSFAIL)
		ctl |= B43_MACCTL_KEEP_BAD;
	if (wl->filter_flags & FIF_PLCPFAIL)
		ctl |= B43_MACCTL_KEEP_BADPLCP;
	if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2985
		ctl |= B43_MACCTL_PROMISC;
2986 2987 2988
	if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
		ctl |= B43_MACCTL_BEACPROMISC;

2989 2990 2991
	/* Workaround: On old hardware the HW-MAC-address-filter
	 * doesn't work properly, so always run promisc in filter
	 * it in software. */
2992
	if (dev->dev->core_rev <= 4)
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		ctl |= B43_MACCTL_PROMISC;

	b43_write32(dev, B43_MMIO_MACCTL, ctl);

	cfp_pretbtt = 2;
	if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2999 3000
		if (dev->dev->chip_id == 0x4306 &&
		    dev->dev->chip_rev == 3)
3001 3002 3003 3004 3005
			cfp_pretbtt = 100;
		else
			cfp_pretbtt = 50;
	}
	b43_write16(dev, 0x612, cfp_pretbtt);
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	/* FIXME: We don't currently implement the PMQ mechanism,
	 *        so always disable it. If we want to implement PMQ,
	 *        we need to enable it here (clear DISCPMQ) in AP mode.
	 */
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	if (0  /* ctl & B43_MACCTL_AP */)
		b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
	else
		b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
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}

static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
{
	u16 offset;

	if (is_ofdm) {
		offset = 0x480;
		offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
	} else {
		offset = 0x4C0;
		offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
	}
	b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
			b43_shm_read16(dev, B43_SHM_SHARED, offset));
}

static void b43_rate_memory_init(struct b43_wldev *dev)
{
	switch (dev->phy.type) {
	case B43_PHYTYPE_A:
	case B43_PHYTYPE_G:
3037
	case B43_PHYTYPE_N:
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Gábor Stefanik committed
3038
	case B43_PHYTYPE_LP:
3039
	case B43_PHYTYPE_HT:
Rafał Miłecki's avatar
Rafał Miłecki committed
3040
	case B43_PHYTYPE_LCN:
3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061
		b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
		b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
		b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
		b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
		b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
		b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
		b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
		if (dev->phy.type == B43_PHYTYPE_A)
			break;
		/* fallthrough */
	case B43_PHYTYPE_B:
		b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
		b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
		b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
		b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
		break;
	default:
		B43_WARN_ON(1);
	}
}

3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075
/* Set the default values for the PHY TX Control Words. */
static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
{
	u16 ctl = 0;

	ctl |= B43_TXH_PHY_ENC_CCK;
	ctl |= B43_TXH_PHY_ANT01AUTO;
	ctl |= B43_TXH_PHY_TXPWR;

	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
}

3076 3077 3078
/* Set the TX-Antenna for management frames sent by firmware. */
static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
{
3079
	u16 ant;
3080 3081
	u16 tmp;

3082
	ant = b43_antenna_to_phyctl(antenna);
3083 3084 3085

	/* For ACK/CTS */
	tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3086
	tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3087 3088 3089
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
	/* For Probe Resposes */
	tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3090
	tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3091 3092 3093 3094 3095 3096
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
}

/* This is the opposite of b43_chip_init() */
static void b43_chip_exit(struct b43_wldev *dev)
{
3097
	b43_phy_exit(dev);
3098 3099 3100 3101 3102 3103 3104 3105 3106 3107
	b43_gpio_cleanup(dev);
	/* firmware is released later */
}

/* Initialize the chip
 * http://bcm-specs.sipsolutions.net/ChipInit
 */
static int b43_chip_init(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
3108
	int err;
3109
	u32 macctl;
3110 3111
	u16 value16;

3112 3113 3114 3115 3116 3117
	/* Initialize the MAC control */
	macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
	if (dev->phy.gmode)
		macctl |= B43_MACCTL_GMODE;
	macctl |= B43_MACCTL_INFRA;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
3118 3119 3120 3121 3122 3123 3124 3125

	err = b43_upload_microcode(dev);
	if (err)
		goto out;	/* firmware is released later */

	err = b43_gpio_init(dev);
	if (err)
		goto out;	/* firmware is released later */
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3126

3127 3128
	err = b43_upload_initvals(dev);
	if (err)
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3129
		goto err_gpio_clean;
3130

3131 3132 3133 3134
	err = b43_upload_initvals_band(dev);
	if (err)
		goto err_gpio_clean;

3135 3136
	/* Turn the Analog on and initialize the PHY. */
	phy->ops->switch_analog(dev, 1);
3137 3138
	err = b43_phy_init(dev);
	if (err)
3139
		goto err_gpio_clean;
3140

3141 3142 3143
	/* Disable Interference Mitigation. */
	if (phy->ops->interf_mitigation)
		phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3144

3145 3146 3147
	/* Select the antennae */
	if (phy->ops->set_rx_antenna)
		phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3148 3149 3150 3151 3152 3153 3154 3155
	b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);

	if (phy->type == B43_PHYTYPE_B) {
		value16 = b43_read16(dev, 0x005E);
		value16 |= 0x0004;
		b43_write16(dev, 0x005E, value16);
	}
	b43_write32(dev, 0x0100, 0x01000000);
3156
	if (dev->dev->core_rev < 5)
3157 3158
		b43_write32(dev, 0x010C, 0x01000000);

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3159 3160
	b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
	b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3161 3162 3163

	/* Probe Response Timeout value */
	/* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
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Hauke Mehrtens committed
3164
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3165 3166 3167 3168

	/* Initially set the wireless operation mode. */
	b43_adjust_opmode(dev);

3169
	if (dev->dev->core_rev < 3) {
3170 3171 3172 3173 3174 3175 3176 3177 3178
		b43_write16(dev, 0x060E, 0x0000);
		b43_write16(dev, 0x0610, 0x8000);
		b43_write16(dev, 0x0604, 0x0000);
		b43_write16(dev, 0x0606, 0x0200);
	} else {
		b43_write32(dev, 0x0188, 0x80000000);
		b43_write32(dev, 0x018C, 0x02000000);
	}
	b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3179
	b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3180 3181 3182 3183 3184 3185
	b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
	b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
	b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
	b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
	b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);

3186
	b43_mac_phy_clock_set(dev, true);
3187

3188
	switch (dev->dev->bus_type) {
3189 3190 3191 3192 3193 3194
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		/* FIXME: 0xE74 is quite common, but should be read from CC */
		b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
		break;
#endif
3195 3196 3197 3198 3199 3200 3201
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		b43_write16(dev, B43_MMIO_POWERUP_DELAY,
			    dev->dev->sdev->bus->chipco.fast_pwrup_delay);
		break;
#endif
	}
3202 3203 3204

	err = 0;
	b43dbg(dev->wl, "Chip initialized\n");
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3205
out:
3206 3207
	return err;

Larry Finger's avatar
Larry Finger committed
3208
err_gpio_clean:
3209
	b43_gpio_cleanup(dev);
Michael Buesch's avatar
Michael Buesch committed
3210
	return err;
3211 3212 3213 3214
}

static void b43_periodic_every60sec(struct b43_wldev *dev)
{
3215
	const struct b43_phy_operations *ops = dev->phy.ops;
3216

3217 3218
	if (ops->pwork_60sec)
		ops->pwork_60sec(dev);
3219 3220 3221

	/* Force check the TX power emission now. */
	b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232
}

static void b43_periodic_every30sec(struct b43_wldev *dev)
{
	/* Update device statistics. */
	b43_calculate_link_quality(dev);
}

static void b43_periodic_every15sec(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247
	u16 wdr;

	if (dev->fw.opensource) {
		/* Check if the firmware is still alive.
		 * It will reset the watchdog counter to 0 in its idle loop. */
		wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
		if (unlikely(wdr)) {
			b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
			b43_controller_restart(dev, "Firmware watchdog");
			return;
		} else {
			b43_shm_write16(dev, B43_SHM_SCRATCH,
					B43_WATCHDOG_REG, 1);
		}
	}
3248

3249 3250 3251
	if (phy->ops->pwork_15sec)
		phy->ops->pwork_15sec(dev);

3252 3253
	atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
	wmb();
3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274

#if B43_DEBUG
	if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
		unsigned int i;

		b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
		       dev->irq_count / 15,
		       dev->tx_count / 15,
		       dev->rx_count / 15);
		dev->irq_count = 0;
		dev->tx_count = 0;
		dev->rx_count = 0;
		for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
			if (dev->irq_bit_count[i]) {
				b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
				       dev->irq_bit_count[i] / 15, i, (1 << i));
				dev->irq_bit_count[i] = 0;
			}
		}
	}
#endif
3275 3276 3277 3278 3279 3280 3281
}

static void do_periodic_work(struct b43_wldev *dev)
{
	unsigned int state;

	state = dev->periodic_state;
3282
	if (state % 4 == 0)
3283
		b43_periodic_every60sec(dev);
3284
	if (state % 2 == 0)
3285
		b43_periodic_every30sec(dev);
3286
	b43_periodic_every15sec(dev);
3287 3288
}

3289 3290 3291
/* Periodic work locking policy:
 * 	The whole periodic work handler is protected by
 * 	wl->mutex. If another lock is needed somewhere in the
3292
 * 	pwork callchain, it's acquired in-place, where it's needed.
3293 3294 3295
 */
static void b43_periodic_work_handler(struct work_struct *work)
{
3296 3297 3298 3299
	struct b43_wldev *dev = container_of(work, struct b43_wldev,
					     periodic_work.work);
	struct b43_wl *wl = dev->wl;
	unsigned long delay;
3300

3301
	mutex_lock(&wl->mutex);
3302 3303 3304 3305 3306 3307

	if (unlikely(b43_status(dev) != B43_STAT_STARTED))
		goto out;
	if (b43_debug(dev, B43_DBG_PWORK_STOP))
		goto out_requeue;

3308
	do_periodic_work(dev);
3309 3310

	dev->periodic_state++;
3311
out_requeue:
3312 3313 3314
	if (b43_debug(dev, B43_DBG_PWORK_FAST))
		delay = msecs_to_jiffies(50);
	else
3315
		delay = round_jiffies_relative(HZ * 15);
3316
	ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3317
out:
3318
	mutex_unlock(&wl->mutex);
3319 3320 3321 3322 3323 3324 3325 3326
}

static void b43_periodic_tasks_setup(struct b43_wldev *dev)
{
	struct delayed_work *work = &dev->periodic_work;

	dev->periodic_state = 0;
	INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3327
	ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3328 3329
}

3330
/* Check if communication with the device works correctly. */
3331 3332
static int b43_validate_chipaccess(struct b43_wldev *dev)
{
3333
	u32 v, backup0, backup4;
3334

3335 3336
	backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
	backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3337 3338

	/* Check for read/write and endianness problems. */
3339 3340 3341
	b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
	if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
		goto error;
3342 3343
	b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
	if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3344 3345
		goto error;

3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362
	/* Check if unaligned 32bit SHM_SHARED access works properly.
	 * However, don't bail out on failure, because it's noncritical. */
	b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
	b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
	b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
	b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
	if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
		b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
	b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
	if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
	    b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
	    b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
	    b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
		b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");

	b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
	b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3363

3364
	if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378
		/* The 32bit register shadows the two 16bit registers
		 * with update sideeffects. Validate this. */
		b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
		b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
		if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
			goto error;
		if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
			goto error;
	}
	b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);

	v = b43_read32(dev, B43_MMIO_MACCTL);
	v |= B43_MACCTL_GMODE;
	if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3379 3380 3381
		goto error;

	return 0;
3382
error:
3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393
	b43err(dev->wl, "Failed to validate the chipaccess\n");
	return -ENODEV;
}

static void b43_security_init(struct b43_wldev *dev)
{
	dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
	/* KTP is a word address, but we address SHM bytewise.
	 * So multiply by two.
	 */
	dev->ktp *= 2;
3394 3395 3396
	/* Number of RCMTA address slots */
	b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
	/* Clear the key memory. */
3397 3398 3399
	b43_clear_keys(dev);
}

3400
#ifdef CONFIG_B43_HWRNG
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John Daiker committed
3401
static int b43_rng_read(struct hwrng *rng, u32 *data)
3402 3403
{
	struct b43_wl *wl = (struct b43_wl *)rng->priv;
3404 3405
	struct b43_wldev *dev;
	int count = -ENODEV;
3406

3407 3408 3409 3410 3411 3412 3413
	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
		*data = b43_read16(dev, B43_MMIO_RNG);
		count = sizeof(u16);
	}
	mutex_unlock(&wl->mutex);
3414

3415
	return count;
3416
}
3417
#endif /* CONFIG_B43_HWRNG */
3418

3419
static void b43_rng_exit(struct b43_wl *wl)
3420
{
3421
#ifdef CONFIG_B43_HWRNG
3422
	if (wl->rng_initialized)
3423
		hwrng_unregister(&wl->rng);
3424
#endif /* CONFIG_B43_HWRNG */
3425 3426 3427 3428
}

static int b43_rng_init(struct b43_wl *wl)
{
3429
	int err = 0;
3430

3431
#ifdef CONFIG_B43_HWRNG
3432 3433 3434 3435 3436
	snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
		 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
	wl->rng.name = wl->rng_name;
	wl->rng.data_read = b43_rng_read;
	wl->rng.priv = (unsigned long)wl;
3437
	wl->rng_initialized = true;
3438 3439
	err = hwrng_register(&wl->rng);
	if (err) {
3440
		wl->rng_initialized = false;
3441 3442 3443
		b43err(wl, "Failed to register the random "
		       "number generator (%d)\n", err);
	}
3444
#endif /* CONFIG_B43_HWRNG */
3445 3446 3447 3448

	return err;
}

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3449
static void b43_tx_work(struct work_struct *work)
3450
{
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Michael Buesch committed
3451 3452 3453
	struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
	struct b43_wldev *dev;
	struct sk_buff *skb;
3454
	int queue_num;
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3455
	int err = 0;
3456

Michael Buesch's avatar
Michael Buesch committed
3457 3458 3459 3460 3461
	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
		mutex_unlock(&wl->mutex);
		return;
3462
	}
3463

3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477
	for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
		while (skb_queue_len(&wl->tx_queue[queue_num])) {
			skb = skb_dequeue(&wl->tx_queue[queue_num]);
			if (b43_using_pio_transfers(dev))
				err = b43_pio_tx(dev, skb);
			else
				err = b43_dma_tx(dev, skb);
			if (err == -ENOSPC) {
				wl->tx_queue_stopped[queue_num] = 1;
				ieee80211_stop_queue(wl->hw, queue_num);
				skb_queue_head(&wl->tx_queue[queue_num], skb);
				break;
			}
			if (unlikely(err))
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Felix Fietkau committed
3478
				ieee80211_free_txskb(wl->hw, skb);
3479 3480
			err = 0;
		}
3481

3482 3483
		if (!err)
			wl->tx_queue_stopped[queue_num] = 0;
3484 3485
	}

3486 3487 3488
#if B43_DEBUG
	dev->tx_count++;
#endif
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3489 3490
	mutex_unlock(&wl->mutex);
}
3491

3492
static void b43_op_tx(struct ieee80211_hw *hw,
3493 3494
		      struct ieee80211_tx_control *control,
		      struct sk_buff *skb)
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3495 3496 3497 3498 3499
{
	struct b43_wl *wl = hw_to_b43_wl(hw);

	if (unlikely(skb->len < 2 + 2 + 6)) {
		/* Too short, this can't be a valid frame. */
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Felix Fietkau committed
3500
		ieee80211_free_txskb(hw, skb);
3501
		return;
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3502 3503 3504
	}
	B43_WARN_ON(skb_shinfo(skb)->nr_frags);

3505 3506 3507 3508 3509 3510
	skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
	if (!wl->tx_queue_stopped[skb->queue_mapping]) {
		ieee80211_queue_work(wl->hw, &wl->tx_work);
	} else {
		ieee80211_stop_queue(wl->hw, skb->queue_mapping);
	}
3511 3512
}

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3513 3514 3515 3516 3517
static void b43_qos_params_upload(struct b43_wldev *dev,
				  const struct ieee80211_tx_queue_params *p,
				  u16 shm_offset)
{
	u16 params[B43_NR_QOSPARAMS];
3518
	int bslots, tmp;
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	unsigned int i;

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	if (!dev->qos_enabled)
		return;

3524
	bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
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	memset(&params, 0, sizeof(params));

	params[B43_QOSPARAM_TXOP] = p->txop * 32;
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	params[B43_QOSPARAM_CWMIN] = p->cw_min;
	params[B43_QOSPARAM_CWMAX] = p->cw_max;
	params[B43_QOSPARAM_CWCUR] = p->cw_min;
	params[B43_QOSPARAM_AIFS] = p->aifs;
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3533
	params[B43_QOSPARAM_BSLOTS] = bslots;
3534
	params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
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	for (i = 0; i < ARRAY_SIZE(params); i++) {
		if (i == B43_QOSPARAM_STATUS) {
			tmp = b43_shm_read16(dev, B43_SHM_SHARED,
					     shm_offset + (i * 2));
			/* Mark the parameters as updated. */
			tmp |= 0x100;
			b43_shm_write16(dev, B43_SHM_SHARED,
					shm_offset + (i * 2),
					tmp);
		} else {
			b43_shm_write16(dev, B43_SHM_SHARED,
					shm_offset + (i * 2),
					params[i]);
		}
	}
}

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/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
static const u16 b43_qos_shm_offsets[] = {
	/* [mac80211-queue-nr] = SHM_OFFSET, */
	[0] = B43_QOS_VOICE,
	[1] = B43_QOS_VIDEO,
	[2] = B43_QOS_BESTEFFORT,
	[3] = B43_QOS_BACKGROUND,
};

3562 3563
/* Update all QOS parameters in hardware. */
static void b43_qos_upload_all(struct b43_wldev *dev)
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{
	struct b43_wl *wl = dev->wl;
	struct b43_qos_params *params;
	unsigned int i;

3569 3570 3571
	if (!dev->qos_enabled)
		return;

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3572 3573
	BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
		     ARRAY_SIZE(wl->qos_params));
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3574 3575 3576 3577

	b43_mac_suspend(dev);
	for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
		params = &(wl->qos_params[i]);
3578 3579
		b43_qos_params_upload(dev, &(params->p),
				      b43_qos_shm_offsets[i]);
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	}
	b43_mac_enable(dev);
}

static void b43_qos_clear(struct b43_wl *wl)
{
	struct b43_qos_params *params;
	unsigned int i;

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	/* Initialize QoS parameters to sane defaults. */

	BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
		     ARRAY_SIZE(wl->qos_params));

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	for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
		params = &(wl->qos_params[i]);

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		switch (b43_qos_shm_offsets[i]) {
		case B43_QOS_VOICE:
			params->p.txop = 0;
			params->p.aifs = 2;
			params->p.cw_min = 0x0001;
			params->p.cw_max = 0x0001;
			break;
		case B43_QOS_VIDEO:
			params->p.txop = 0;
			params->p.aifs = 2;
			params->p.cw_min = 0x0001;
			params->p.cw_max = 0x0001;
			break;
		case B43_QOS_BESTEFFORT:
			params->p.txop = 0;
			params->p.aifs = 3;
			params->p.cw_min = 0x0001;
			params->p.cw_max = 0x03FF;
			break;
		case B43_QOS_BACKGROUND:
			params->p.txop = 0;
			params->p.aifs = 7;
			params->p.cw_min = 0x0001;
			params->p.cw_max = 0x03FF;
			break;
		default:
			B43_WARN_ON(1);
		}
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	}
}

/* Initialize the core's QOS capabilities */
static void b43_qos_init(struct b43_wldev *dev)
{
3631 3632 3633 3634 3635 3636 3637 3638 3639 3640
	if (!dev->qos_enabled) {
		/* Disable QOS support. */
		b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
		b43_write16(dev, B43_MMIO_IFSCTL,
			    b43_read16(dev, B43_MMIO_IFSCTL)
			    & ~B43_MMIO_IFSCTL_USE_EDCF);
		b43dbg(dev->wl, "QoS disabled\n");
		return;
	}

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3641
	/* Upload the current QOS parameters. */
3642
	b43_qos_upload_all(dev);
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	/* Enable QOS support. */
	b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
	b43_write16(dev, B43_MMIO_IFSCTL,
		    b43_read16(dev, B43_MMIO_IFSCTL)
		    | B43_MMIO_IFSCTL_USE_EDCF);
3649
	b43dbg(dev->wl, "QoS enabled\n");
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}

3652 3653
static int b43_op_conf_tx(struct ieee80211_hw *hw,
			  struct ieee80211_vif *vif, u16 _queue,
3654
			  const struct ieee80211_tx_queue_params *params)
3655
{
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3656
	struct b43_wl *wl = hw_to_b43_wl(hw);
3657
	struct b43_wldev *dev;
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3658
	unsigned int queue = (unsigned int)_queue;
3659
	int err = -ENODEV;
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	if (queue >= ARRAY_SIZE(wl->qos_params)) {
		/* Queue not available or don't support setting
		 * params on this queue. Return success to not
		 * confuse mac80211. */
		return 0;
	}
3667 3668
	BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
		     ARRAY_SIZE(wl->qos_params));
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3669

3670 3671 3672 3673
	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
		goto out_unlock;
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3675 3676 3677 3678 3679 3680
	memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
	b43_mac_suspend(dev);
	b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
			      b43_qos_shm_offsets[queue]);
	b43_mac_enable(dev);
	err = 0;
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3682 3683 3684 3685
out_unlock:
	mutex_unlock(&wl->mutex);

	return err;
3686 3687
}

3688 3689
static int b43_op_get_stats(struct ieee80211_hw *hw,
			    struct ieee80211_low_level_stats *stats)
3690 3691 3692
{
	struct b43_wl *wl = hw_to_b43_wl(hw);

3693
	mutex_lock(&wl->mutex);
3694
	memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3695
	mutex_unlock(&wl->mutex);
3696 3697 3698 3699

	return 0;
}

3700
static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
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{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;
	u64 tsf;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;

	if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
		b43_tsf_read(dev, &tsf);
	else
		tsf = 0;

	mutex_unlock(&wl->mutex);

	return tsf;
}

3719 3720
static void b43_op_set_tsf(struct ieee80211_hw *hw,
			   struct ieee80211_vif *vif, u64 tsf)
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{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;

	if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
		b43_tsf_write(dev, tsf);

	mutex_unlock(&wl->mutex);
}

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3734
static const char *band_to_string(enum ieee80211_band band)
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{
	switch (band) {
	case IEEE80211_BAND_5GHZ:
		return "5";
	case IEEE80211_BAND_2GHZ:
		return "2.4";
	default:
		break;
	}
	B43_WARN_ON(1);
	return "";
}

3748
/* Expects wl->mutex locked */
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3749 3750
static int b43_switch_band(struct b43_wldev *dev,
			   struct ieee80211_channel *chan)
3751
{
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	struct b43_phy *phy = &dev->phy;
	bool gmode;
	u32 tmp;
3755

3756 3757
	switch (chan->band) {
	case IEEE80211_BAND_5GHZ:
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		gmode = false;
3759 3760
		break;
	case IEEE80211_BAND_2GHZ:
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		gmode = true;
3762 3763 3764 3765
		break;
	default:
		B43_WARN_ON(1);
		return -EINVAL;
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	}
3767

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	if (!((gmode && phy->supports_2ghz) ||
	      (!gmode && phy->supports_5ghz))) {
		b43err(dev->wl, "This device doesn't support %s-GHz band\n",
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3771 3772
		       band_to_string(chan->band));
		return -ENODEV;
3773
	}
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	if (!!phy->gmode == !!gmode) {
3776 3777 3778
		/* This device is already running. */
		return 0;
	}
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	b43dbg(dev->wl, "Switching to %s GHz band\n",
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	       band_to_string(chan->band));
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3782

3783 3784 3785
	/* Some new devices don't need disabling radio for band switching */
	if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
		b43_software_rfkill(dev, true);
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	phy->gmode = gmode;
	b43_phy_put_into_reset(dev);
	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		if (gmode)
			tmp |= B43_BCMA_IOCTL_GMODE;
		else
			tmp &= ~B43_BCMA_IOCTL_GMODE;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		if (gmode)
			tmp |= B43_TMSLOW_GMODE;
		else
			tmp &= ~B43_TMSLOW_GMODE;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		break;
#endif
3810
	}
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3811
	b43_phy_take_out_of_reset(dev);
3812

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	b43_upload_initvals_band(dev);

	b43_phy_init(dev);
3816 3817 3818 3819

	return 0;
}

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/* Write the short and long frame retry limit values. */
static void b43_set_retry_limits(struct b43_wldev *dev,
				 unsigned int short_retry,
				 unsigned int long_retry)
{
	/* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
	 * the chip-internal counter. */
	short_retry = min(short_retry, (unsigned int)0xF);
	long_retry = min(long_retry, (unsigned int)0xF);

	b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
			short_retry);
	b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
			long_retry);
}

3836
static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3837 3838
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
3839 3840
	struct b43_wldev *dev = wl->current_dev;
	struct b43_phy *phy = &dev->phy;
3841
	struct ieee80211_conf *conf = &hw->conf;
3842
	int antenna;
3843 3844 3845
	int err = 0;

	mutex_lock(&wl->mutex);
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	b43_mac_suspend(dev);

3848
	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3849
		phy->chandef = &conf->chandef;
3850
		phy->channel = conf->chandef.chan->hw_value;
3851

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		/* Switch the band (if necessary). */
		err = b43_switch_band(dev, conf->chandef.chan);
		if (err)
			goto out_mac_enable;

		/* Switch to the requested channel.
		 * The firmware takes care of races with the TX handler.
		 */
3860
		b43_switch_channel(dev, phy->channel);
3861
	}
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3863 3864 3865 3866 3867
	if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
		b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
					  conf->long_frame_max_tx_count);
	changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
	if (!changed)
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		goto out_mac_enable;
3869

3870
	dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3871

3872 3873
	/* Adjust the desired TX power level. */
	if (conf->power_level != 0) {
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		if (conf->power_level != phy->desired_txpower) {
			phy->desired_txpower = conf->power_level;
			b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
						   B43_TXPWR_IGNORE_TSSI);
3878 3879 3880 3881
		}
	}

	/* Antennas for RX and management frame TX. */
3882
	antenna = B43_ANTENNA_DEFAULT;
3883
	b43_mgmtframe_txantenna(dev, antenna);
3884
	antenna = B43_ANTENNA_DEFAULT;
3885 3886
	if (phy->ops->set_rx_antenna)
		phy->ops->set_rx_antenna(dev, antenna);
3887

3888 3889
	if (wl->radio_enabled != phy->radio_on) {
		if (wl->radio_enabled) {
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3890
			b43_software_rfkill(dev, false);
3891 3892 3893 3894 3895 3896 3897
			b43info(dev->wl, "Radio turned on by software\n");
			if (!dev->radio_hw_enable) {
				b43info(dev->wl, "The hardware RF-kill button "
					"still turns the radio physically off. "
					"Press the button to turn it on.\n");
			}
		} else {
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			b43_software_rfkill(dev, true);
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			b43info(dev->wl, "Radio turned off by software\n");
		}
	}

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out_mac_enable:
	b43_mac_enable(dev);
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	mutex_unlock(&wl->mutex);

	return err;
}

3910
static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
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{
	struct ieee80211_supported_band *sband =
		dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
	struct ieee80211_rate *rate;
	int i;
	u16 basic, direct, offset, basic_offset, rateptr;

	for (i = 0; i < sband->n_bitrates; i++) {
		rate = &sband->bitrates[i];

		if (b43_is_cck_rate(rate->hw_value)) {
			direct = B43_SHM_SH_CCKDIRECT;
			basic = B43_SHM_SH_CCKBASIC;
			offset = b43_plcp_get_ratecode_cck(rate->hw_value);
			offset &= 0xF;
		} else {
			direct = B43_SHM_SH_OFDMDIRECT;
			basic = B43_SHM_SH_OFDMBASIC;
			offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
			offset &= 0xF;
		}

		rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);

		if (b43_is_cck_rate(rate->hw_value)) {
			basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
			basic_offset &= 0xF;
		} else {
			basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
			basic_offset &= 0xF;
		}

		/*
		 * Get the pointer that we need to point to
		 * from the direct map
		 */
		rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
					 direct + 2 * basic_offset);
		/* and write it to the basic map */
		b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
				rateptr);
	}
}

static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
				    struct ieee80211_vif *vif,
				    struct ieee80211_bss_conf *conf,
				    u32 changed)
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);

	dev = wl->current_dev;
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	if (!dev || b43_status(dev) < B43_STAT_STARTED)
3967
		goto out_unlock_mutex;
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	B43_WARN_ON(wl->vif != vif);

	if (changed & BSS_CHANGED_BSSID) {
		if (conf->bssid)
			memcpy(wl->bssid, conf->bssid, ETH_ALEN);
		else
			memset(wl->bssid, 0, ETH_ALEN);
3976
	}
3977

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	if (b43_status(dev) >= B43_STAT_INITIALIZED) {
		if (changed & BSS_CHANGED_BEACON &&
		    (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
		     b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
		     b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
			b43_update_templates(wl);

		if (changed & BSS_CHANGED_BSSID)
3986 3987 3988
			b43_write_mac_bssid_templates(dev);
	}

3989 3990
	b43_mac_suspend(dev);

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	/* Update templates for AP/mesh mode. */
	if (changed & BSS_CHANGED_BEACON_INT &&
	    (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
	     b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
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	     b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
	    conf->beacon_int)
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		b43_set_beacon_int(dev, conf->beacon_int);

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	if (changed & BSS_CHANGED_BASIC_RATES)
		b43_update_basic_rates(dev, conf->basic_rates);

	if (changed & BSS_CHANGED_ERP_SLOT) {
		if (conf->use_short_slot)
			b43_short_slot_timing_enable(dev);
		else
			b43_short_slot_timing_disable(dev);
	}

	b43_mac_enable(dev);
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out_unlock_mutex:
4011 4012 4013
	mutex_unlock(&wl->mutex);
}

4014
static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4015 4016
			  struct ieee80211_vif *vif, struct ieee80211_sta *sta,
			  struct ieee80211_key_conf *key)
4017 4018
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
4019
	struct b43_wldev *dev;
4020 4021
	u8 algorithm;
	u8 index;
4022
	int err;
4023
	static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4024 4025 4026 4027

	if (modparam_nohwcrypt)
		return -ENOSPC; /* User disabled HW-crypto */

4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041
	if ((vif->type == NL80211_IFTYPE_ADHOC ||
	     vif->type == NL80211_IFTYPE_MESH_POINT) &&
	    (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
	     key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
	    !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
		/*
		 * For now, disable hw crypto for the RSN IBSS group keys. This
		 * could be optimized in the future, but until that gets
		 * implemented, use of software crypto for group addressed
		 * frames is a acceptable to allow RSN IBSS to be used.
		 */
		return -EOPNOTSUPP;
	}

4042 4043 4044 4045 4046 4047 4048
	mutex_lock(&wl->mutex);

	dev = wl->current_dev;
	err = -ENODEV;
	if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
		goto out_unlock;

Michael Buesch's avatar
Michael Buesch committed
4049
	if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4050 4051 4052 4053 4054 4055
		/* We don't have firmware for the crypto engine.
		 * Must use software-crypto. */
		err = -EOPNOTSUPP;
		goto out_unlock;
	}

4056
	err = -EINVAL;
4057 4058 4059 4060 4061 4062
	switch (key->cipher) {
	case WLAN_CIPHER_SUITE_WEP40:
		algorithm = B43_SEC_ALGO_WEP40;
		break;
	case WLAN_CIPHER_SUITE_WEP104:
		algorithm = B43_SEC_ALGO_WEP104;
4063
		break;
4064
	case WLAN_CIPHER_SUITE_TKIP:
4065 4066
		algorithm = B43_SEC_ALGO_TKIP;
		break;
4067
	case WLAN_CIPHER_SUITE_CCMP:
4068 4069 4070 4071
		algorithm = B43_SEC_ALGO_AES;
		break;
	default:
		B43_WARN_ON(1);
4072
		goto out_unlock;
4073 4074 4075 4076 4077 4078 4079
	}
	index = (u8) (key->keyidx);
	if (index > 3)
		goto out_unlock;

	switch (cmd) {
	case SET_KEY:
gregor kowski's avatar
gregor kowski committed
4080 4081 4082 4083
		if (algorithm == B43_SEC_ALGO_TKIP &&
		    (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
		    !modparam_hwtkip)) {
			/* We support only pairwise key */
4084 4085 4086 4087
			err = -EOPNOTSUPP;
			goto out_unlock;
		}

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Michael Buesch committed
4088
		if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4089 4090 4091 4092
			if (WARN_ON(!sta)) {
				err = -EOPNOTSUPP;
				goto out_unlock;
			}
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4093
			/* Pairwise key with an assigned MAC address. */
4094
			err = b43_key_write(dev, -1, algorithm,
4095 4096
					    key->key, key->keylen,
					    sta->addr, key);
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Michael Buesch committed
4097 4098 4099 4100
		} else {
			/* Group key */
			err = b43_key_write(dev, index, algorithm,
					    key->key, key->keylen, NULL, key);
4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112
		}
		if (err)
			goto out_unlock;

		if (algorithm == B43_SEC_ALGO_WEP40 ||
		    algorithm == B43_SEC_ALGO_WEP104) {
			b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
		} else {
			b43_hf_write(dev,
				     b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
		}
		key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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4113 4114
		if (algorithm == B43_SEC_ALGO_TKIP)
			key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4115 4116 4117 4118 4119 4120 4121 4122 4123 4124
		break;
	case DISABLE_KEY: {
		err = b43_key_clear(dev, key->hw_key_idx);
		if (err)
			goto out_unlock;
		break;
	}
	default:
		B43_WARN_ON(1);
	}
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4125

4126 4127 4128
out_unlock:
	if (!err) {
		b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4129
		       "mac: %pM\n",
4130
		       cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4131
		       sta ? sta->addr : bcast_addr);
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4132
		b43_dump_keymemory(dev);
4133
	}
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4134 4135
	mutex_unlock(&wl->mutex);

4136 4137 4138
	return err;
}

4139 4140
static void b43_op_configure_filter(struct ieee80211_hw *hw,
				    unsigned int changed, unsigned int *fflags,
4141
				    u64 multicast)
4142 4143
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
4144
	struct b43_wldev *dev;
4145

4146 4147
	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
4148 4149
	if (!dev) {
		*fflags = 0;
4150
		goto out_unlock;
4151
	}
4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172

	*fflags &= FIF_PROMISC_IN_BSS |
		  FIF_ALLMULTI |
		  FIF_FCSFAIL |
		  FIF_PLCPFAIL |
		  FIF_CONTROL |
		  FIF_OTHER_BSS |
		  FIF_BCN_PRBRESP_PROMISC;

	changed &= FIF_PROMISC_IN_BSS |
		   FIF_ALLMULTI |
		   FIF_FCSFAIL |
		   FIF_PLCPFAIL |
		   FIF_CONTROL |
		   FIF_OTHER_BSS |
		   FIF_BCN_PRBRESP_PROMISC;

	wl->filter_flags = *fflags;

	if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
		b43_adjust_opmode(dev);
4173 4174 4175

out_unlock:
	mutex_unlock(&wl->mutex);
4176 4177
}

4178 4179 4180 4181
/* Locking: wl->mutex
 * Returns the current dev. This might be different from the passed in dev,
 * because the core might be gone away while we unlocked the mutex. */
static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4182
{
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4183
	struct b43_wl *wl;
4184
	struct b43_wldev *orig_dev;
4185
	u32 mask;
4186
	int queue_num;
4187

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Larry Finger committed
4188 4189 4190
	if (!dev)
		return NULL;
	wl = dev->wl;
4191 4192 4193
redo:
	if (!dev || b43_status(dev) < B43_STAT_STARTED)
		return dev;
4194

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4195
	/* Cancel work. Unlock to avoid deadlocks. */
4196 4197
	mutex_unlock(&wl->mutex);
	cancel_delayed_work_sync(&dev->periodic_work);
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4198
	cancel_work_sync(&wl->tx_work);
4199 4200 4201 4202 4203 4204
	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (!dev || b43_status(dev) < B43_STAT_STARTED) {
		/* Whoops, aliens ate up the device while we were unlocked. */
		return dev;
	}
4205

4206
	/* Disable interrupts on the device. */
4207
	b43_set_status(dev, B43_STAT_INITIALIZED);
4208
	if (b43_bus_host_is_sdio(dev->dev)) {
4209 4210 4211 4212 4213 4214 4215 4216 4217
		/* wl->mutex is locked. That is enough. */
		b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
		b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);	/* Flush */
	} else {
		spin_lock_irq(&wl->hardirq_lock);
		b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
		b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);	/* Flush */
		spin_unlock_irq(&wl->hardirq_lock);
	}
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4218
	/* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4219
	orig_dev = dev;
4220
	mutex_unlock(&wl->mutex);
4221
	if (b43_bus_host_is_sdio(dev->dev)) {
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4222 4223
		b43_sdio_free_irq(dev);
	} else {
4224 4225
		synchronize_irq(dev->dev->irq);
		free_irq(dev->dev->irq, dev);
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4226
	}
4227
	mutex_lock(&wl->mutex);
4228 4229 4230 4231 4232 4233 4234 4235
	dev = wl->current_dev;
	if (!dev)
		return dev;
	if (dev != orig_dev) {
		if (b43_status(dev) >= B43_STAT_STARTED)
			goto redo;
		return dev;
	}
4236 4237
	mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
	B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4238

4239 4240
	/* Drain all TX queues. */
	for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
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4241 4242 4243 4244 4245 4246
		while (skb_queue_len(&wl->tx_queue[queue_num])) {
			struct sk_buff *skb;

			skb = skb_dequeue(&wl->tx_queue[queue_num]);
			ieee80211_free_txskb(wl->hw, skb);
		}
4247
	}
Michael Buesch's avatar
Michael Buesch committed
4248

4249
	b43_mac_suspend(dev);
4250
	b43_leds_exit(dev);
4251
	b43dbg(wl, "Wireless interface stopped\n");
4252 4253

	return dev;
4254 4255 4256 4257 4258 4259 4260 4261 4262 4263
}

/* Locking: wl->mutex */
static int b43_wireless_core_start(struct b43_wldev *dev)
{
	int err;

	B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);

	drain_txstatus_queue(dev);
4264
	if (b43_bus_host_is_sdio(dev->dev)) {
4265 4266 4267 4268 4269 4270
		err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
		if (err) {
			b43err(dev->wl, "Cannot request SDIO IRQ\n");
			goto out;
		}
	} else {
4271
		err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4272 4273 4274
					   b43_interrupt_thread_handler,
					   IRQF_SHARED, KBUILD_MODNAME, dev);
		if (err) {
4275
			b43err(dev->wl, "Cannot request IRQ-%d\n",
4276
			       dev->dev->irq);
4277 4278
			goto out;
		}
4279 4280 4281
	}

	/* We are ready to run. */
4282
	ieee80211_wake_queues(dev->wl->hw);
4283 4284 4285 4286
	b43_set_status(dev, B43_STAT_STARTED);

	/* Start data flow (TX/RX). */
	b43_mac_enable(dev);
4287
	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4288

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4289
	/* Start maintenance work */
4290 4291
	b43_periodic_tasks_setup(dev);

4292 4293
	b43_leds_init(dev);

4294
	b43dbg(dev->wl, "Wireless interface started\n");
4295
out:
4296 4297 4298
	return err;
}

4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327
static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
{
	switch (phy_type) {
	case B43_PHYTYPE_A:
		return "A";
	case B43_PHYTYPE_B:
		return "B";
	case B43_PHYTYPE_G:
		return "G";
	case B43_PHYTYPE_N:
		return "N";
	case B43_PHYTYPE_LP:
		return "LP";
	case B43_PHYTYPE_SSLPN:
		return "SSLPN";
	case B43_PHYTYPE_HT:
		return "HT";
	case B43_PHYTYPE_LCN:
		return "LCN";
	case B43_PHYTYPE_LCNXN:
		return "LCNXN";
	case B43_PHYTYPE_LCN40:
		return "LCN40";
	case B43_PHYTYPE_AC:
		return "AC";
	}
	return "UNKNOWN";
}

4328 4329 4330 4331
/* Get PHY and RADIO versioning numbers */
static int b43_phy_versioning(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
4332
	const u8 core_rev = dev->dev->core_rev;
4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346
	u32 tmp;
	u8 analog_type;
	u8 phy_type;
	u8 phy_rev;
	u16 radio_manuf;
	u16 radio_ver;
	u16 radio_rev;
	int unsupported = 0;

	/* Get PHY versioning */
	tmp = b43_read16(dev, B43_MMIO_PHY_VER);
	analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
	phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
	phy_rev = (tmp & B43_PHYVER_VERSION);
4347 4348 4349 4350 4351 4352 4353

	/* LCNXN is continuation of N which run out of revisions */
	if (phy_type == B43_PHYTYPE_LCNXN) {
		phy_type = B43_PHYTYPE_N;
		phy_rev += 16;
	}

4354
	switch (phy_type) {
4355
#ifdef CONFIG_B43_PHY_G
4356
	case B43_PHYTYPE_G:
4357
		if (phy_rev > 9)
4358 4359
			unsupported = 1;
		break;
4360
#endif
4361
#ifdef CONFIG_B43_PHY_N
4362
	case B43_PHYTYPE_N:
4363
		if (phy_rev > 9)
4364 4365
			unsupported = 1;
		break;
4366 4367 4368
#endif
#ifdef CONFIG_B43_PHY_LP
	case B43_PHYTYPE_LP:
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Gábor Stefanik committed
4369
		if (phy_rev > 2)
4370 4371
			unsupported = 1;
		break;
4372 4373 4374 4375 4376 4377
#endif
#ifdef CONFIG_B43_PHY_HT
	case B43_PHYTYPE_HT:
		if (phy_rev > 1)
			unsupported = 1;
		break;
4378 4379 4380 4381 4382 4383
#endif
#ifdef CONFIG_B43_PHY_LCN
	case B43_PHYTYPE_LCN:
		if (phy_rev > 1)
			unsupported = 1;
		break;
4384
#endif
4385 4386
	default:
		unsupported = 1;
4387
	}
4388
	if (unsupported) {
4389 4390 4391
		b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
		       analog_type, phy_type, b43_phy_name(dev, phy_type),
		       phy_rev);
4392 4393
		return -EOPNOTSUPP;
	}
4394 4395
	b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
		analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4396 4397

	/* Get RADIO versioning */
4398 4399 4400 4401 4402 4403 4404 4405 4406
	if (core_rev == 40 || core_rev == 42) {
		radio_manuf = 0x17F;

		b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 0);
		radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);

		b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 1);
		radio_ver = b43_read16(dev, B43_MMIO_RADIO24_DATA);
	} else if (core_rev >= 24) {
4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419
		u16 radio24[3];

		for (tmp = 0; tmp < 3; tmp++) {
			b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
			radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
		}

		/* Broadcom uses "id" for our "ver" and has separated "ver" */
		/* radio_ver = (radio24[0] & 0xF0) >> 4; */

		radio_manuf = 0x17F;
		radio_ver = (radio24[2] << 8) | radio24[1];
		radio_rev = (radio24[0] & 0xF);
4420
	} else {
4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439
		if (dev->dev->chip_id == 0x4317) {
			if (dev->dev->chip_rev == 0)
				tmp = 0x3205017F;
			else if (dev->dev->chip_rev == 1)
				tmp = 0x4205017F;
			else
				tmp = 0x5205017F;
		} else {
			b43_write16(dev, B43_MMIO_RADIO_CONTROL,
				    B43_RADIOCTL_ID);
			tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
			b43_write16(dev, B43_MMIO_RADIO_CONTROL,
				    B43_RADIOCTL_ID);
			tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
				<< 16;
		}
		radio_manuf = (tmp & 0x00000FFF);
		radio_ver = (tmp & 0x0FFFF000) >> 12;
		radio_rev = (tmp & 0xF0000000) >> 28;
4440
	}
4441

4442 4443
	if (radio_manuf != 0x17F /* Broadcom */)
		unsupported = 1;
4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460
	switch (phy_type) {
	case B43_PHYTYPE_A:
		if (radio_ver != 0x2060)
			unsupported = 1;
		if (radio_rev != 1)
			unsupported = 1;
		if (radio_manuf != 0x17F)
			unsupported = 1;
		break;
	case B43_PHYTYPE_B:
		if ((radio_ver & 0xFFF0) != 0x2050)
			unsupported = 1;
		break;
	case B43_PHYTYPE_G:
		if (radio_ver != 0x2050)
			unsupported = 1;
		break;
4461
	case B43_PHYTYPE_N:
4462
		if (radio_ver != 0x2055 && radio_ver != 0x2056)
4463 4464
			unsupported = 1;
		break;
4465
	case B43_PHYTYPE_LP:
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Gábor Stefanik committed
4466
		if (radio_ver != 0x2062 && radio_ver != 0x2063)
4467 4468
			unsupported = 1;
		break;
4469 4470 4471 4472
	case B43_PHYTYPE_HT:
		if (radio_ver != 0x2059)
			unsupported = 1;
		break;
4473 4474 4475 4476
	case B43_PHYTYPE_LCN:
		if (radio_ver != 0x2064)
			unsupported = 1;
		break;
4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503
	default:
		B43_WARN_ON(1);
	}
	if (unsupported) {
		b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
		       "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
		       radio_manuf, radio_ver, radio_rev);
		return -EOPNOTSUPP;
	}
	b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
	       radio_manuf, radio_ver, radio_rev);

	phy->radio_manuf = radio_manuf;
	phy->radio_ver = radio_ver;
	phy->radio_rev = radio_rev;

	phy->analog = analog_type;
	phy->type = phy_type;
	phy->rev = phy_rev;

	return 0;
}

static void setup_struct_phy_for_init(struct b43_wldev *dev,
				      struct b43_phy *phy)
{
	phy->hardware_power_control = !!modparam_hwpctl;
4504
	phy->next_txpwr_check_time = jiffies;
4505 4506
	/* PHY TX errors counter. */
	atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4507 4508

#if B43_DEBUG
4509 4510
	phy->phy_locked = false;
	phy->radio_locked = false;
4511
#endif
4512 4513 4514 4515
}

static void setup_struct_wldev_for_init(struct b43_wldev *dev)
{
4516
	dev->dfq_valid = false;
4517

4518 4519
	/* Assume the radio is enabled. If it's not enabled, the state will
	 * immediately get fixed on the first periodic work run. */
4520
	dev->radio_hw_enable = true;
4521 4522 4523 4524 4525 4526 4527 4528 4529

	/* Stats */
	memset(&dev->stats, 0, sizeof(dev->stats));

	setup_struct_phy_for_init(dev, &dev->phy);

	/* IRQ related flags */
	dev->irq_reason = 0;
	memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4530
	dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4531
	if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4532
		dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4533 4534 4535 4536 4537 4538 4539 4540 4541

	dev->mac_suspended = 1;

	/* Noise calculation context */
	memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
}

static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
{
Rafał Miłecki's avatar
Rafał Miłecki committed
4542
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
4543
	u64 hf;
4544

4545 4546
	if (!modparam_btcoex)
		return;
4547
	if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4548 4549 4550 4551 4552
		return;
	if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
		return;

	hf = b43_hf_read(dev);
4553
	if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4554 4555 4556 4557 4558 4559 4560
		hf |= B43_HF_BTCOEXALT;
	else
		hf |= B43_HF_BTCOEX;
	b43_hf_write(dev, hf);
}

static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4561 4562 4563 4564
{
	if (!modparam_btcoex)
		return;
	//TODO
4565 4566 4567 4568
}

static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
{
4569
	struct ssb_bus *bus;
4570 4571
	u32 tmp;

4572
#ifdef CONFIG_B43_SSB
4573 4574
	if (dev->dev->bus_type != B43_BUS_SSB)
		return;
4575 4576 4577
#else
	return;
#endif
4578 4579 4580

	bus = dev->dev->sdev->bus;

4581 4582
	if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
	    (bus->chip_id == 0x4312)) {
4583
		tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4584 4585 4586
		tmp &= ~SSB_IMCFGLO_REQTO;
		tmp &= ~SSB_IMCFGLO_SERTO;
		tmp |= 0x3;
4587
		ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4588
		ssb_commit_settings(bus);
4589 4590 4591
	}
}

4592 4593 4594 4595 4596 4597 4598 4599 4600
static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
{
	u16 pu_delay;

	/* The time value is in microseconds. */
	if (dev->phy.type == B43_PHYTYPE_A)
		pu_delay = 3700;
	else
		pu_delay = 1050;
4601
	if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614
		pu_delay = 500;
	if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
		pu_delay = max(pu_delay, (u16)2400);

	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
}

/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
static void b43_set_pretbtt(struct b43_wldev *dev)
{
	u16 pretbtt;

	/* The time value is in microseconds. */
4615
	if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626
		pretbtt = 2;
	} else {
		if (dev->phy.type == B43_PHYTYPE_A)
			pretbtt = 120;
		else
			pretbtt = 250;
	}
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
	b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
}

4627 4628 4629 4630
/* Shutdown a wireless core */
/* Locking: wl->mutex */
static void b43_wireless_core_exit(struct b43_wldev *dev)
{
4631 4632
	B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
	if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4633
		return;
4634

4635 4636
	b43_set_status(dev, B43_STAT_UNINIT);

4637
	/* Stop the microcode PSM. */
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Rafał Miłecki committed
4638 4639
	b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
		      B43_MACCTL_PSM_JMP0);
4640

4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653
	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		bcma_core_pci_down(dev->dev->bdev->bus);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		/* TODO */
		break;
#endif
	}

4654
	b43_dma_free(dev);
4655
	b43_pio_free(dev);
4656
	b43_chip_exit(dev);
4657
	dev->phy.ops->switch_analog(dev, 0);
4658 4659 4660 4661 4662
	if (dev->wl->current_beacon) {
		dev_kfree_skb_any(dev->wl->current_beacon);
		dev->wl->current_beacon = NULL;
	}

4663 4664
	b43_device_disable(dev, 0);
	b43_bus_may_powerdown(dev);
4665 4666 4667 4668 4669
}

/* Initialize a wireless core */
static int b43_wireless_core_init(struct b43_wldev *dev)
{
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4670
	struct ssb_sprom *sprom = dev->dev->bus_sprom;
4671 4672
	struct b43_phy *phy = &dev->phy;
	int err;
4673
	u64 hf;
4674 4675 4676

	B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);

4677
	err = b43_bus_powerup(dev, 0);
4678 4679
	if (err)
		goto out;
4680 4681
	if (!b43_device_is_enabled(dev))
		b43_wireless_core_reset(dev, phy->gmode);
4682

4683
	/* Reset all data structures. */
4684
	setup_struct_wldev_for_init(dev);
4685
	phy->ops->prepare_structs(dev);
4686 4687

	/* Enable IRQ routing to this device. */
4688
	switch (dev->dev->bus_type) {
4689 4690
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
4691
		bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
4692
				      dev->dev->bdev, true);
4693
		bcma_core_pci_up(dev->dev->bdev->bus);
4694 4695
		break;
#endif
4696 4697 4698 4699 4700 4701 4702
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
					       dev->dev->sdev);
		break;
#endif
	}
4703 4704 4705

	b43_imcfglo_timeouts_workaround(dev);
	b43_bluetooth_coext_disable(dev);
4706 4707
	if (phy->ops->prepare_hardware) {
		err = phy->ops->prepare_hardware(dev);
4708
		if (err)
4709
			goto err_busdown;
4710
	}
4711 4712
	err = b43_chip_init(dev);
	if (err)
4713
		goto err_busdown;
4714
	b43_shm_write16(dev, B43_SHM_SHARED,
4715
			B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4716 4717 4718 4719 4720
	hf = b43_hf_read(dev);
	if (phy->type == B43_PHYTYPE_G) {
		hf |= B43_HF_SYMW;
		if (phy->rev == 1)
			hf |= B43_HF_GDCW;
4721
		if (sprom->boardflags_lo & B43_BFL_PACTRL)
4722
			hf |= B43_HF_OFDMPABOOST;
Michael Buesch's avatar
Michael Buesch committed
4723 4724 4725 4726 4727 4728
	}
	if (phy->radio_ver == 0x2050) {
		if (phy->radio_rev == 6)
			hf |= B43_HF_4318TSSI;
		if (phy->radio_rev < 6)
			hf |= B43_HF_VCORECALC;
4729
	}
4730 4731
	if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
		hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4732
#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4733 4734 4735
	if (dev->dev->bus_type == B43_BUS_SSB &&
	    dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
	    dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4736
		hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4737
#endif
4738
	hf &= ~B43_HF_SKCFPUP;
4739 4740
	b43_hf_write(dev, hf);

4741 4742
	b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
			     B43_DEFAULT_LONG_RETRY_LIMIT);
4743 4744 4745 4746 4747 4748 4749 4750 4751 4752
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);

	/* Disable sending probe responses from firmware.
	 * Setting the MaxTime to one usec will always trigger
	 * a timeout, so we never send any probe resp.
	 * A timeout of zero is infinite. */
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);

	b43_rate_memory_init(dev);
4753
	b43_set_phytxctl_defaults(dev);
4754 4755

	/* Minimum Contention Window */
4756
	if (phy->type == B43_PHYTYPE_B)
4757
		b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4758
	else
4759 4760 4761 4762
		b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
	/* Maximum Contention Window */
	b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);

4763
	if (b43_bus_host_is_pcmcia(dev->dev) ||
4764
	    b43_bus_host_is_sdio(dev->dev)) {
4765
		dev->__using_pio_transfers = true;
4766 4767 4768 4769 4770
		err = b43_pio_init(dev);
	} else if (dev->use_pio) {
		b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
			"This should not be needed and will result in lower "
			"performance.\n");
4771
		dev->__using_pio_transfers = true;
4772 4773
		err = b43_pio_init(dev);
	} else {
4774
		dev->__using_pio_transfers = false;
4775 4776
		err = b43_dma_init(dev);
	}
4777 4778
	if (err)
		goto err_chip_exit;
Michael Buesch's avatar
Michael Buesch committed
4779
	b43_qos_init(dev);
4780
	b43_set_synth_pu_delay(dev, 1);
4781 4782
	b43_bluetooth_coext_enable(dev);

4783
	b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4784
	b43_upload_card_macaddress(dev);
4785 4786
	b43_security_init(dev);

4787
	ieee80211_wake_queues(dev->wl->hw);
4788 4789 4790

	b43_set_status(dev, B43_STAT_INITIALIZED);

Larry Finger's avatar
Larry Finger committed
4791
out:
4792 4793
	return err;

4794
err_chip_exit:
4795
	b43_chip_exit(dev);
4796
err_busdown:
4797
	b43_bus_may_powerdown(dev);
4798 4799 4800 4801
	B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
	return err;
}

4802
static int b43_op_add_interface(struct ieee80211_hw *hw,
4803
				struct ieee80211_vif *vif)
4804 4805 4806 4807
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;
	int err = -EOPNOTSUPP;
4808 4809 4810

	/* TODO: allow WDS/AP devices to coexist */

4811 4812 4813 4814 4815
	if (vif->type != NL80211_IFTYPE_AP &&
	    vif->type != NL80211_IFTYPE_MESH_POINT &&
	    vif->type != NL80211_IFTYPE_STATION &&
	    vif->type != NL80211_IFTYPE_WDS &&
	    vif->type != NL80211_IFTYPE_ADHOC)
4816
		return -EOPNOTSUPP;
4817 4818

	mutex_lock(&wl->mutex);
4819
	if (wl->operating)
4820 4821
		goto out_mutex_unlock;

4822
	b43dbg(wl, "Adding Interface type %d\n", vif->type);
4823 4824

	dev = wl->current_dev;
4825
	wl->operating = true;
4826 4827 4828
	wl->vif = vif;
	wl->if_type = vif->type;
	memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4829 4830

	b43_adjust_opmode(dev);
4831 4832
	b43_set_pretbtt(dev);
	b43_set_synth_pu_delay(dev, 0);
4833 4834 4835 4836 4837 4838
	b43_upload_card_macaddress(dev);

	err = 0;
 out_mutex_unlock:
	mutex_unlock(&wl->mutex);

4839 4840 4841
	if (err == 0)
		b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);

4842 4843 4844
	return err;
}

4845
static void b43_op_remove_interface(struct ieee80211_hw *hw,
4846
				    struct ieee80211_vif *vif)
4847 4848 4849 4850
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev = wl->current_dev;

4851
	b43dbg(wl, "Removing Interface type %d\n", vif->type);
4852 4853 4854 4855

	mutex_lock(&wl->mutex);

	B43_WARN_ON(!wl->operating);
4856
	B43_WARN_ON(wl->vif != vif);
4857
	wl->vif = NULL;
4858

4859
	wl->operating = false;
4860 4861 4862 4863 4864 4865 4866 4867

	b43_adjust_opmode(dev);
	memset(wl->mac_addr, 0, ETH_ALEN);
	b43_upload_card_macaddress(dev);

	mutex_unlock(&wl->mutex);
}

4868
static int b43_op_start(struct ieee80211_hw *hw)
4869 4870 4871 4872
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev = wl->current_dev;
	int did_init = 0;
4873
	int err = 0;
4874

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Michael Buesch committed
4875 4876 4877 4878 4879 4880
	/* Kill all old instance specific information to make sure
	 * the card won't use it in the short timeframe between start
	 * and mac80211 reconfiguring it. */
	memset(wl->bssid, 0, ETH_ALEN);
	memset(wl->mac_addr, 0, ETH_ALEN);
	wl->filter_flags = 0;
4881
	wl->radiotap_enabled = false;
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Michael Buesch committed
4882
	b43_qos_clear(wl);
4883 4884 4885 4886
	wl->beacon0_uploaded = false;
	wl->beacon1_uploaded = false;
	wl->beacon_templates_virgin = true;
	wl->radio_enabled = true;
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Michael Buesch committed
4887

4888 4889
	mutex_lock(&wl->mutex);

4890 4891
	if (b43_status(dev) < B43_STAT_INITIALIZED) {
		err = b43_wireless_core_init(dev);
4892
		if (err)
4893 4894 4895
			goto out_mutex_unlock;
		did_init = 1;
	}
4896

4897 4898 4899 4900 4901 4902 4903 4904 4905
	if (b43_status(dev) < B43_STAT_STARTED) {
		err = b43_wireless_core_start(dev);
		if (err) {
			if (did_init)
				b43_wireless_core_exit(dev);
			goto out_mutex_unlock;
		}
	}

4906 4907 4908
	/* XXX: only do if device doesn't support rfkill irq */
	wiphy_rfkill_start_polling(hw->wiphy);

4909
 out_mutex_unlock:
4910 4911
	mutex_unlock(&wl->mutex);

4912 4913 4914 4915 4916 4917 4918 4919
	/*
	 * Configuration may have been overwritten during initialization.
	 * Reload the configuration, but only if initialization was
	 * successful. Reloading the configuration after a failed init
	 * may hang the system.
	 */
	if (!err)
		b43_op_config(hw, ~0);
4920

4921 4922 4923
	return err;
}

4924
static void b43_op_stop(struct ieee80211_hw *hw)
4925 4926
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
4927
	struct b43_wldev *dev = wl->current_dev;
4928

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4929
	cancel_work_sync(&(wl->beacon_update_trigger));
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Larry Finger committed
4930

4931 4932 4933
	if (!dev)
		goto out;

4934
	mutex_lock(&wl->mutex);
4935 4936 4937 4938 4939
	if (b43_status(dev) >= B43_STAT_STARTED) {
		dev = b43_wireless_core_stop(dev);
		if (!dev)
			goto out_unlock;
	}
4940
	b43_wireless_core_exit(dev);
4941
	wl->radio_enabled = false;
4942 4943

out_unlock:
4944
	mutex_unlock(&wl->mutex);
4945
out:
4946
	cancel_work_sync(&(wl->txpower_adjust_work));
4947 4948
}

4949 4950
static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
				 struct ieee80211_sta *sta, bool set)
4951 4952 4953
{
	struct b43_wl *wl = hw_to_b43_wl(hw);

4954
	/* FIXME: add locking */
4955
	b43_update_templates(wl);
4956 4957 4958 4959

	return 0;
}

4960 4961 4962
static void b43_op_sta_notify(struct ieee80211_hw *hw,
			      struct ieee80211_vif *vif,
			      enum sta_notify_cmd notify_cmd,
4963
			      struct ieee80211_sta *sta)
4964 4965 4966 4967 4968 4969
{
	struct b43_wl *wl = hw_to_b43_wl(hw);

	B43_WARN_ON(!vif || wl->vif != vif);
}

4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997
static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
		/* Disable CFP update during scan on other channels. */
		b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
	}
	mutex_unlock(&wl->mutex);
}

static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;
	if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
		/* Re-enable CFP update. */
		b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
	}
	mutex_unlock(&wl->mutex);
}

4998 4999 5000 5001 5002 5003 5004 5005 5006 5007
static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
			     struct survey_info *survey)
{
	struct b43_wl *wl = hw_to_b43_wl(hw);
	struct b43_wldev *dev = wl->current_dev;
	struct ieee80211_conf *conf = &hw->conf;

	if (idx != 0)
		return -ENOENT;

5008
	survey->channel = conf->chandef.chan;
5009 5010 5011 5012 5013 5014
	survey->filled = SURVEY_INFO_NOISE_DBM;
	survey->noise = dev->stats.link_noise;

	return 0;
}

5015
static const struct ieee80211_ops b43_hw_ops = {
5016 5017 5018 5019 5020
	.tx			= b43_op_tx,
	.conf_tx		= b43_op_conf_tx,
	.add_interface		= b43_op_add_interface,
	.remove_interface	= b43_op_remove_interface,
	.config			= b43_op_config,
5021
	.bss_info_changed	= b43_op_bss_info_changed,
5022 5023
	.configure_filter	= b43_op_configure_filter,
	.set_key		= b43_op_set_key,
gregor kowski's avatar
gregor kowski committed
5024
	.update_tkip_key	= b43_op_update_tkip_key,
5025
	.get_stats		= b43_op_get_stats,
5026 5027
	.get_tsf		= b43_op_get_tsf,
	.set_tsf		= b43_op_set_tsf,
5028 5029
	.start			= b43_op_start,
	.stop			= b43_op_stop,
5030
	.set_tim		= b43_op_beacon_set_tim,
5031
	.sta_notify		= b43_op_sta_notify,
5032 5033
	.sw_scan_start		= b43_op_sw_scan_start_notifier,
	.sw_scan_complete	= b43_op_sw_scan_complete_notifier,
5034
	.get_survey		= b43_op_get_survey,
5035
	.rfkill_poll		= b43_rfkill_poll,
5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052
};

/* Hard-reset the chip. Do not call this directly.
 * Use b43_controller_restart()
 */
static void b43_chip_reset(struct work_struct *work)
{
	struct b43_wldev *dev =
	    container_of(work, struct b43_wldev, restart_work);
	struct b43_wl *wl = dev->wl;
	int err = 0;
	int prev_status;

	mutex_lock(&wl->mutex);

	prev_status = b43_status(dev);
	/* Bring the device down... */
5053 5054 5055 5056 5057 5058 5059
	if (prev_status >= B43_STAT_STARTED) {
		dev = b43_wireless_core_stop(dev);
		if (!dev) {
			err = -ENODEV;
			goto out;
		}
	}
5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075
	if (prev_status >= B43_STAT_INITIALIZED)
		b43_wireless_core_exit(dev);

	/* ...and up again. */
	if (prev_status >= B43_STAT_INITIALIZED) {
		err = b43_wireless_core_init(dev);
		if (err)
			goto out;
	}
	if (prev_status >= B43_STAT_STARTED) {
		err = b43_wireless_core_start(dev);
		if (err) {
			b43_wireless_core_exit(dev);
			goto out;
		}
	}
5076 5077 5078
out:
	if (err)
		wl->current_dev = NULL; /* Failed to init the dev. */
5079
	mutex_unlock(&wl->mutex);
5080 5081

	if (err) {
5082
		b43err(wl, "Controller restart FAILED\n");
5083 5084 5085 5086 5087 5088 5089 5090 5091
		return;
	}

	/* reload configuration */
	b43_op_config(wl->hw, ~0);
	if (wl->vif)
		b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);

	b43info(wl, "Controller restarted\n");
5092 5093
}

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5094
static int b43_setup_bands(struct b43_wldev *dev,
5095
			   bool have_2ghz_phy, bool have_5ghz_phy)
5096 5097 5098
{
	struct ieee80211_hw *hw = dev->wl->hw;

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5099 5100 5101 5102 5103 5104 5105 5106 5107
	if (have_2ghz_phy)
		hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
	if (dev->phy.type == B43_PHYTYPE_N) {
		if (have_5ghz_phy)
			hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
	} else {
		if (have_5ghz_phy)
			hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
	}
5108

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Michael Buesch committed
5109 5110
	dev->phy.supports_2ghz = have_2ghz_phy;
	dev->phy.supports_5ghz = have_5ghz_phy;
5111 5112 5113 5114 5115 5116 5117 5118 5119

	return 0;
}

static void b43_wireless_core_detach(struct b43_wldev *dev)
{
	/* We release firmware that late to not be required to re-request
	 * is all the time when we reinit the core. */
	b43_release_firmware(dev);
5120
	b43_phy_free(dev);
5121 5122
}

5123 5124 5125 5126 5127
static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
				bool *have_5ghz_phy)
{
	u16 dev_id = 0;

5128 5129 5130 5131 5132
#ifdef CONFIG_B43_BCMA
	if (dev->dev->bus_type == B43_BUS_BCMA &&
	    dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
		dev_id = dev->dev->bdev->bus->host_pci->device;
#endif
5133 5134 5135 5136 5137
#ifdef CONFIG_B43_SSB
	if (dev->dev->bus_type == B43_BUS_SSB &&
	    dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
		dev_id = dev->dev->sdev->bus->host_pci->device;
#endif
5138 5139 5140
	/* Override with SPROM value if available */
	if (dev->dev->bus_sprom->dev_id)
		dev_id = dev->dev->bus_sprom->dev_id;
5141 5142 5143 5144 5145 5146

	/* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
	switch (dev_id) {
	case 0x4324: /* BCM4306 */
	case 0x4312: /* BCM4311 */
	case 0x4319: /* BCM4318 */
5147 5148 5149 5150 5151 5152 5153 5154 5155 5156
	case 0x4328: /* BCM4321 */
	case 0x432b: /* BCM4322 */
	case 0x4350: /* BCM43222 */
	case 0x4353: /* BCM43224 */
	case 0x0576: /* BCM43224 */
	case 0x435f: /* BCM6362 */
	case 0x4331: /* BCM4331 */
	case 0x4359: /* BCM43228 */
	case 0x43a0: /* BCM4360 */
	case 0x43b1: /* BCM4352 */
5157 5158 5159 5160
		/* Dual band devices */
		*have_2ghz_phy = true;
		*have_5ghz_phy = true;
		return;
5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173
	case 0x4321: /* BCM4306 */
	case 0x4313: /* BCM4311 */
	case 0x431a: /* BCM4318 */
	case 0x432a: /* BCM4321 */
	case 0x432d: /* BCM4322 */
	case 0x4352: /* BCM43222 */
	case 0x4333: /* BCM4331 */
	case 0x43a2: /* BCM4360 */
	case 0x43b3: /* BCM4352 */
		/* 5 GHz only devices */
		*have_2ghz_phy = false;
		*have_5ghz_phy = true;
		return;
5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194
	}

	/* As a fallback, try to guess using PHY type */
	switch (dev->phy.type) {
	case B43_PHYTYPE_A:
		*have_2ghz_phy = false;
		*have_5ghz_phy = true;
		return;
	case B43_PHYTYPE_G:
	case B43_PHYTYPE_N:
	case B43_PHYTYPE_LP:
	case B43_PHYTYPE_HT:
	case B43_PHYTYPE_LCN:
		*have_2ghz_phy = true;
		*have_5ghz_phy = false;
		return;
	}

	B43_WARN_ON(1);
}

5195 5196 5197
static int b43_wireless_core_attach(struct b43_wldev *dev)
{
	struct b43_wl *wl = dev->wl;
5198
	struct b43_phy *phy = &dev->phy;
5199
	int err;
5200
	u32 tmp;
5201
	bool have_2ghz_phy = false, have_5ghz_phy = false;
5202 5203 5204 5205 5206 5207 5208 5209

	/* Do NOT do any device initialization here.
	 * Do it in wireless_core_init() instead.
	 * This function is for gathering basic information about the HW, only.
	 * Also some structs may be set up here. But most likely you want to have
	 * that in core_init(), too.
	 */

5210
	err = b43_bus_powerup(dev, 0);
5211 5212 5213 5214 5215
	if (err) {
		b43err(wl, "Bus powerup failed\n");
		goto out;
	}

5216 5217
	phy->do_full_init = true;

5218
	/* Try to guess supported bands for the first init needs */
5219
	switch (dev->dev->bus_type) {
5220 5221
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
5222 5223 5224
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
		have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
		have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5225 5226
		break;
#endif
5227 5228 5229
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		if (dev->dev->core_rev >= 5) {
5230 5231 5232
			tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
			have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
			have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5233 5234 5235 5236 5237
		} else
			B43_WARN_ON(1);
		break;
#endif
	}
5238

5239
	dev->phy.gmode = have_2ghz_phy;
5240
	b43_wireless_core_reset(dev, dev->phy.gmode);
5241

5242
	/* Get the PHY type. */
5243 5244
	err = b43_phy_versioning(dev);
	if (err)
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5245
		goto err_powerdown;
5246 5247 5248 5249 5250 5251 5252 5253 5254

	/* Get real info about supported bands */
	b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);

	/* We don't support 5 GHz on some PHYs yet */
	switch (dev->phy.type) {
	case B43_PHYTYPE_A:
	case B43_PHYTYPE_N:
	case B43_PHYTYPE_LP:
5255
	case B43_PHYTYPE_HT:
5256
		b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5257
		have_5ghz_phy = false;
5258
	}
5259 5260 5261

	if (!have_2ghz_phy && !have_5ghz_phy) {
		b43err(wl, "b43 can't support any band on this device\n");
5262 5263 5264
		err = -EOPNOTSUPP;
		goto err_powerdown;
	}
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5265

5266 5267 5268 5269
	err = b43_phy_allocate(dev);
	if (err)
		goto err_powerdown;

5270
	dev->phy.gmode = have_2ghz_phy;
5271
	b43_wireless_core_reset(dev, dev->phy.gmode);
5272 5273 5274

	err = b43_validate_chipaccess(dev);
	if (err)
5275
		goto err_phy_free;
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5276
	err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5277
	if (err)
5278
		goto err_phy_free;
5279 5280 5281 5282 5283 5284

	/* Now set some default "current_dev" */
	if (!wl->current_dev)
		wl->current_dev = dev;
	INIT_WORK(&dev->restart_work, b43_chip_reset);

5285
	dev->phy.ops->switch_analog(dev, 0);
5286 5287
	b43_device_disable(dev, 0);
	b43_bus_may_powerdown(dev);
5288 5289 5290 5291

out:
	return err;

5292 5293
err_phy_free:
	b43_phy_free(dev);
5294
err_powerdown:
5295
	b43_bus_may_powerdown(dev);
5296 5297 5298
	return err;
}

5299
static void b43_one_core_detach(struct b43_bus_dev *dev)
5300 5301 5302 5303
{
	struct b43_wldev *wldev;
	struct b43_wl *wl;

5304 5305 5306
	/* Do not cancel ieee80211-workqueue based work here.
	 * See comment in b43_remove(). */

5307
	wldev = b43_bus_get_wldev(dev);
5308 5309 5310 5311
	wl = wldev->wl;
	b43_debugfs_remove_device(wldev);
	b43_wireless_core_detach(wldev);
	list_del(&wldev->list);
5312
	b43_bus_set_wldev(dev, NULL);
5313 5314 5315
	kfree(wldev);
}

5316
static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5317 5318 5319 5320 5321 5322 5323 5324
{
	struct b43_wldev *wldev;
	int err = -ENOMEM;

	wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
	if (!wldev)
		goto out;

5325
	wldev->use_pio = b43_modparam_pio;
5326
	wldev->dev = dev;
5327 5328 5329 5330 5331 5332 5333 5334 5335
	wldev->wl = wl;
	b43_set_status(wldev, B43_STAT_UNINIT);
	wldev->bad_frames_preempt = modparam_bad_frames_preempt;
	INIT_LIST_HEAD(&wldev->list);

	err = b43_wireless_core_attach(wldev);
	if (err)
		goto err_kfree_wldev;

5336
	b43_bus_set_wldev(dev, wldev);
5337 5338 5339 5340 5341 5342 5343 5344 5345 5346
	b43_debugfs_add_device(wldev);

      out:
	return err;

      err_kfree_wldev:
	kfree(wldev);
	return err;
}

5347 5348 5349 5350 5351 5352
#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice)		( \
	(pdev->vendor == PCI_VENDOR_ID_##_vendor) &&			\
	(pdev->device == _device) &&					\
	(pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) &&	\
	(pdev->subsystem_device == _subdevice)				)

5353
#ifdef CONFIG_B43_SSB
5354 5355
static void b43_sprom_fixup(struct ssb_bus *bus)
{
5356 5357
	struct pci_dev *pdev;

5358 5359
	/* boardflags workarounds */
	if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5360
	    bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5361
		bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5362
	if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5363
	    bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5364
		bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5365 5366
	if (bus->bustype == SSB_BUSTYPE_PCI) {
		pdev = bus->host_pci;
5367
		if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5368
		    IS_PDEV(pdev, BROADCOM, 0x4320,    DELL, 0x0003) ||
5369
		    IS_PDEV(pdev, BROADCOM, 0x4320,      HP, 0x12f8) ||
5370
		    IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5371
		    IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5372 5373
		    IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
		    IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5374 5375
			bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
	}
5376 5377
}

5378
static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5379 5380 5381
{
	struct ieee80211_hw *hw = wl->hw;

5382
	ssb_set_devtypedata(dev->sdev, NULL);
5383 5384
	ieee80211_free_hw(hw);
}
5385
#endif
5386

5387
static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5388
{
5389
	struct ssb_sprom *sprom = dev->bus_sprom;
5390 5391
	struct ieee80211_hw *hw;
	struct b43_wl *wl;
5392
	char chip_name[6];
5393
	int queue_num;
5394 5395 5396 5397

	hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
	if (!hw) {
		b43err(NULL, "Could not allocate ieee80211 device\n");
5398
		return ERR_PTR(-ENOMEM);
5399
	}
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Michael Buesch committed
5400
	wl = hw_to_b43_wl(hw);
5401 5402

	/* fill hw info */
5403
	hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5404
		    IEEE80211_HW_SIGNAL_DBM;
5405

5406 5407 5408 5409 5410 5411 5412
	hw->wiphy->interface_modes =
		BIT(NL80211_IFTYPE_AP) |
		BIT(NL80211_IFTYPE_MESH_POINT) |
		BIT(NL80211_IFTYPE_STATION) |
		BIT(NL80211_IFTYPE_WDS) |
		BIT(NL80211_IFTYPE_ADHOC);

5413 5414
	hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;

5415
	wl->hw_registred = false;
5416
	hw->max_rates = 2;
5417
	SET_IEEE80211_DEV(hw, dev->dev);
5418 5419
	if (is_valid_ether_addr(sprom->et1mac))
		SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5420
	else
5421
		SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5422

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Michael Buesch committed
5423
	/* Initialize struct b43_wl */
5424 5425
	wl->hw = hw;
	mutex_init(&wl->mutex);
5426
	spin_lock_init(&wl->hardirq_lock);
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Michael Buesch committed
5427
	INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5428
	INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
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Michael Buesch committed
5429
	INIT_WORK(&wl->tx_work, b43_tx_work);
5430 5431 5432 5433 5434 5435

	/* Initialize queues and flags. */
	for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
		skb_queue_head_init(&wl->tx_queue[queue_num]);
		wl->tx_queue_stopped[queue_num] = 0;
	}
5436

5437 5438 5439 5440
	snprintf(chip_name, ARRAY_SIZE(chip_name),
		 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
	b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
		dev->core_rev);
5441
	return wl;
5442 5443
}

5444 5445 5446
#ifdef CONFIG_B43_BCMA
static int b43_bcma_probe(struct bcma_device *core)
{
5447
	struct b43_bus_dev *dev;
5448 5449
	struct b43_wl *wl;
	int err;
5450

5451 5452 5453 5454 5455 5456
	if (!modparam_allhwsupport &&
	    (core->id.rev == 0x17 || core->id.rev == 0x18)) {
		pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
		return -ENOTSUPP;
	}

5457 5458 5459 5460
	dev = b43_bus_dev_bcma_init(core);
	if (!dev)
		return -ENODEV;

5461 5462 5463 5464 5465 5466 5467 5468 5469 5470
	wl = b43_wireless_init(dev);
	if (IS_ERR(wl)) {
		err = PTR_ERR(wl);
		goto bcma_out;
	}

	err = b43_one_core_attach(dev, wl);
	if (err)
		goto bcma_err_wireless_exit;

5471 5472 5473
	/* setup and start work to load firmware */
	INIT_WORK(&wl->firmware_load, b43_request_firmware);
	schedule_work(&wl->firmware_load);
5474 5475 5476 5477 5478 5479 5480

bcma_out:
	return err;

bcma_err_wireless_exit:
	ieee80211_free_hw(wl->hw);
	return err;
5481 5482 5483 5484
}

static void b43_bcma_remove(struct bcma_device *core)
{
5485 5486 5487 5488 5489 5490
	struct b43_wldev *wldev = bcma_get_drvdata(core);
	struct b43_wl *wl = wldev->wl;

	/* We must cancel any work here before unregistering from ieee80211,
	 * as the ieee80211 unreg will destroy the workqueue. */
	cancel_work_sync(&wldev->restart_work);
5491
	cancel_work_sync(&wl->firmware_load);
5492

5493
	B43_WARN_ON(!wl);
5494 5495
	if (!wldev->fw.ucode.data)
		return;			/* NULL if firmware never loaded */
5496 5497 5498 5499
	if (wl->current_dev == wldev && wl->hw_registred) {
		b43_leds_stop(wldev);
		ieee80211_unregister_hw(wl->hw);
	}
5500 5501 5502

	b43_one_core_detach(wldev->dev);

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5503 5504 5505
	/* Unregister HW RNG driver */
	b43_rng_exit(wl);

5506 5507 5508
	b43_leds_unregister(wl);

	ieee80211_free_hw(wl->hw);
5509 5510 5511 5512 5513 5514 5515 5516 5517 5518
}

static struct bcma_driver b43_bcma_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= b43_bcma_tbl,
	.probe		= b43_bcma_probe,
	.remove		= b43_bcma_remove,
};
#endif

5519
#ifdef CONFIG_B43_SSB
5520 5521
static
int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5522
{
5523
	struct b43_bus_dev *dev;
5524 5525 5526
	struct b43_wl *wl;
	int err;

5527
	dev = b43_bus_dev_ssb_init(sdev);
5528 5529
	if (!dev)
		return -ENOMEM;
5530

5531
	wl = ssb_get_devtypedata(sdev);
5532 5533 5534 5535
	if (wl) {
		b43err(NULL, "Dual-core devices are not supported\n");
		err = -ENOTSUPP;
		goto err_ssb_kfree_dev;
5536
	}
5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547

	b43_sprom_fixup(sdev->bus);

	wl = b43_wireless_init(dev);
	if (IS_ERR(wl)) {
		err = PTR_ERR(wl);
		goto err_ssb_kfree_dev;
	}
	ssb_set_devtypedata(sdev, wl);
	B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);

5548 5549
	err = b43_one_core_attach(dev, wl);
	if (err)
5550
		goto err_ssb_wireless_exit;
5551

5552 5553 5554
	/* setup and start work to load firmware */
	INIT_WORK(&wl->firmware_load, b43_request_firmware);
	schedule_work(&wl->firmware_load);
5555 5556 5557

	return err;

5558 5559 5560 5561
err_ssb_wireless_exit:
	b43_wireless_exit(dev, wl);
err_ssb_kfree_dev:
	kfree(dev);
5562 5563 5564
	return err;
}

5565
static void b43_ssb_remove(struct ssb_device *sdev)
5566
{
5567 5568
	struct b43_wl *wl = ssb_get_devtypedata(sdev);
	struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5569
	struct b43_bus_dev *dev = wldev->dev;
5570

5571 5572 5573
	/* We must cancel any work here before unregistering from ieee80211,
	 * as the ieee80211 unreg will destroy the workqueue. */
	cancel_work_sync(&wldev->restart_work);
5574
	cancel_work_sync(&wl->firmware_load);
5575

5576
	B43_WARN_ON(!wl);
5577 5578
	if (!wldev->fw.ucode.data)
		return;			/* NULL if firmware never loaded */
5579
	if (wl->current_dev == wldev && wl->hw_registred) {
5580
		b43_leds_stop(wldev);
5581
		ieee80211_unregister_hw(wl->hw);
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Michael Buesch committed
5582
	}
5583

5584
	b43_one_core_detach(dev);
5585

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Larry Finger committed
5586 5587 5588
	/* Unregister HW RNG driver */
	b43_rng_exit(wl);

5589 5590
	b43_leds_unregister(wl);
	b43_wireless_exit(dev, wl);
5591 5592
}

5593 5594 5595 5596 5597 5598 5599 5600
static struct ssb_driver b43_ssb_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= b43_ssb_tbl,
	.probe		= b43_ssb_probe,
	.remove		= b43_ssb_remove,
};
#endif /* CONFIG_B43_SSB */

5601 5602 5603 5604 5605 5606 5607
/* Perform a hardware reset. This can be called from any context. */
void b43_controller_restart(struct b43_wldev *dev, const char *reason)
{
	/* Must avoid requeueing, if we are in shutdown. */
	if (b43_status(dev) < B43_STAT_INITIALIZED)
		return;
	b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5608
	ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5609 5610
}

5611 5612 5613
static void b43_print_driverinfo(void)
{
	const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5614
		   *feat_leds = "", *feat_sdio = "";
5615 5616 5617 5618 5619 5620 5621

#ifdef CONFIG_B43_PCI_AUTOSELECT
	feat_pci = "P";
#endif
#ifdef CONFIG_B43_PCMCIA
	feat_pcmcia = "M";
#endif
5622
#ifdef CONFIG_B43_PHY_N
5623 5624 5625 5626
	feat_nphy = "N";
#endif
#ifdef CONFIG_B43_LEDS
	feat_leds = "L";
5627 5628 5629
#endif
#ifdef CONFIG_B43_SDIO
	feat_sdio = "S";
5630 5631
#endif
	printk(KERN_INFO "Broadcom 43xx driver loaded "
5632
	       "[ Features: %s%s%s%s%s ]\n",
5633
	       feat_pci, feat_pcmcia, feat_nphy,
5634
	       feat_leds, feat_sdio);
5635 5636
}

5637 5638 5639 5640 5641 5642 5643 5644
static int __init b43_init(void)
{
	int err;

	b43_debugfs_init();
	err = b43_pcmcia_init();
	if (err)
		goto err_dfs_exit;
5645
	err = b43_sdio_init();
5646 5647
	if (err)
		goto err_pcmcia_exit;
5648 5649
#ifdef CONFIG_B43_BCMA
	err = bcma_driver_register(&b43_bcma_driver);
5650 5651
	if (err)
		goto err_sdio_exit;
5652
#endif
5653
#ifdef CONFIG_B43_SSB
5654 5655 5656
	err = ssb_driver_register(&b43_ssb_driver);
	if (err)
		goto err_bcma_driver_exit;
5657
#endif
5658
	b43_print_driverinfo();
5659 5660 5661

	return err;

5662
#ifdef CONFIG_B43_SSB
5663
err_bcma_driver_exit:
5664
#endif
5665 5666
#ifdef CONFIG_B43_BCMA
	bcma_driver_unregister(&b43_bcma_driver);
5667
err_sdio_exit:
5668
#endif
5669
	b43_sdio_exit();
5670 5671 5672 5673 5674 5675 5676 5677 5678
err_pcmcia_exit:
	b43_pcmcia_exit();
err_dfs_exit:
	b43_debugfs_exit();
	return err;
}

static void __exit b43_exit(void)
{
5679
#ifdef CONFIG_B43_SSB
5680
	ssb_driver_unregister(&b43_ssb_driver);
5681
#endif
5682 5683 5684
#ifdef CONFIG_B43_BCMA
	bcma_driver_unregister(&b43_bcma_driver);
#endif
5685
	b43_sdio_exit();
5686 5687 5688 5689 5690 5691
	b43_pcmcia_exit();
	b43_debugfs_exit();
}

module_init(b43_init)
module_exit(b43_exit)