• Damien Lespiau's avatar
    drm/i915/skl: Flush the WM configuration · 0e8fb7ba
    Damien Lespiau authored
    When we write new values for the DDB allocation and WM parameters, we now
    need to trigger the double buffer update for the pipe to take the new
    configuration into account.
    
    As the DDB is a global resource shared between planes, enabling or
    disabling one plane will result in changes for all planes that are
    currently in use, thus the need write PLANE_SURF/CUR_BASE for more than
    the plane we're touching.
    
    v2: Don't wait for pipes that are off
    
    v3: Split the staging results structure to not exceed the 1Kb stack
        allocation in skl_update_wm()
    
    v4: Rework and document the algorithm after Ville found that it was all
        wrong.
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    0e8fb7ba
intel_pm.c 204 KB