This commit drops implementation of duplex streams synchronization
from ALSA dice driver, due to a reason of hardware design. This patch
allows dice-based units to generate sounds correctly when isochronous
packet streaming starts at first time.

In IEC 61883-6:2005, CIP packetization layer for AM824 data format
utilizes the value of SYT field in CIP header of received packet for
a reference to phase lock loop. Figure 3 in clause 4.3 describes it.
The value is an offset from cycle_time field of every cycle start packet
from cycle master on IEEE 1394 bus. The time calculated with these two
fields is called as 'presentation timestamp' which represents the time
to play data included in the packet.

Although, this idea includes some problems due to accuracy of timekeep in
cycle master, accuracy of transmission of cycle start packet on the bus
with the other units, accuracy of sampling clock in data transmitter side
and accuracy of replay in data receiver side. In most case, these
accuracies somewhat worse because there's no such ideal hardwares in this
world.

For the issues, ASICs for Dice include Jitter Elimination Technologies
(JET) PLL. The PLL can handle several sources of clock and compensate it
with high-precision internal clock source. The sequence of value in syt
field of received AMDTP packets is one of the sources, therefore
transmitters on IEEE 1394 bus should transfer it.

On the other hand, current ALSA dice driver is programmed with a mode of
duplex streams with synchronization. In this mode, the driver outputs
packets after some incoming packets are handled, to re-use the value of
SYT field in incoming packets to the value for outgoing packets. This mode
is enabled when source signal of sampling clock is set to internal, and
this is a major use case. Thus, in most cases, the unit receives no packets
during a short time after packet streaming starts.

As long as I experienced, this causes the units to generate no sounds at
first time to receive packets. This issue occurs only with Dice II. I guess
this is due to a quirk of the PLL. In short, the PLL cannot generate firm
signals to ADCs/DACs or the other ICs when no packets are received in the
beginning of packet streaming. While, on second time or later, the unit
generates sound correctly. I guess that starting packet streaming at first
time sets the PLL correctly.

Well, still based on my hypothesis and no way to prove it, this commit
drops duplex streams synchronization from this driver. At least, the PLL
requires the sequence of value in SYT field of received AMDTP packets as
one of source of clock signals with internal clock source.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>