The is an issue where setting Relaxed Ordering (RO) bit
(in a PCI-E write transaction) on 82598 causing the chipset
to drop DCA hints.  This patch forces RO not to be set for
descriptors as well as payload.  This will only be in effect
while DCA is enabled and no performance difference was
noticed in testing.
Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>