The clock bindings for Freescale CoreNet platform are updated.
So, the driver needs to be updated accordingly.
The main changes include:
	- Added a new node to present the input system clock
	- Changed PLL and MUX's compatible string
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>