currently, spi irq handler only does rx processing and fetching data from rx
fifo when "FRM_END" irq happens. FRM_END indicates one transfer completes. if
rx size is less than 256, it works well.
but the problem is that spi rx fifo size is only 256 bytes, then if data size
of one frame is more than 256, before FRM_END comes, rx fifo will be filled with
RXFIFO_OFLOW overflow interrupt, it will make us lose some data due to fifo
overflow.
Explicitly we need do fetch work from device rx fifo in irq handler not only in
"FRM_END" irq but also in "THD_REACH" irq. THD_REACH means rx fifo has come to
its threshold and will come to overflow if we don't take data from it in time.

In this patch, we fix this issue. we take data from rx fifo when either FRM_END
or RX_THD_REACH irq comes, we put data into tx fifo when either TX_FIFO_EMPTY
or TX_THD_REACH irq comes.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>