• Heiko Stuebner's avatar
    phy: rockchip-usb: expose the phy-internal PLLs · b74fe7c7
    Heiko Stuebner authored
    The USB phys on Rockchip SoCs contain their own internal PLLs to create
    the 480MHz needed. Additionally this PLL output is also fed back into the
    core clock-controller as possible source for clocks like the GPU or others.
    
    Until now this was modelled incorrectly with a "virtual" factor clock in
    the clock controller. The one big caveat is that if we turn off the usb phy
    via the siddq signal, all analog components get turned off, including the
    PLLs. It is therefore possible that a source clock gets disabled without
    the clock driver ever knowing, possibly making the system hang.
    
    Therefore register the phy-plls as real clocks that the clock driver can
    then reference again normally, making the clock hirarchy finally reflect
    the actual hardware.
    
    The phy-ops get converted to simply turning that new clock on and off
    which in turn controls the siddq signal of the phy.
    
    Through this the driver gains handling for platform-specific data, to
    handle the phy->clock name association.
    Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
    Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
    Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
    b74fe7c7
rockchip-usb-phy.txt 1004 Bytes