Most ATA host controllers follow a standard layout for the
ATA shadow registers, where command/status, error/feature, and
devctl/altstatus share a single bus I/O address, because one register
of each pair is read-only, and the other is write-only.

On the Vitesse/Intel chip, all registers are given distinction bus I/O
addresses, which necessitates changing the libata data structures
to cope with this.  This simply involves storing a few more bus addresses.