• Daniel Vetter's avatar
    drm/i915: Fix up fifo underrun tracking, take N · 2ae2a50c
    Daniel Vetter authored
    So apparently this is tricky.
    
    We need to consider:
    - We start out with all the hw enabling bits disabled, both the
      individual fifo underrun interrupts and the shared display error
      interrupts masked. Otherwise if the bios config is broken we'll blow
      up with a NULL deref in our interrupt handler since the crtc
      structures aren't set up yet at driver load time.
    - On gmch we need to mask fifo underruns on the sw side, so always
      need to set that in sanitize_crtc for those platforms.
    - On other platforms we try to set the sw tracking so that it reflects
      the real state. But since a few platforms have shared bits we must
      _not_ disable fifo underrun reporting. Otherwise we'll never enable
      the shared error interrupt.
    
    This is the state before out patch, but unfortunately this is not good
    enough. But after a suspend resume operation this is broken:
    1. We don't enable the hw interrupts since the same code runs on
    resume as on driver load.
    2. The fifo underrun state adjustments we do in sanitize_crtc doesn't
    fire on resume since (except for hilarious firmware) all pipes are off
    at that point. But they also don't hurt since the subsequent crtc
    enabling due to force_restore will enable fifo underruns.
    
    Which means when we enable fifo underrun reporting we notice that the
    per-crtc state is already correct and short-circuit everthing out. And
    the interrupt doesn't get enabled.
    
    A similar problem would happen if the bios doesn't light up anything
    when the driver loads. Which is exactly what happens when we reload
    the driver since our unload functions disables all outputs.
    
    Now we can't just rip out the short-circuit logic and unconditionally
    update the fifo underrun reporting interrupt masking: We have some
    checks for shared error interrupts to catch issues that happened when
    the shared error interrupt was disabled.
    
    The right fix is to push down this logic so that we can always update
    the hardware state, but only check for missed fifo underruns on a real
    enabled->disabled transition and ignore them when we're already
    disabled.
    
    On platforms with shared error interrupt the pipe CRC interrupts are
    grouped together with the fifo underrun reporting this fixes pipe CRC
    support after suspend and driver reloads.
    
    Testcase: igt/kms_pipe_crc_basic/suspend-*
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    2ae2a50c
i915_irq.c 126 KB