• Chen-Yu Tsai's avatar
    clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops · 5682e268
    Chen-Yu Tsai authored
    When support for the A31/A31s CCU was first added, the clock ops for
    the CLK_OUT_* clocks was set to the wrong type. The clocks are MP-type,
    but the ops was set for div (M) clocks. This went unnoticed until now.
    This was because while they are different clocks, their data structures
    aligned in a way that ccu_div_ops would access the second ccu_div_internal
    and ccu_mux_internal structures, which were valid, if not incorrect.
    
    Furthermore, the use of these CLK_OUT_* was for feeding a precise 32.768
    kHz clock signal to the WiFi chip. This was achievable by using the parent
    with the same clock rate and no divider. So the incorrect divider setting
    did not affect this usage.
    
    Commit 946797aa ("clk: sunxi-ng: Support fixed post-dividers on MP
    style clocks") added a new field to the ccu_mp structure, which broke
    the aforementioned alignment. Now the system crashes as div_ops tries
    to look up a nonexistent table.
    Reported-by: default avatarPhilipp Rossak <embed3d@gmail.com>
    Tested-by: default avatarPhilipp Rossak <embed3d@gmail.com>
    Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
    Cc: <stable@vger.kernel.org>
    Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
    Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
    5682e268
ccu-sun6i-a31.c 39.5 KB