The CEC receive buffer was not always cleared correctly. The
datasheet was a bit confusing since sometimes it mentioned that the
bit in CEC register 0x4a had to be toggled, and sometimes it suggested
it was a 'Clear-on-write' bit. But it really needs to be toggled.

The patch also enables/disables the CEC irqs after the other irq are
enabled/disabled instead of doing it before. It may not matter, but it
feels more logical to do it in that order, and the implementation that
we (Cisco) have used until now and that is known to be reliable also
did it in that order.
Signed-off-by: Hans Verkuil <hansverk@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>