• Michael Ellerman's avatar
    powerpc/64s: Fix masking of SRR1 bits on instruction fault · 475b581f
    Michael Ellerman authored
    On 64-bit Book3s, when we take an instruction fault the reason for the
    fault may be reported in SRR1. For data faults the reason is reported
    in DSISR (Data Storage Instruction Status Register).
    
    The reasons reported in each do not necessarily correspond, so we mask
    the SRR1 bits before copying them to the DSISR, which is then used by
    the page fault code.
    
    Prior to commit b4c001dc ("powerpc/mm: Use symbolic constants for
    filtering SRR1 bits on ISIs") we used a hard-coded mask of 0x58200000,
    which corresponds to:
    
      DSISR_NOHPTE		0x40000000 /* no translation found */
      DSISR_NOEXEC_OR_G	0x10000000 /* exec of no-exec or guarded */
      DSISR_PROTFAULT	0x08000000 /* protection fault */
      DSISR_KEYFAULT	0x00200000 /* Storage Key fault */
    
    That commit added a #define for the mask, DSISR_SRR1_MATCH_64S, but
    incorrectly used a different similarly named DSISR_BAD_FAULT_64S.
    
    This had the effect of changing the mask to 0xa43a0000, which omits
    everything but DSISR_KEYFAULT.
    
    Luckily this had no visible effect, because in practice we hardly use
    the DSISR bits. The lack of DSISR_NOHPTE means a TLB flush
    optimisation was missed in the native HPTE code, and DSISR_NOEXEC_OR_G
    and DSISR_PROTFAULT are both only used to trigger rare warnings.
    
    So we got lucky, but let's fix it. The new value only has bits between
    17 and 30 set, so we can continue to use andis.
    
    Fixes: b4c001dc ("powerpc/mm: Use symbolic constants for filtering SRR1 bits on ISIs")
    Cc: stable@vger.kernel.org # v4.14+
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    475b581f
exceptions-64s.S 48.7 KB