• Catalin Marinas's avatar
    arm64: Fix barriers used for page table modifications · 7f0b1bf0
    Catalin Marinas authored
    The architecture specification states that both DSB and ISB are required
    between page table modifications and subsequent memory accesses using the
    corresponding virtual address. When TLB invalidation takes place, the
    tlb_flush_* functions already have the necessary barriers. However, there are
    other functions like create_mapping() for which this is not the case.
    
    The patch adds the DSB+ISB instructions in the set_pte() function for
    valid kernel mappings. The invalid pte case is handled by tlb_flush_*
    and the user mappings in general have a corresponding update_mmu_cache()
    call containing a DSB. Even when update_mmu_cache() isn't called, the
    kernel can still cope with an unlikely spurious page fault by
    re-executing the instruction.
    
    In addition, the set_pmd, set_pud() functions gain an ISB for
    architecture compliance when block mappings are created.
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Reported-by: default avatarLeif Lindholm <leif.lindholm@linaro.org>
    Acked-by: default avatarSteve Capper <steve.capper@linaro.org>
    Cc: Will Deacon <will.deacon@arm.com>
    Cc: <stable@vger.kernel.org>
    7f0b1bf0
cacheflush.h 4.63 KB