• Jani Nikula's avatar
    drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 · 68f357cb
    Jani Nikula authored
    There is some conflation related to sink rates, making this change more
    complicated than it would otherwise have to be. There are three changes
    here that are rather difficult to split up:
    
    1) Use the intel_dp->sink_rates array for all DP, not just eDP 1.4. We
       initialize it from DPCD on eDP 1.4 like before, but generate it based
       on DP_MAX_LINK_RATE on others. This reduces code complexity when we
       need to use the sink rates; they are all always in the sink_rates
       array.
    
    2) Update the sink rate array whenever we read DPCD, and use the
       information from there. This increases code readability when we need
       the sink rates.
    
    3) Disentangle fallback rate limiting from sink rates. In the code, the
       max rate is a dynamic property of the *link*, not of the *sink*. Do
       the limiting after intersecting the source and sink rates, which are
       static properties of the devices.
    
    This paves the way for follow-up refactoring that I've refrained from
    doing here to keep this change as simple as it possibly can.
    
    v2: introduce use_rate_select and handle non-confirming eDP (Ville)
    
    v3: don't clobber cached eDP rates on short pulse (Ville)
    
    Cc: Manasi Navare <manasi.d.navare@intel.com>
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
    Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/071bad76467f8ab2e73f3f61ad52d5a468004c71.1490712890.git.jani.nikula@intel.com
    68f357cb
intel_dp_link_training.c 8.7 KB