• Keith Busch's avatar
    PCI/DPC: Fix control register setting · 69a3025d
    Keith Busch authored
    This driver was OR'ing desired bits from the existing control setting.
    That could create an invalid DPC Trigger Enabled configuration if the
    platform previously set this to "ERR_FATAL", 01b.  The driver currently
    wants to set this to ERR_NONFATAL/ERR_FATAL, 10b, and the logical OR of
    this gets 11b, which is reserved.  Fix that by masking off the fields it is
    setting.
    Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
    Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
    69a3025d
pcie-dpc.c 5.19 KB