• Vineet Gupta's avatar
    ARC: [axs101] Tweak DDR port aperture mappings for performance · 749aa0e1
    Vineet Gupta authored
    Route all MB originated traffic to DDR Port 1 and keep Port 0 for CPU
    traffic only
    
    Basic system parameters
    --------------------------------------------------------------------------------------
            Host                 OS Description 				Mhz  tlb   cache  mem   scal
                                                    			    pages  line   par   load
                                                          				   bytes
    ----------------- ------------- --------------------------------------- ---- ----- ----- ------ ----
    axs101-sd-2-new-f Linux 3.13.0+ axs101-sd-2-new-fw-old-img-rerun    	739  	8    32 1.1100    1
    axs101-sd-3-arc-3 Linux 3.13.9+ axs101-sd-3-arc-3.13-tip-regression 	735  	8    32 1.1000    1
    axs101-sd-9-diffe Linux 3.13.11 axs101-sd-9-different-tweak         	740  	8    32 1.0000    1
    
    Processor, Processes - times in microseconds - smaller is better
    ------------------------------------------------------------------------------
    Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                                 call  I/O stat clos TCP  inst hndl proc proc proc
    --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    axs101-sd Linux 3.13.0+  739 0.50 0.88 5.38 14.6 34.1 0.92 5.18 2135 6555 12.K
    axs101-sd Linux 3.13.9+  735 0.50 0.90 5.89 19.2 81.4 0.94 4.08 2560 8559 15.K
    axs101-sd Linux 3.13.11  740 0.50 0.88 4.45 17.8 34.4 0.94 3.25 2052 6493 12.K
                                                     ^^^^                     ^^^^
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    749aa0e1
axs10x.c 9.03 KB