Because of its shallow queues and limited reordering ability, the i.MX6Q
memory controller likes AXI bursts of consecutive addresses a lot.
To optimize memory access performance, lock the IPU scanout channels for
a number of burst accesses each, before switching to the next channel.
The burst size and length of a locked burst chain are chosen not to
overshoot the stride.

Enabling the 8-burst channel lock on a single 1920x1080@60Hz RGBx
scanout (474 MiB/s of 64-byte IPU memory read accesses) reduces the
reported memory controller busy cycles from 46% to below 28% on an
otherwise idle i.MX6Q.
Tested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>