• Oliver O'Halloran's avatar
    powerpc/timer: Large Decrementer support · 79901024
    Oliver O'Halloran authored
    Power ISAv3 adds a large decrementer (LD) mode which increases the size
    of the decrementer register. The size of the enlarged decrementer
    register is between 32 and 64 bits with the exact size being dependent
    on the implementation. When in LD mode, reads are sign extended to 64
    bits and a decrementer exception is raised when the high bit is set (i.e
    the value goes below zero). Writes however are truncated to the physical
    register width so some care needs to be taken to ensure that the high
    bit is not set when reloading the decrementer. This patch adds support
    for using the LD inside the host kernel on processors that support it.
    
    When LD mode is supported firmware will supply the ibm,dec-bits property
    for CPU nodes to allow the kernel to determine the maximum decrementer
    value. Enabling LD mode is a hypervisor privileged operation so the kernel
    can only enable it manually when running in hypervisor mode. Guests that
    support LD mode can request it using the "ibm,client-architecture-support"
    firmware call (not implemented in this patch) or some other platform
    specific method. If this property is not supplied then the traditional
    decrementer width of 32 bit is assumed and LD mode will not be enabled.
    
    This patch was based on initial work by Jack Miller.
    Signed-off-by: default avatarOliver O'Halloran <oohall@gmail.com>
    Signed-off-by: default avatarBalbir Singh <bsingharora@gmail.com>
    Acked-by: default avatarMichael Neuling <mikey@neuling.org>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    79901024
reg.h 56.5 KB