• A.s. Dong's avatar
    clk: imx: add pfdv2 support · 9fcb6be3
    A.s. Dong authored
    The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
    Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
    
    NOTE pfdv2 can only be operated when clk is gated.
    
    Cc: Stephen Boyd <sboyd@codeaurora.org>
    Cc: Michael Turquette <mturquette@baylibre.com>
    Cc: Shawn Guo <shawnguo@kernel.org>
    Cc: Anson Huang <Anson.Huang@nxp.com>
    Cc: Bai Ping <ping.bai@nxp.com>
    Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
    [sboyd@kernel.org: Include clk.h for sparse warnings]
    Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
    9fcb6be3
clk.h 7.69 KB