• Claudiu Manoil's avatar
    arm64: dts: ls1028a: add node for Felix switch · b1520d8b
    Claudiu Manoil authored
    Add the switch device node, available on PF5, so that the switch port
    sub-nodes (net devices) can be linked to corresponding board specific
    phy nodes (external ports) or have their link mode defined (internal
    ports).
    
    The switch device features 6 ports, 4 with external links and 2
    internally facing to the LS1028A SoC and connected via fixed links to 2
    internal ENETC Ethernet controller ports.
    
    Add the corresponding ENETC host port device nodes, mapped to PF2 and
    PF6 PCIe functions. Since the switch only supports tagging on one CPU
    port, only one port pair (swp4, eno2) is enabled by default and the
    other, lower speed, port pair is disabled to prevent the PCI core from
    probing them. If enabled, swp5 will be a fixed-link slave port.
    
    DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the
    1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to
    <&enetc_port3> and moving it under port5, but in that case enetc_port2
    should not be disabled, because it is the hardware owner of the Felix
    PCS and disabling its memory would result in access faults in the Felix
    DSA driver.
    
    All ports are disabled by default, including the CPU port, and need to
    be enabled on a per-board basis.
    
    The phy-mode binding of the internal ENETC ports was modified from
    "gmii" to "internal" to match the phy-mode of the internal-facing switch
    ports connected to them. The ENETC driver does not perform any phy_mode
    validation anyway, so the change is only cosmetic. Also, enetc_port2 is
    defined as a fixed-link 1000 Mbps port even though it is 2500 Mbps (as
    can be seen by the fact that it is connected to mscc_felix_port4). The
    fact that it is currently defined as 1000 Mbps is an artifact of its
    PHYLIB implementation instead of PHYLINK (the former can't describe a
    fixed-link speed higher than what swphy can emulate from the Clause 22
    MDIO spec).
    
    The switch's INTB interrupt line signals:
    - PTP TX timestamp availability
    - TSN Frame Preemption
    
    And don't forget to enable the 4MB BAR4 in the root complex ECAM space,
    where the switch registers are mapped.
    Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
    Signed-off-by: default avatarAlex Marginean <alexandru.marginean@nxp.com>
    Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
    Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
    Tested-by: default avatarMichael Walle <michael@walle.cc>
    Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
    b1520d8b
fsl-ls1028a.dtsi 24 KB