• Paulo Zanoni's avatar
    drm/i915: fix CFB size calculation · c4ffd409
    Paulo Zanoni authored
    We were considering the whole framebuffer height, but the spec says we
    should only consider the active display height size. There were still
    some unclear questions based on the spec, but the hardware guys
    clarified them for us. According to them:
    
    - CFB size = CFB stride * Number of lines FBC writes to CFB
    - CFB stride = plane stride / compression limit
    - Number of lines FBC writes to CFB = MIN(plane source height, maximum
      number of lines FBC writes to CFB)
    - Plane source height =
      - pipe source height (PIPE_SRCSZ register) (before SKL)
      - plane size register height (PLANE_SIZE register) (SKL+)
    - Maximum number of lines FBC writes to CFB =
      - plane source height (before HSW)
      - 2048 (HSW+)
    
    For the plane source height, I could just have made our code do
    I915_READ() in order to be more future proof, but since it's not cool
    to do register reads I decided to just recalculate the values we use
    when we actually write to those registers.
    
    With this patch, depending on your machine configuration, a lot of the
    kms_frontbuffer_tracking subtests that used to result in a SKIP due to
    not enough stolen memory still start resulting in a PASS.
    
    v2: Use the clipped src size instead of pipe_src_h (Ville).
    v3: Use the appropriate information provided by the hardware guys.
    v4: Bikesheds: s/sizes/size/, s/fb_cpp/cpp/ (Ville).
    v5: - Don't use crtc->config->pipe_src_x for BDW- (Ville).
        - Fix the register name written in the comment.
    Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    c4ffd409
intel_fbc.c 30.5 KB